JP2527066B2 - Reception queue processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing device for performing distributed processing of a central processing device, and more particularly to a queue of the central processing device mounted in a switching device of a data communication system. The present invention relates to a reception queue processing device for decentralized control.

[Conventional technology]

In an electronic exchange in a general data communication system, a large number of same processing requests or different processing requests are generated from a plurality of terminals in a short time, but these requests cannot be processed at the same time. You need to make a line and wait for the turn. Specifically, necessary processing is written in each transaction and registered in a queue, but as a processing method thereof, so-called first-in-first-out (FIFO) is generally used, which performs processing on a first-come-first-served basis.

Conventionally, processing control of this type of reception queue has been performed by software installed in a central processing unit.

[Problems to be Solved by the Invention]

As described above, since the conventional reception queue processing control is performed by the software installed in the central processing unit, there is a drawback that the load on the central processing unit becomes heavy. Also, the time required for each processing is determined by the processing capacity of the central processing unit, but if an excessive state occurs in which a large amount of data is concentrated and received especially in a short time, the queue take-up processing is performed after reception. The waiting time until it is done becomes long. For this reason, there is a drawback in that the subsequent received data may be missing. In this case, although there is a means for recovering the lost data by re-transmission, this will reduce the data transfer processing speed. Also, especially for voice or image data,
In the case of data in which the real-time property is more important than the quality of individual data, the loss of data will lead to deterioration of the quality as a whole.

Therefore, an object of the present invention is to provide a reception queue processing device capable of performing a queue processing control so as to prevent omission of received data.

[Means for solving the problem]

In the invention according to claim 1, (i) an empty block number assigned to an empty block of a reception buffer memory for storing received data in block units divided into arbitrary sizes is in the form of a queue. Empty block number storage means for sequentially storing, and (ii) processing for sequentially storing processing waiting block numbers, which are the numbers of blocks used for storing received data and waiting for a predetermined processing, in the reception buffer memory in the form of a queue A waiting block number storage means, (iii) an empty block number control unit for controlling storage and retrieval of an empty block number to and from an empty block number storage means, and a storage waiting block number storage and retrieval to and from the processing waiting block number storage means The reception queue processing device is provided with a reception processing control means including a processing waiting block number control unit for controlling.

In the invention according to claim 1, the receiving processing control means controls the storage and retrieval of the empty block number and the processing waiting block number to achieve the object.

In the invention according to claim 2, (i) a reception buffer memory for storing reception data in block units divided into arbitrary sizes, and (ii) a central processing unit for processing the reception data stored in the reception buffer memory. A processing device, and (iii) empty block number storage means for sequentially storing in block form the block numbers assigned to the empty blocks among the blocks of the reception buffer memory as empty block numbers,
(Iv) empty block number fetching means for fetching empty block numbers from the empty block number storage means when data is received; and (v) fetching by empty block number fetching means in the receive buffer memory. Received data transfer means for transferring received data to a block corresponding to an empty block number, and (vi) received data storage block number which is the number of the block in which the received data transferred by this received data transfer means is stored. Means for sequentially storing the received data in the form of a queue, and (vi
i) reception completion signal output means for outputting to the central processing unit a reception completion signal indicating that reception of the reception data is completed when the storage of the reception data storage block number in the reception data storage block number storage means is completed. To the reception queue processing device.

According to the second aspect of the present invention, the received data is stored in an empty block of the reception buffer memory, and the corresponding block number is taken out from the empty block storage means and stored in the received data storage block number storage means. To the central processing unit to achieve that purpose.

〔Example〕

 The present invention will be described in detail below with reference to examples.

FIG. 1 shows a reception queue processing device according to an embodiment of the present invention. This device includes a central processing unit (hereinafter referred to as CPU) 11 and a local bus 12
Is connected to the main bus 13 via. This main bus 13 has a reception buffer memory 15 for storing reception data.
And a reception processing control unit 16 for controlling reception processing are connected via local buses 17 and 18, respectively. A reception completion notification signal 19 is output from the reception processing control unit 16 and input to the CPU 11.

The main bus 13 is also connected to the address control unit 22 in the reception interface unit 21, and the received data is transmitted via this.
23 is entered. The reception interface unit 21 is provided with a reception queue 24 and an empty reception buffer queue 25, which are connected to the address control unit 22 and the local bus 27 to the reception processing control unit 16. The reception queue 24 and the empty reception buffer queue 25 are constituted by a first-in first-out (FIFO) memory.

The empty reception buffer queue 25 has an interrupt signal output unit.
26 is connected, and a reception interrupt signal 28 is sent to the reception processing control unit 16.

FIG. 2 shows the internal structure of the reception buffer memory 15 of FIG. The reception buffer memory 15 is divided into n blocks having an arbitrary buffer size, and is handled in block units based on the numbers given to the blocks. These block numbers are used as queuing information in the reception queue 24 and the empty reception buffer queue 25 in the reception interface 21. That is, the empty block numbers, which are the numbers of empty blocks, are sequentially stored in the empty reception buffer queue 25.
And the received data is stored in the CPU 11 (first
Processing waiting block numbers, which are the numbers of blocks waiting for processing according to the drawing), are sequentially stored in the reception queue 24. Here, it is assumed that the n blocks in the reception buffer memory 15 are used sequentially from the first block 0 to the last block n, and the block n is returned to the block 0.

The operation of the reception queue processing device having the above configuration will be described.

FIG. 3 shows the contents of the reception queue 24 and the empty reception buffer queue 25 in the initial state.
As shown in this figure, in the initial state, all blocks in the receive buffer memory 15 (Fig. 1) are empty, so the empty receive buffer queue 25 has block numbers from "O" to "n". Is stored. At this time,
No block number is stored in the reception queue 24.

In this state, the received data 23 is received by the receiving interface unit 21.
The address control unit 22 fetches the first empty block number stored in the empty reception buffer queue 25 and calculates the address of the corresponding block of the reception buffer memory 15 based on this. To do. Then, the received data 23 is transferred to and stored in the corresponding block of the receive buffer memory 15 via the main bus 13. At this time, the empty block number fetched by the address controller 22 is also stored in the reception queue 24. Here, as shown in FIG. 4, the empty block number “O” at the head of the empty reception buffer queue 25 is stored at the head of the reception queue 24.
Upon detecting this, the interrupt signal output unit 26 sends a reception interrupt signal 28 to the reception processing control unit 16.

Receiving this, the reception processing control unit 16 performs a series of preset processes. That is, the block number waiting to be processed is fetched from the reception queue 24 via the local bus 27, and a new empty block number is replenished to the empty reception buffer queue 25. Here, the block number "O" is fetched, but a new empty block number is not replenished. After that, the reception interrupt signal 28 from the interrupt signal output unit 26 is reset and the CPU 11 receives the reception completion notification signal 1
Sends 9.

FIG. 5 shows the contents of the reception queue 24 and the empty reception buffer queue 25 at the time when the reception processing from block 0 to block 4 of the reception buffer memory 15 is performed. As shown in this figure, since the processing by the CPU 11 has finished for blocks 0 and 1 and have become empty blocks, these block numbers are newly stored in the empty reception buffer queue 25. Further, the block numbers of blocks 2 to 4 are stored in the reception queue 24, and indicate the state of waiting for processing by the CPU 11.

In this way, in the present embodiment, the order control for storing the received data in the reception buffer memory is performed by the reception interface section and the reception processing control section, so that the CPU simply executes the predetermined processing after receiving the reception completion notification. All you have to do is do it.

〔The invention's effect〕

As described above, according to the present invention, the order control for storing the reception data in the reception buffer memory is performed by the hardware independent of the central processing unit, so that the reception of data is concentrated in a short time. Even in the state, the processing of the queue can be performed in real time, so that there is an effect that the loss of received data, which has been a problem in the past, does not occur.

Further, since the software processing which has conventionally depended on the central processing unit is not performed, there is an effect that the load on the central processing unit can be reduced.

[Brief description of drawings]

The drawings are for explaining one embodiment of the present invention, in which FIG. 1 is a block diagram showing a reception queue processing device,
FIG. 2 is an explanatory view showing the inside of the reception buffer memory of FIG. 1, FIG. 3 is an explanatory view showing the states of the reception queue and the empty reception buffer queue in the initial state, and FIG. 4 is the first block. Explanatory diagram showing the state of the reception queue and empty reception buffer queue at the time of performing the process,
FIG. 5 is an explanatory diagram showing the states of the reception queue and the empty reception buffer queue at the time when the reception processing is performed for blocks 0 to 4. 11 ... CPU, 15 ... Reception buffer memory, 16 ... Reception processing control section, 21 ... Reception interface section, 22 ... Address control section, 24 ... Reception queue, 25 ... Empty reception buffer queue, 26 …… Interrupt signal output section.

Claims (2)

(57) [Claims] 1. An empty block number for sequentially storing, in the form of a queue, empty block numbers assigned to empty blocks in a receive buffer memory that stores received data in blocks divided into arbitrary sizes. Storage means, processing wait block number storage means for sequentially storing, in the form of a queue, processing wait block numbers, which are numbers of blocks used to store received data and waiting for predetermined processing, in the reception buffer memory; An empty block number control unit for controlling storage and retrieval of the empty block number in the empty block number storage unit, and a processing waiting block number for controlling storage and retrieval of the processing waiting block number in the processing waiting block number storage unit A reception queue processing device, comprising: a reception processing control means including a control unit. 2. A reception buffer memory for storing reception data in block units divided into arbitrary sizes, a central processing unit for processing the reception data stored in the reception buffer memory, and the reception buffer memory An empty block number storage means for sequentially storing in the form of a queue the block number given to an empty block among the blocks as an empty block number, and an empty block number from the empty block number storage means when data is received. And a received data transfer for transferring the received data to a block in the reception buffer memory corresponding to an empty block number acquired by the empty block number acquisition means. Means and the block number in which the received data transferred by this received data transfer means is stored Reception data storage block number storage means for sequentially storing a reception data storage block number in the form of a queue, and the central processing when the storage of the reception data storage block number in the reception data storage block number storage means is completed. A reception completion signal output means for outputting a reception completion signal indicating that the reception of the reception data has been completed to the device, the reception queue processing device.