JPS6151256A - Receiving data transfer control system - Google Patents

Abstract

PURPOSE:To improve the efficiency of data buffer area and reduce the number of interrupt lines to control programs by subdividing the data buffer areas for storing the receiving data. CONSTITUTION:A buffer control part 2 holds the buffer information on the idle data buffer currently not in use among several data buffer areas allocated to a memory part 1. The control part 2 is a cue of first-in first-out system, and provides a wire/read pointer 13 and 14. When the request to allocate data buffer areas occurs from a transfer control part 5 through a common bus 7, the buffer information 0 is returned via the bus 7, and the pointer 14 is incremented by +1. The control part 5 receives the returned information 0, and performs data transfer using the data buffer area 0 on the memory part 1 specified by that information. The buffer information format contains the beginning address BFAI, the area length BLFI, and unused bits (always 0) of the buffer area.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a data transfer control method in an information processing device or a communication control processing device, etc. The present invention relates to a received data transfer control method for efficiently transferring received data from a terminal device or other information processing device to a data buffer area on a storage unit and notifying a control program.

(b) Conventional technology In a communication control processing device that controls multiple communication lines, conventionally, a data buffer area larger than the maximum received data length is allocated for each line, and when data received from the line is In some cases, even if the received data arrives, the received data is prepared so that it can be immediately stored in the data buffer area. In this method, the following two points are wasteful in the way the data buffer area is used. The first point is that even though it is almost impossible for received data to arrive from all lines at the same time, a data buffer area is always prepared for it. The second point is that although the normal reception data length is considerably shorter than the maximum length, a data buffer area that is longer than the maximum reception data length is always prepared.

In order to improve these wastes, a buffer control unit that holds multiple pieces of buffer information is provided, and the data buffer area is subdivided into pieces approximately a fraction of the maximum received data length and registered in the buffer control unit. When the received data from the line arrives and a data buffer area is needed to store it, the transfer control unit receives the registered buffer information from the buffer control unit and uses that buffer to store the information. A method has been devised to store received data in a designated data buffer area. here,
The buffer information includes, for example, the start address of the data buffer area and the length of the data buffer area.

(c) Problems to be solved by the invention In this method, only the line on which the received data has arrived uses the data buffer area, and only a small number of data buffer areas are used for short received data. The efficiency of buffer area usage is greatly improved.

However, with regard to the number of interrupts that the transfer control unit makes to notify the control program of the data buffer area where the received data is stored, conventionally it was only required once for each received data, but with this method, Since the data buffer area is subdivided, it is generally required multiple times. As a result, the load on the control program increases, resulting in a problem of reduced processing capacity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reception data transfer control system that improves the drawbacks of the prior art described above, has high data buffer area usage efficiency, and reduces the number of interrupts to a control program.

(d) Means for solving the problem A storage section, a processor section that executes a control program stored in the storage section, a buffer control section that holds a plurality of buffer information, and an input terminal connected thereunder. When receiving data from the output device, it receives sofa information from the buffer control section, stores the received data in a data buffer area on the storage section specified by the buffer information, and requests an interrupt to the processor section. In a data transfer system comprising a transfer control unit that notifies a control program, when receiving data from the input/output device, the transfer control unit stores the received data in one or more data buffer areas depending on the length of the data. A chain of buffer information indicating the one or more data buffer areas is stored on the storage unit, and a storage position of the chain of buffer information is notified to the control program.

(e) Effects According to the present invention, the control program can identify the storage position of the chain of buffer information with only one notification, and the control program can continuously process the entire received data area. Become.

(F) Embodiment FIG. 1 shows a block configuration of a communication control processing device according to an embodiment of the present invention. Here, the storage unit 1 includes a control program,
Control information, transmission/reception data, etc. are stored. The processor unit 4 reads and executes commands of a control program stored in the storage unit 1, and controls the entire communication control processing device. It also performs an interrupt operation in response to an interrupt request notified via the interrupt request signal line 8.9. The upper level interface unit 3 transfers data between the higher level device and this communication control processing device under the control of the control program. The transfer control unit 5 transfers data between the plurality of connected lines 10 to 11 and the present communication control processing device under the control of a control program. The buffer control unit 2 retains buffer information regarding empty data buffer areas that are currently not in use among the plurality of data buffer areas allocated on the storage unit 1, and responds to data buffer area allocation requests from other modules. Allocate empty data buffer area. Here, the other modules are the upper interface control unit 3. Refers to the processor section 4 and transfer control section 5.

Further, it is assumed that the control program returns a data buffer area that is no longer needed after it has been allocated to the buffer control unit 2. Further, the common bus 7 is a bus for transferring data between modules within this communication control processing device.

The configuration of the buffer control section 2 is shown in FIG. The buffer control memory 12 is a first-in, first-out queue that holds buffer information regarding a plurality of empty data buffer areas, and has a write pointer 13 and a read pointer 14 as address pointers for controlling the queue. FIG. 2 shows a state in which buffer information regarding n+1 empty data buffer areas of buffer information i10-n is held. Now, when a data buffer area allocation request is generated from the transfer control unit 5 via the common bus 7, buffer information 0 is returned via the common bus 7 and the contents of the read pointer 14 are incremented by 1. The transfer control unit 5 receives the returned buffer information @0 and performs data transfer using the data buffer area 0 on the storage unit 1 specified by the information. As shown in FIG. 2, the format of the buffer information includes the start address BFAI of the data buffer area, the length BFL I of the data buffer area, and the leftmost unused bit (always set to "0"). However, I
=O, -.

It is n.

Now, when the transfer control section 5 receives received data as shown in FIG. 3 from the line, the operation is as follows, and the data is stored in the storage section 1 as shown in FIG. 4.

(2) Data buffer area 0 is allocated to store a chain of buffer information indicating multiple data buffer areas in which received data is stored.

■ To store the received data, data buffer area 1 is allocated and the RDA at the beginning of the received data is stored there.
Store the TAI part.

(2) After storing received data until data buffer area 1 becomes full, buffer information indicating data buffer area 1 is stored at the beginning of data buffer area 0. Here, the leftmost bit is used as a chain bit of buffer information, "°O" in the middle of the chain, and "1" at the end of the chain.
shall be.

(2) Upon receiving the allocation of the data buffer area 2, storage of received data in the data buffer area and storage of buffer information indicating the data buffer area are performed in the same manner as in (2) and (3).

■ Perform the same procedure as ■ for data buffer area 3.

(2) Receive the allocation of the data buffer area 4 and store the RDATA4 portion of the received data there.

(2) When the end of the received data is detected, the buffer information indicating the data buffer area 4 is stored at the end of the chain of buffer information in the data buffer area O.

In this case, the leftmost heso information chain bit is °“1
", and as the data buffer area length, the value of the length DTAL4 of the stored received data RDATA4 is stored instead of the actual data buffer area length BFL4.

(2) Interrupt cause information including buffer information of the data buffer area O is held in an interrupt cause register (not shown) in the transfer control unit 5, and an interrupt is requested to the processor unit 4 via the signal line 9.

As a result, the interrupt processing routine of the control program is started, and the contents of the interrupt cause register (not shown) in the transfer control unit 5 are read out via the common bus 7, and the data from the line is received. It is known that the data has been stored in the data buffer area specified by the chain of buffer information in data buffer area O.

In the embodiment described above, it has been explained that the transfer control unit 5 holds interrupt cause information in the interrupt cause register and requests an interrupt from the processor unit 4, but since it controls multiple lines, Since interrupt factors may occur consecutively, the transfer control unit 5 or processor unit 4
It is preferable to provide a queue in which a plurality of pieces of interrupt factor information can be held on a first-come, first-served basis.

Further, the buffer control memory 12 of the buffer control unit 2 may be configured to use a specific area on the storage unit 1, and in this case, the amount of hardware in the buffer control unit 2 can be reduced. can.

(G) Effects of the Invention According to the present invention, by dividing the data buffer area for storing received data into smaller parts, the data buffer area can be used efficiently and the number of interruptions to the control program can be reduced. This is effective in improving the processing capacity of information processing devices, communication control processing devices, etc.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the block configuration of a communication control processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a buffer control unit, and FIG. 3 is a diagram showing received data and a data buffer area in which it is stored. FIG. FIG. 4 is a diagram showing a chain of buffer information stored in the data buffer area on the storage unit and received data. In the figure, 1 is a storage section, 2 is a buffer control section, 4 is a processor section, 5 is a transfer control section, and 12 is a buffer control memory. σ・−′1・・

Claims (2)

[Claims] (1) When receiving data from a storage unit, a processor unit that executes a control program stored in the storage unit, a buffer control unit that holds a plurality of buffer information, and an input/output device connected thereto, receiving buffer information from the buffer control unit and storing the received data in a data buffer area on the storage unit specified by the buffer information;
In a data transfer system comprising a transfer control unit that requests an interrupt from the processor unit and notifies the control program, when receiving data from the input/output device, the transfer control unit converts the received data into one data according to its length. a chain of buffer information indicating the one or more data buffer areas is stored on the storage unit, and the storage position of the chain of buffer information is determined by the control program. A reception data transfer control method characterized by notification. (2) The reception according to claim (1), wherein the buffer information includes at least information indicating the start address of the corresponding data buffer area and the length of the data buffer area. Data transfer control method.