JPH0439700B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a data transfer control method in an information processing device or a communication control processing device, etc. The present invention relates to a received data transfer control method for efficiently transferring received data from a terminal device or other information processing device to a data buffer area on a storage unit and notifying a control program.

(b) Conventional technology Conventionally, in a communication control processing device that controls multiple communication lines, a data buffer area larger than the maximum received data length is allocated for each line, and it is determined when the received data from the line arrives. However, in some cases, the received data is prepared so that it can be immediately stored in the data buffer area.
In this method, the following two points were wasteful in the way the data buffer area was used. The first point is
Even though it is almost impossible for received data to arrive from all lines at the same time, a data buffer area is always prepared for it. The second point is that although the normal received data length is considerably shorter than the maximum length, a data buffer area that is longer than the maximum received data length is always prepared.

In order to improve these wastes, a buffer control section that holds a plurality of pieces of buffer information is provided, and the data buffer area is subdivided into a size of about a fraction of the maximum received data length and registered in the buffer control section. When received data from the line arrives and a data buffer area is required to store it, the transfer control unit receives the registered buffer information from the buffer control unit and specifies the data buffer area specified by the buffer information. A method has been devised for storing received data in a data buffer area. Here, the buffer information includes, for example, the start address of the data buffer area and the length of the data buffer area.

(c) Problems to be solved by the invention In this method, only the line on which the received data has arrived uses the data buffer area, and only a small number of data buffer areas are used for short received data, so the data buffer area is Usage efficiency is greatly improved.

However, with regard to the number of interrupts that the transfer control unit makes to notify the control program of the data buffer area where the received data is stored, conventionally it was only required once for each received data, but in this method, the data buffer area is Because the area is subdivided,
Generally required multiple times. As a result, the load on the control program increases, resulting in a problem of reduced processing capacity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a received data transfer control system that improves the drawbacks of the prior art described above, has high data buffer area usage efficiency, and reduces the number of interrupts to a control program.

(d) Means for solving the problem A storage section, a processor section that executes a control program stored in the storage section, a buffer control section that holds a plurality of pieces of buffer information, and an input device connected thereunder. The data receiving unit from the output device receives buffer information from the buffer control unit, stores the received data in a data buffer area on the storage unit specified by the buffer information, and requests an interrupt to the processor unit. In a data transfer system consisting of a transfer control unit that notifies a control program, when receiving data from the input/output device, the transfer control unit converts the received data into 1 bits according to the length of the data.
store in one or more data buffer areas, store a chain of buffer information indicating the one or more data buffer areas on the storage unit, and notify the control program of the storage position of the chain of buffer information. It is characterized by

(e) Effects According to the present invention, the control program can identify the storage location of the buffer information chain with only one notification, and the control program can continuously process the entire received data area. Become.

(f) Embodiment FIG. 1 shows a block configuration of a communication control processing device according to an embodiment of the present invention. Here, the storage unit 1 stores control programs, control information, transmission/reception data, and the like. The processor section 4 reads and executes commands of the control program stored in the storage section 1, and controls the entire communication control processing device. In addition, an interrupt operation is performed in response to an interrupt request notified via interrupt request signal lines 8 and 9. The higher-level interface unit 3 transfers data between the higher-level device and this communication control processing device under the control of the control program. The transfer control unit 5 transfers data between the plurality of connected lines 10 to 11 and the present communication control processing device under the control of a control program. The buffer control unit 2 retains buffer information regarding empty data buffer areas that are currently not in use among a plurality of data buffer areas allocated on the storage unit 1, and stores buffer information regarding empty data buffer areas in response to data buffer area allocation requests from other modules. Allocates data buffer area. Here, other modules are
This refers to the upper interface control section 3, processor section 4, and transfer control section 5. Furthermore, once allocated, the data buffer area that is no longer needed is returned to the buffer control unit 2 by the control program. Further, the common bus 7 is a bus for transferring data between modules within this communication control processing device.

The configuration of the buffer control section 2 is shown in FIG. The buffer control memory 12 is a first-in, first-out queue that holds buffer information regarding a plurality of empty data buffer areas, and has a write pointer 13 and a read pointer 14 as address pointers for controlling the queue. FIG. 2 shows a state in which buffer information regarding n+1 empty data buffer areas of buffer information 0 to n is held. Now, when a data buffer area allocation request is generated from the transfer control unit 5 via the common bus 7, buffer information 0 is returned via the common bus 7 and the contents of the read pointer 14 are incremented by 1. The transfer control unit 5 receives the returned buffer information 0 and performs data transfer using the data buffer area 0 on the storage unit 1 specified by the information. The format of the buffer information, as shown in FIG. 2, includes the start address BFAI of the data buffer area, the length BFLI of the data buffer area, and an unused bit at the left end (always set to "0"). However, I=0,...n.

Now, when the transfer control section 5 receives received data as shown in FIG. 3 from the line, the operation is as follows, and the data is stored in the storage section 1 as shown in FIG. 4.

Data buffer area 0 is allocated to store a chain of buffer information indicating a plurality of data buffer areas storing received data.

In order to store the received data, data buffer area 1 is allocated, and the RDATA1 portion at the beginning of the received data is stored there.

After storing the received data until data buffer area 1 becomes full, buffer information indicating data buffer area 1 is stored at the beginning of data buffer area 0. Here, the leftmost bit is used as a chain bit of buffer information, and is set to "0" in the middle of the chain and "1" at the end of the chain.

Upon receiving the allocation of the data buffer area 2, storing the received data in the data buffer area;
Buffer information indicating the relevant data buffer area is stored in the same manner as in .

The same process as for data buffer area 3 is performed.

After receiving the allocation of the data buffer area 4, the RDATA4 portion of the received data is stored there.

When the end of the received data is detected, buffer information indicating data buffer area 4 is stored at the end of the chain of buffer information in data buffer area 0. In this case, the leftmost buffer information chain bit is set to "1", and the data buffer area length is the length of the stored received data RDATA4 instead of the actual data buffer area length BFL4.
Store the value of DTAL4.

Interrupt cause information including buffer information of data buffer area 0 is held in an interrupt cause register (not shown) in transfer control section 5, and an interrupt is requested to processor section 4 via signal line 9.

As a result, the interrupt processing routine of the control program is activated, reads the contents of the interrupt cause register (not shown) in the transfer control unit 5 via the common bus 7, and confirms that data from the line has been received. is stored in the data buffer area specified by the chain of buffer information in data buffer area 0.

In the embodiment described above, it has been explained that the transfer control unit 5 holds interrupt cause information in the interrupt cause register and requests an interrupt from the processor unit 4, but since it controls multiple lines, Since interrupt factors may occur consecutively, the transfer control unit 5 or processor unit 4 may have
It is preferable to provide a queue capable of holding a plurality of pieces of interrupt factor information on a first-come, first-served basis.

Furthermore, the buffer control memory 12 of the buffer control unit 2 may be configured to use a specific area on the storage unit 1; in this case,
The amount of hardware in the buffer control section 2 can be reduced.

(G) Effects of the Invention According to the present invention, by dividing the data buffer area for storing received data into smaller parts, the data buffer area can be used efficiently, and the number of interrupts to the control program can be reduced, thereby improving information processing. This is effective in improving the processing capacity of devices, communication control processing devices, etc.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the block configuration of a communication control processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a buffer control section, and FIG. 3 is a diagram showing received data and a data buffer area in which it is stored. Diagram showing correspondence,
FIG. 4 is a diagram showing a chain of buffer information stored in a data buffer area on a storage unit and received data. In the figure, 1 is a storage section, 2 is a buffer control section, 4 is a processor section, 5 is a transfer control section, and 12 is a buffer control memory.

Claims (1)

[Scope of Claims] 1. A storage unit, a processor unit that executes a control program stored in the storage unit, a buffer control unit that holds a plurality of pieces of buffer information, and a buffer control unit that stores data from input/output devices connected thereunder. When receiving data, buffer information is received from the buffer control section, the received data is stored in a data buffer area on the storage section specified by the buffer information, and an interrupt is requested from the processor section to notify the control program. In a data transfer system comprising a control unit, when receiving data from the input/output device, the transfer control unit stores the received data in one or more data buffer areas according to the length of the received data,
A received data transfer control method, characterized in that a chain of buffer information indicating the one or more data buffer areas is stored on the storage unit, and a storage position of the chain of buffer information is notified to the control program. 2. The reception data transfer control system according to claim 1, wherein the buffer information includes at least information indicating the start address of the corresponding data buffer area and the length of the data buffer area.