JP4428787B2 - Imaging apparatus, control method thereof, and storage medium - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging device such as a video camera, a scanner, or a digital camera using a color-compatible CCD or MOS image sensor, and more particularly to an access technology for a memory that stores image data.
[0002]
[Prior art]
When an image sensor such as a linear CCD having a color-corresponding multi-line configuration is used as an image pickup device in an image pickup device, the image sensor reads lines between colors of R, G, B (Red, Green, Blue) due to its structure. An offset occurs.
[0003]
In order to eliminate such a reading line offset, a buffer memory (offset memory) for offset cancellation is generally used. In the imaging device, an imaging element is used for image processing. For child Therefore, it is necessary to simultaneously input pixel data at the same position several lines before being read into the image processing unit. Further, since the pixel data read by the image sensor and digitally converted by the A / D conversion means is transmitted to the host computer in real time, the access to the offset memory is repeatedly performed while the writing and reading of the pixel data are mixed.
[0004]
Therefore, as the offset memory, an SRAM (Static Random Access Memory) or the like, which is conventionally characterized by random access and has a high access speed, is often used.
[0005]
[Problems to be solved by the invention]
By the way, in the imaging apparatus, as the resolution of the imaging device and the A / D converter increases, the amount of digital pixel data after A / D conversion of the input image increases.
[0006]
However, for example, when an SRAM or the like characterized by random access is used as an offset memory as in the prior art, each SRAM has a small capacity, so it is necessary to use a plurality of SRAMs, and the number of parts is increased. . Such an increase in the number of parts also leads to an increase in power consumption, which is very wasteful.
[0007]
In addition, when a large capacity memory such as DRAM (Dynamic Random Access Memory) is used as an offset memory, if the pixel data is read / written to / from the offset memory for each pixel (that is, for each data), the response speed of the DRAM is increased by random access. Because it was slow, it was not possible to read and write data efficiently. Conversely, in order to read and write data efficiently, a plurality of DRAMs are used for parallel processing. This also increases the number of parts and increases the power consumption, which is very wasteful.
[0008]
The present invention has been made under such a background, and an object thereof is to enable efficient access to temporary storage means.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention Imaging apparatus according to Is A color-capable imaging device having a multi-line configuration; Temporary storage means for temporarily storing pixel data output from the image sensor and subjected to A / D conversion; , A plurality of the pixel data are stored in the temporary storage unit. For each color of the multi-line configuration color Transfer control means for performing burst transfer collectively, and reading and writing the plurality of pixel data burst-transferred by the transfer control means And offset between pixel data of each color corresponding to the multiple lines And an access control means for controlling access to the temporary storage means.
[0010]
The present invention also provides: Multi-line color support A method for controlling an imaging apparatus having temporary storage means for temporarily storing pixel data output from an image sensor and subjected to A / D conversion, wherein a plurality of the pixel data are stored in the temporary storage means. For each color of the multi-line configuration color A transfer control process for performing burst transfer collectively, and a plurality of pixel data burst-transferred by the transfer control process are collectively read and written And offset between pixel data of each color corresponding to the multiple lines And an access control step for controlling access to the temporary storage means.
[0011]
The present invention also provides: Multi-line color support A storage medium for storing a program executed by an imaging apparatus having temporary storage means for temporarily storing pixel data output from an image sensor and subjected to A / D conversion. The pixel data of For each color of the multi-line configuration color A transfer control routine for collectively transferring bursts, and reading and writing a plurality of the pixel data burst-transferred by the transfer control routines And offset between pixel data of each color corresponding to the multiple lines And an access control routine for controlling access to the temporary storage means.
[0012]
In the present invention, the temporary storage means is constituted by an EDO DRAM (Extended Data Output DRAM) or an SDRAM (Synchronous DRAM).
[0013]
In the present invention, the image sensor is Consists of RGB 3-color CCD image sensor .
[0015]
In the present invention, the transfer control means is a FIFO type. Buffer memory Using Summarize by the color, Burst transfer control is performed.
[0016]
In the present invention, the transfer control means is a random access type. Buffer memory Using Summarize by the color, Burst transfer control is performed.
[0018]
In the present invention, the access control means Stage The two groups of the plurality of pixel data corresponding to the two preceding and following lines relating to the same color are continuously read out.
[0019]
In the present invention, the access control means Stage Access control for continuously reading two groups of the plurality of pixel data corresponding to two preceding and following lines relating to the same color, and access control for collectively writing the plurality of pixel data Are mixed.
[0022]
In the present invention, the access control means In steps A rearrangement method for rearranging the pixel data read out in batches by color according to the color arrangement order as input after A / D conversion. Step Have.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0026]
[First Embodiment]
FIG. 1 is a block diagram showing a schematic configuration of an imaging apparatus to which the first embodiment of the present invention is applied. In FIG. 1, 1 is an image sensor, 2 is an A / D converter, 3 is a pixel data write buffer memory (also referred to as WRITE CASH), 4 is a pixel data read buffer memory (also referred to as READ CASH), and 5 is An offset memory, 6 is an offset memory control unit, 7 is an external CPU, 8 is a switching unit between the external CPU 7 and a block inside the apparatus, 9 is an image processing unit, and 10 is another block of the imaging apparatus.
[0027]
Various operations described later in the present embodiment are controlled by the CPU 100 based on a program preset in the ROM 200, and at this time, the RAM 300 is used as a work area or the like.
[0028]
FIG. 2 is a block diagram showing the detailed configuration of the pixel data writing buffer memory 3 and the pixel data reading buffer memory 4. FIG. 3 is a timing chart showing the basic operation of the present embodiment. 4 and 5 are timing charts when only writing and reading are performed to the offset memory 5, respectively.
[0029]
As the image sensor 1, a color-corresponding 3-line CCD is used and scanned in a dot sequential manner. At this time, the pixel data input from the image sensor 1 via the A / D conversion unit 2 is pixel data of R, G, B colors such as R1, G1, B1, R2, G2, B2,. Are arranged in a cyclic manner. In addition, since the imaging device 1 is a linear type with a plurality of lines corresponding to color, for example, the pixel data R1, G1, and B1 are not color data of the same pixel but pixel data having an interline offset value.
[0030]
The pixel data writing buffer memory 3 and the pixel data reading buffer memory 4 are constituted by a FIFO (First In First Out) type memory that does not require management of access addresses, and the pixel data is R, G, B. It is composed of three surfaces (three memories) so that each color can be stored together, and pixel data of each color is sequentially input to the corresponding surface one color at a time. Further, each of the three R, G, and B memories has a memory capacity capable of storing pixel data for 16 pixels.
[0031]
In other words, the number of data words in the three memory planes for R, G, and B is 16, respectively, and is divided into two blocks to form a two-block configuration, with one block for writing and the other block for Used exclusively for reading from memory. Then, R, G, and B pixel data are burst transferred to the offset memory 5 in units of 8 pixels.
[0032]
In other words, the pixel data transferred via the A / D converter 2 is selected and stored in the first block in the initial state in the first block of each color memory. When pixel data for eight pixels of each color is accumulated in the first block, the second block is selected, and the transferred pixel data is sequentially input and held in the second block. When pixel data for eight pixels of each color is accumulated in the second block, the first block is selected, and the transferred pixel data is sequentially input and held in the first block.
[0033]
Thereafter, this operation is repeated. Therefore, the pixel data is written into the pixel data writing buffer memory 3 for each color of R, G, and B in the form of the first block → second block → first block → second block... Two blocks are used alternately in units. At this time, since the pixel data is input from the A / D converter 2 in the order of R1, G1, B1, R2, G2, B2,..., The first block of R to collect 8 pixels of each color. R1 → G first block G1 → B first block B1 → R first block R2 → G first block G2 → B first block B2,..., R first block From R8 → G to the first block G8 → B to the first block B8,..., R to the second block R9 → G to the second block G9 → B to the second block B9,... It is distributed to the corresponding color memory block.
[0034]
On the other hand, the reading of the pixel data from the pixel data writing buffer memory 3 is performed using a block exclusively from the above writing.
[0035]
That is, when reading out pixel data from the pixel data writing buffer memory 3, in the initial state, the second block of the memory of each color is selected, and continuous pixel data of 8 pixels of each color of this second block is batched. The data is read in the order of R → G → B. When the pixel data for 8 pixels of each color of the second block is read out, the first block is selected, and the continuous pixel data of 8 pixels of each color in the first block are collectively R → G → B. Are read in this order.
[0036]
Thereafter, this operation is repeated. Accordingly, the pixel data output from the pixel data writing buffer memory 3 is written in the order of the second block → the first block → the second block → the first block, for each of R, G, and B colors. The block is exclusively used by alternately using two blocks. At this time, the pixel data is input from the A / D conversion unit 2 in the order of R1, G1, B1, R2, G2, B2,... 8 pixels in order from the top of the block → 8 pixels in order from the top of the two blocks of G → 8 pixels in order from the top of the second block of B → 8 pixels in order from the top of the first block of R, etc. In order. That is, R1, R2,..., R8, G1, G2,..., G8, B1, B2, ..., B8, R9, R10,. Output.
[0037]
The access control as described above for the pixel data writing buffer memory 3 is performed under the control of three write access control units 3a corresponding to the R, G, and B colors.
[0038]
As described above, the pixel data collected and output by 8 pixels from the pixel data writing buffer memory 3 is output to the offset memory 5 via the switching unit 8 under the control of the offset memory control unit 6. Burst transfer.
[0039]
In the present embodiment, an EDO DRAM having a faster access response speed in sequential access than in random access is used as the offset memory 5, and the offset memory control unit 6 performs pixel processing in the EDO mode with respect to the offset memory 5. Perform data access. In addition, an image processing unit 9 is arranged after the offset memory 5, and the image processing unit 9 performs image processing using the same line data and the previous line data of each color. The continuous writing of a plurality of pixel data for each of the 8 pixels and the continuous reading of the pixel data of the same color and the previous line for each of the 8 pixels are performed in a mixed manner.
[0040]
FIG. 3 is a timing chart showing the basic operation in the first embodiment.
[0041]
In FIG. 3, CLK is a clock signal for controlling the operation of the imaging apparatus, DATAIN is pixel data input from the A / D conversion unit 2, and WR CASH WE is writing to the pixel data writing buffer memory 3. An enable signal WR CASH OE indicates an output enable signal from the pixel data writing buffer memory 3.
[0042]
WR CASH DATA OUT is pixel data output from the pixel data writing buffer memory 3, RAM RAS is a signal of the RAS terminal for row access of the offset memory 5, and RAM CAS is column access of the offset memory 5. The CAS terminal signal RAM WE indicates a write enable signal for the offset memory 5, RAM OE indicates an output enable signal from the offset memory 5, and RAM DATA indicates access data for the offset memory 5.
[0043]
RD CASH DATA IN is pixel data output to the pixel data reading buffer memory 4, RD CASH WE is a write enable signal for the pixel data reading buffer memory 4, and RD CASH OE is pixel data reading. An output enable signal from the buffer memory 4 is shown. DATA OUT indicates output data from the pixel data reading buffer memory 4. All signals other than the above data are negative logic.
[0044]
As shown in the RAM DATA of FIG. 3, after the pixel data of R11 to R18 are written in the offset memory 5, two R01 to R08 and R11 to R18 of the R color before and after the R color are written from the offset memory 5. The pixel data of the line is continuously read out in units of 8 pixels. Further, although not shown in FIG. 3, when G11 to G18 are written next to the continuous reading of R01 to R08 and R11 to R18 and the subsequent continuous reading is performed, R01 to R08 are set to eliminate the offset. Similarly, pixel data of two lines of G color corresponding to each pixel of R11 to R18 are continuously read out in units of 8 pixels.
[0045]
In this way, the pixel data of the same line and the previous line for each color for 8 pixels read from the offset memory 5 under the control of the offset memory control unit 6 are input to the image processing unit 9. The image processing unit 9 performs image processing such as interpolation by taking an average value of pixel data for two lines, and outputs the data to the pixel data reading buffer memory 4 as data for one line (RD in FIG. 3). (See RSH01 to R'08 of CASH DATA IN).
[0046]
As the pixel data input to the pixel data reading buffer memory 4, the first block of the R, G, B color memory is selected in the initial state. That is, the continuous pixel data of 8 pixels for each color transferred from the offset memory 5 via the offset memory control unit 6 and the image processing unit 9 is first input and held in the first block. When continuous pixel data of 8 pixels for each color is input to the first block, the second block is selected, and continuous pixel data of 8 pixels for each color is input to the second block and held. Furthermore, when continuous pixel data for the next eight colors is transferred, the first block is selected.
[0047]
Thereafter, this operation is repeated. Accordingly, the pixel data transferred from the image processing unit 9 is, for each color, 8 pixels in order from the top of the first block → 8 pixels in order from the top of the second block → 8 pixels in order from the top of the first block. In order and R → G → B (R′1, R′2,..., R′8, G′1, G′2,..., G′8, B′1, B′2,. B′8, R′9, R′10,..., R′16, ...) are held in the pixel data reading buffer memory 4.
[0048]
The pixel data output from the pixel data reading buffer memory 4 to the other block 10 is performed exclusively from the above state. In other words, in the initial state, the pixel data output to the other block 10 is performed by selecting the second block of the memory of each color and outputting the pixel data of each color from the second block. When pixel data for 8 pixels of each color in the second block is output, the first block is selected, and pixel data for the next 8 pixels of each color is output from the 1st block, and the pixel data for 8 pixels of each color. Is output, the second block is selected.
[0049]
Thereafter, this operation is repeated. However, the order output from the pixel data reading buffer memory 4 is the order read from the offset memory 5 and supplied via the memory control unit 6 and the image processing unit 9, that is, the pixel data of the same color is 8 It is not the order in which the pixels are continuous, but in the order (R′1, G′1, B′1, R′2, G′2, B′2) input via the A / D converter 2. Output.
[0050]
That is, the head of the second block of R → the head of the second block of G → the head of the second block of B → the second of the second block of R → the second to the second block of G → the second block of B 8th of the second block of R, 8th of the second block of G, 8th of the second block of B,..., The beginning of the first block of R → the beginning of the first block of G → Read access is performed in the order of the top of the first block of B,... And output in the order of R′1, G′1, B′1, R′2, G′2, B′2. The
[0051]
Note that the access control as described above for the pixel data reading buffer memory 4 is performed under the control of the three read access control units 4a corresponding to the R, G, and B colors.
[0052]
In this way, the pixel data in the pixel data reading buffer memory 4 is output to the other blocks 10 without breaking the order of the pixel data input from the image sensor 1 via the A / D converter 2. To do.
[0053]
In addition, since the image processing unit 9 is arranged in the preceding stage of the pixel data reading buffer memory 4, the pixel data reading buffer memory 4 is 16 times as many as eight pixels, like the pixel data writing buffer memory 3. This can be realized with a FIFO memory for pixels (2-block configuration).
[0054]
In addition, as described above, only writing or reading is performed on the offset memory 5 by changing the operation of the memory control unit 6 without performing both writing and reading on the offset memory 5 in a mixed manner. It is also possible to do this.
[0055]
When the mode for performing only writing to the offset memory 5 is set, pixel data input from the image sensor 1 via the A / D conversion unit 2 can be stored by the capacity of the offset memory 5. By reading out the pixel data from the external CPU 7 through the switching unit 8, the pixel data can be handled by the external CPU 7. Further, when the mode in which only reading from the offset memory 5 is performed, when there is no pixel data input from the image sensor 1 via the A / D converter 2, the pixel data remaining in the offset memory 5 is efficiently stored. It can be output to another block 10.
[0056]
4 and 5 show timing charts when only writing and reading are performed, respectively.
[0057]
As described above, in the first embodiment, the offset memory 5 is a high-speed, large-capacity memory such as an EDO DRAM that has a faster access response speed in sequential access such as burst transfer than in random access for each data. In the EDO (fast page) mode, high-speed access is made in units of continuous 8-pixel pixel data.
[0058]
In addition, in the offset memory 5, as preparation for high-speed access in units of pixel data of 8 consecutive pixels, the FIFO memory pixel data writing buffer memory 3 is used to perform A / D conversion from the image sensor 1. Pixel data that is cyclically input in the order of R, G, and B via the unit 2 is collected into a plurality of pixel data that is continuous for 8 pixels of each color, and is output to the offset memory 5.
[0059]
Further, the data is read from the offset memory 5 at a high speed with continuous data for 8 pixels of each color, and the read data is input from the image sensor 1 through the A / D converter 2 using the FIFO-type pixel data reading buffer memory 4. The pixel data is rearranged in the order as it is, and output to another block 10.
[0060]
With such a configuration, it is possible to access the offset memory at high speed without connecting DRAMs as the offset memory in parallel as in the prior art, and to avoid an increase in power consumption. Therefore, it is not necessary to reduce the operation speed of the image sensor 1 and the A / D converter 2, and the image data can be processed efficiently.
[0061]
Furthermore, since a FIFO memory that does not require address management is used as a memory that temporarily stores input data from the A / D converter 12, access control to the temporary memory is simplified.
[0062]
[Second Embodiment]
FIG. 6 is a block diagram showing a schematic configuration of an imaging apparatus to which the second embodiment of the present invention is applied. In FIG. 6, 11 is an image sensor, 12 is an A / D converter, 13 is a pixel data write buffer memory (also referred to as WRITE CASH), 14 is a pixel data read buffer memory (also referred to as READ CASH), and 15 is Offset memory, 16 is an offset memory control unit, 17 is an external CPU, 18 is a switching unit between the external CPU 17 and a block inside the apparatus, 20 is another block of the imaging device, 21 is a write side address control unit, and 22 is a read This is a side address control unit.
[0063]
Various operations described later in the present embodiment are controlled by the CPU 400 based on a program preset in the ROM 500. At this time, the RAM 600 is used as a work area or the like.
[0064]
FIG. 7 is a block diagram showing detailed configurations of the pixel data writing buffer memory 13 and the pixel data reading buffer memory 14. FIG. 8 is a timing chart showing the operation of this embodiment.
[0065]
As the image pickup device 11, a color-corresponding three-line CCD is used, and scanning is performed in a dot sequential manner. At this time, pixel data input from the image sensor 11 via the A / D converter 12 is pixel data of each color of R, G, and B, such as R1, G1, B1, R2, G2, B2,. Are arranged in a cyclic manner. Further, since the image pickup device 11 is a linear type having a plurality of color-corresponding line configurations, for example, the pixel data R1, G1, and B1 are not the color data of the same pixel but pixel data having an interline offset value.
[0066]
The pixel data writing buffer memory 13 and the pixel data reading buffer memory 14 are configured by a RAM (Random Access Memory) that requires management of access addresses. The number of data words in the RAM is equal to or more than a plurality of pixels designated to collectively transfer and access a plurality of pixel data of each color. The designated number of pixels is “4” in the present embodiment.
[0067]
The writing side address control unit 21 performs access control to the pixel data writing buffer memory 13. At this time, the write side address control unit 21 exclusively controls the write / read address so that the write address for the pixel data write buffer memory 13 and the read address do not overlap.
[0068]
Further, the write side address control unit 21 performs A / D in a state where pixel data of each color of R, G, B is cyclically arranged as in R1, G1, B1, R2, G2, B2,. As shown in FIG. 7, the pixel data input from the conversion unit 12 is a group of pixel data of the same color for a specified number of pixels, and the arrangement order of the group is R → G → B. Thus, the write address is controlled so as to be held in the pixel data write buffer memory 13. Further, the read address is controlled so that the pixel data held in the pixel data writing buffer memory 13 is output in a form in which a specified number of pixels are collected in the order of R → G → B. That is, R, G, and B pixel data are burst transferred to the offset memory 15 in units of four pixels.
[0069]
In this way, the pixel data collected and output for each of the four pixels from the pixel data writing buffer memory 13 is burst to the offset memory 15 via the switching unit 18 under the control of the offset memory control unit 16. Transferred.
[0070]
In the present embodiment, an EDO DRAM having a faster access response speed during sequential access than during random access is used as the offset memory 15, and the offset memory control unit 16 uses pixel data for the offset memory 15 in EDO mode. Access. In addition, in order to perform image processing using the same line data of each color and the data of the previous line by the other block 20 or the like, a plurality of pixel data of a specified plurality of pixels (for four pixels) is provided to the offset memory 15 And continuous reading of a plurality of pixel data for each specified number of pixels (for four pixels) are performed in a mixed manner.
[0071]
FIG. 8 is a timing chart showing the operation in the second embodiment.
[0072]
In FIG. 8, CLK is a clock signal for controlling the operation of the imaging apparatus, DATAIN is pixel data input from the A / D converter 12, and WR CASH WA is writing to the pixel data writing buffer memory 13. An address WR CASH OA indicates an output address from the pixel data writing buffer memory 13.
[0073]
WR CASH DATA OUT is pixel data output from the pixel data writing buffer memory 13, RAM RAS is a signal of the RAS terminal for row access of the offset memory 15, and RAM CAS is column access of the offset memory 15. The CAS terminal signal RAM WE indicates a write enable signal for the offset memory 15, RAM OE indicates an output enable signal from the offset memory 15, and RAM DATA indicates access data for the offset memory 15.
[0074]
Further, RD CASH DATA IN is pixel data output to the pixel data reading buffer memory 14, RD CASH WA is a writing address to the pixel data reading buffer memory 14, and RD CASH OA is pixel data reading. An output address from the buffer memory 14 is shown. DATA OUT indicates output data from the pixel data reading buffer memory 14. All signals other than the above data are negative logic.
[0075]
As shown in the RAM DATA of FIG. 8, after the pixel data of R11 to R14 are written to the offset memory 15, two R01 to R04 and R11 to R14 of the R color before and after the R color are written from the offset memory 15. The pixel data of the line is continuously read out in units of 4 pixels. Although not shown in FIG. 8, G11 to G14 are written after the continuous reading of R01 to R04 and R11 to R14. Similarly, pixel data of two lines of G color corresponding to each pixel of R11 to R14 are continuously read out in units of four pixels.
[0076]
In this manner, the pixel data of the same color and the previous line for each of the four pixels read from the offset memory 15 under the control of the offset memory control unit 16 are output to the pixel data reading buffer memory 14 (FIG. 8). RD CASH DATA IN R'01 to R'04).
[0077]
Access control to the pixel data reading buffer memory 14 is performed by the reading-side address control unit 22. At this time, the read side address control unit 22 exclusively controls the write / read address so that the write address for the pixel data read buffer memory 14 and the read address do not overlap.
[0078]
Further, as shown in FIG. 7, the read-side address control unit 22 controls the write address so that pixel data of the same color is collected in a specified number of pixels and held in the pixel data read buffer memory 14. To do. However, the order output from the pixel data reading buffer memory 4 is the order read from the offset memory 15 and supplied via the offset memory control unit 16, that is, the pixel data of the same color is continuous for four pixels. Output in the order (R′1, G′1, B′1, R′2, G′2, B′2) input via the A / D conversion unit 2 instead of Control the read address.
[0079]
In this manner, the pixel data in the pixel data reading buffer memory 14 is output to the other block 20 without changing the order of the pixel data input from the image sensor 11 via the A / D converter 12. To do.
[0080]
With this configuration, as in the first embodiment, the offset memory can be accessed at high speed without connecting the DRAM as the offset memory in parallel as in the prior art, and the power consumption is increased. Can also be avoided. Therefore, it is not necessary to reduce the operation speed of the image sensor 11 and the A / D converter 12, and it is possible to efficiently process image data.
[0081]
Further, since the RAM is used as the memory for temporarily storing the input data from the A / D converter 12, the number of pixel data to be burst transferred to the offset memory 16 can be easily changed. .
[0082]
The present invention is not limited to the above-described embodiment. For example, an SDRAM (Synchronous DRAM) can be used as an offset memory instead of an EDO DRAM. Also in the second embodiment, a mode in which only writing or reading is performed with respect to the offset memory 15 may be provided as in the first embodiment.
[0083]
【The invention's effect】
As described above, according to the present invention, it is possible to access pixel data at a high speed to one temporary storage unit without connecting a plurality of temporary storage units in parallel. Therefore, it is possible to efficiently access the temporary storage means without reducing the operation speed of the image sensor and the A / D conversion unit, and it is also possible to avoid an increase in power consumption.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of an imaging apparatus to which a first embodiment of the present invention is applied.
FIG. 2 is a diagram showing a detailed configuration of a pixel data writing buffer memory according to the first embodiment of the present invention.
FIG. 3 is a time chart showing a basic operation in the first embodiment of the present invention.
FIG. 4 is a time chart showing an operation when only writing to the offset memory is performed in the first embodiment of the present invention;
FIG. 5 is a time chart showing an operation when only reading is performed with respect to the offset memory in the first embodiment of the present invention;
FIG. 6 is a block diagram showing a schematic configuration of an imaging apparatus to which a second embodiment of the present invention is applied.
FIG. 7 is a diagram showing a detailed configuration of a pixel data writing buffer memory according to a second embodiment of the present invention.
FIG. 8 is a time chart showing the basic operation in the second embodiment of the present invention.
[Explanation of symbols]
1, 11 ... Image sensor
2,12 ... A / D converter
3, 13 ... Buffer memory for writing pixel data
3a: Write side access control unit
4, 14... Are pixel data reading buffer memories.
4a: Read side access control unit
5, 15 ... Offset memory
6, 16 ... Offset memory control unit
21: Write side address control unit
22... Read side address control unit
100, 400 ... CPU
200,500 ... ROM
300,600 ... RAM

Claims (10)

A multi-line color image sensor;
A temporary storage means for temporarily storing the pixel data A / D-converted output from the imaging element,
A transfer control unit that burst-transfers the plurality of pixel data to the temporary storage unit in a collective manner according to colors of the plurality of lines ; and
Access control means for collectively reading and reading the plurality of pixel data burst-transferred by the transfer control means and performing access control to the temporary storage means so as to eliminate the offset between the pixel data of each color corresponding to the plurality of lines When,
An imaging apparatus comprising:   2. The imaging apparatus according to claim 1, wherein the temporary storage unit is configured by an EDO DRAM (Extended Data Output DRAM) or an SDRAM (Synchronous DRAM). The image pickup apparatus according to claim 1, wherein the image pickup device is an RGB three-color three-line CCD image pickup device. The image pickup apparatus according to claim 1 , wherein the transfer control unit performs burst transfer control for each color using a FIFO buffer memory . The imaging apparatus according to claim 1 , wherein the transfer control unit performs burst transfer control for each color using a random access buffer memory . The imaging apparatus according to claim 1 , wherein the access control unit continuously reads two groups of the plurality of pieces of pixel data corresponding to two preceding and following lines related to the same color. The access control means writes access control for continuously reading two groups of the plurality of pixel data corresponding to two lines preceding and following the same color, and collectively writing the plurality of pixel data. The image pickup apparatus according to claim 6 , wherein the access control is performed in a mixed manner. Re-arrangement means for re-arranging pixel data collectively read by the access control means for each color according to the color arrangement order as input after A / D conversion; The imaging device according to claim 1 . A method for controlling an imaging apparatus having temporary storage means for temporarily storing pixel data output from a color-capable color- capturing image sensor having a plurality of lines and subjected to A / D conversion,
A transfer control step of burst-transferring the plurality of pieces of pixel data to the temporary storage unit for each color of the plurality of line configurations ;
An access control step for performing access control on the temporary storage unit so as to collectively read / write the plurality of pixel data burst-transferred by the transfer control step and eliminate an offset between pixel data of each color corresponding to the plurality of lines When,
An image pickup apparatus control method comprising: A storage medium for storing a program executed by an imaging apparatus having temporary storage means for temporarily storing pixel data output from a color-compatible imaging device having a multi-line configuration and subjected to A / D conversion.
A transfer control routine for burst-transferring a plurality of the pixel data to the temporary storage unit for each color of the plurality of line configurations ;
An access control routine that collectively reads / writes the plurality of pixel data burst-transferred by the transfer control routine and performs access control to the temporary storage means so as to eliminate the offset between the pixel data of each color corresponding to the plurality of lines When,
A storage medium comprising:

Images