JPH02108169A - Frame memory device - Google Patents

Abstract

PURPOSE:To generate different offsets when image data are inputted and outputted and to easily move an image by setting the optional offsets for addresses generated by a main scanning address generating means and a subscanning address generating means. CONSTITUTION:Addresses on frame memory means 800 and a 900 which are accessed are generated by the main scanning address generating means and subscanning address generating means. Those addresses are updated in order according to the scanning of a device which attains access by using the values of a main scanning offset value holding means and a subscanning offset value holding means as initial values. Therefore, the actual access address of the memory is varied in a main scanning direction and a subscanning direction according to the offset values. Consequently, the offset values are updated after the input image data are written in the frame memory means 800 and 900 to read the input image data out of the frame memory means and record the image, and consequently the addresses of the writing to the memory and the reading from the memory are slightly different from each other, so the image moves instantaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame memory device used to store information such as one image, and particularly to movement of an image to be processed.

[Prior Art] For example, when attempting to perform various editing processes on an image read by an image scanner before printing, the information is input sequentially as time-series information, so all of the information must be The information is temporarily stored in memory, and then the memory in which the information is stored is accessed to perform editing processing. This type of memory is called frame memory.
Usually requires a very large storage capacity 6 For example,
When reading a Δ3 size image at a resolution of 16 pixels/mm, approximately 4 Mbytes are required even for a single color with two gradations, and a color image requires at least 12 Mbytes.

[Problems to be Solved by the Invention] For example, when an image input from an image scanner is to be recorded by a printer, it is often desired to move the position of the image to be recorded in the vertical or horizontal direction. In an image processing device equipped with a frame memory, after storing image data on the memory, the CPU is used to access the memory and transfer (move) all the data to a different address than before. By repeating this, you can move the image on the memory and change the position of the recorded image. This type of operation is a relatively simple process, but since it needs to be performed on all data, the amount of processing is enormous and it takes a long time to execute. Additionally, if the size of the image to be processed is as large as the capacity of the frame memory, it is necessary to temporarily save part of the image data so that it is not destroyed by moving the data. Additional memory is required.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a frame memory device that can perform image movement processing in a short time, and also to eliminate the need for a special memory for saving data.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides frame memory means including a main scanning address bus and a sub-scanning address bus for specifying the address of the memory to be accessed; main scanning offset value holding means = Sub-scanning offset value holding means; After loading the value held by the main-scanning offset value holding means as an initial value, it counts the pixel synchronization signals output from the device that accesses the memory, and stores the counted value as described above. The signal is applied to the main scanning address bus of the frame memory means. Main scanning address generation means; after loading the value held by the sub-scanning offset value holding means as an initial value, it counts line synchronization signals output from a device that accesses the memory, and stores the counted value in the frame memory. to the sub-scanning address bus of the means. A sub-scanning address generating means; and an offset value updating means for updating the values held by the main-scanning offset value holding means and the sub-scanning offset value holding means are provided.

[Function] According to the present invention, the address on the frame 11 memory means to be accessed is generated by the main scanning address generating means and the sub-scanning address generating means.

In addition, these addresses are updated sequentially as the accessing device scans, with the values of the main scanning offset value holding means and the sub-scanning offset value holding means as initial values, so that the memory is actually accessed. The address to be scanned changes in the main scanning direction and the sub-scanning direction according to the offset value. Therefore, after writing the input image data to the frame memory means, if the offset value is updated and the image data is read from the frame memory means and recorded, the address when writing to the memory and the address when reading from the memory Since the addresses are shifted from each other, the image is moved accordingly. According to this, since the movement of the image only involves updating the offset value in ja, this process is instantaneously executed. No special memory for saving is required.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

[Embodiment] FIG. 1 shows the configuration of one type of image processing system that implements the present invention.

Referring to FIG. 1, the system includes an image scanner 104. Page printer 105. A printer controller 100 and a general-purpose computer 110 are provided. The image scanner 104 main-scans and sub-scans a document image positioned on its reading surface, and converts one image information into R.
(Red).

Each of G (green) and B (blue) is sequentially output as independent 8-bit time-series gradation information.

In this example, a laser printer is used as the page printer 105. Image scanner 104, printer controller 100, and page printer 105 are commonly connected to bus 101 of general-purpose computer 110.

General-purpose computer 110 is a commercially available computer and includes a central processing unit (CPU) 102. Storage device 103. It is equipped with a keyboard 111 and a CRT 112. The central processing unit 102 has a general-purpose bus 101, which connects an image scanner 104 and a printer controller 100.
and a page printer 105.

The printer controller 100 includes a task processor 10
8. Skyana Interface 120. It includes a frame memory 1062, an image processing section 107, and a printer interface 121. The raster processor 108 is a device that performs data format conversion, and in this embodiment, the raster processor 108 is a device that converts data format.
vector format data handled by esign) systems, etc., and DTP (Desk Top Publishing)
g) PDL (Page Desc) handled by the system
It has a function of converting data in the RIPT Language format into rask, ie, bitmap format image data at high speed. In this example, a vector format or PDL file created by general-purpose computer 110 is used.
A raster processor 108 is used to convert various types of image information into raster.

Either the image data output from the image scanner 104 or the image data output from the raster processor 108 is input to the frame memory 106 via the scanner interface 120.

Roughly speaking, the frame memory 106 has a function of storing image data input from an interface 120 according to a control signal applied from the interface 120, and a function of storing image data input directly from the general-purpose computer 110 via the general-purpose bus 101. It has a viewing function and a function of outputting image data stored in its memory in synchronization with a control signal applied from the image processing unit 107.

The image processing unit 107 performs input γ correction on the image data input from the frame memory 106.

Various conventionally known processes such as color correction, scaling (enlargement/reduction), filter processing, and so on are performed.

Furthermore, in order to accommodate various image formats, parameters for various processes can be set by the general-purpose computer 110 via the general-purpose bus 101.

The system shown in FIG. 1 has four operating modes that can be broadly classified. That is, in the first operation mode, the flow of image data is 104-120-106-10.
7-121-105.

An image read by an image scanner 104 is recorded by a page printer 105. In other words, the system 11 operates as a copying machine. General purpose computer 110 in this case
The processing contents of the CPU are shown in FIG. 2a, so please refer to it.

In the second mode of operation, the image data flow is 10
3-102-101-108-120-106-107
-121-105. In other words, general-purpose computer 1
The contents of the image information file in vector format or PDL format stored in advance in the storage device 103 of 10 are
It is recorded by the page printer 105. In this case, the data is converted from vector format or PDL format to raster format by raster processor 108 and then sent to page printer 105 . The details of the processing of the general-purpose computer 110 in this case are shown in FIG. 2b, so please refer to it.6 In the third operation mode, the flow of image data is
03-102-101-1.06-107-121-1
It becomes 05. This mode is used when image data previously created in bitmap format exists on the general-purpose computer 110 and the image is to be recorded by the printer 105. The details of the processing performed by the general-purpose computer 110 in this case are shown in FIG. 2c.

In the fourth mode of operation, the image data flow is 1
04-120-106-101-102-103. That is, in this case, image information read by the image scanner 104 can be stored in the storage device 103 on the general-purpose computer 110. The contents of the processing of the general-purpose computer 110 in this case are shown in FIG. 2d, so refer to ν).

As described above, in the system 11 shown in FIG. 1, this single system converts images in various formats into image information in formats required by various types of page printers, and outputs the image information. It is extremely versatile and can be used for a variety of purposes.

Next, the frame memory 106 shown in FIG. 1 will be specifically explained. The configuration of this frame memory.

It is shown in Figure 3.

Referring to FIG. 3, this device includes a first interface 201. which is connected to a general-purpose bus 101 of a general-purpose computer. A second interface 202 connected to a page printer. and a third interface 203 connected to the image scanner side, and are connected to various external devices via these interfaces.

That is, the general-purpose computer 110 can access the frame memory via the general-purpose bus 101 and the interface 201, and image data input from the image scanner 104 is input to the frame memory via the interface 203, and is sent from the frame memory to the page printer. Direct data output occurs via interface 202.

The signals applied to each interface will be explained in detail. Note that an overlined symbol in one drawing means that the signal is active when the signal is at a low level, but the overline is omitted from the description in the specification.

The number 0 applied to the signals m22o, 221 and 222 is
These are synchronization signals output from the page printer, and are as follows.

FGATE...Frame synchronization signal indicating the effective image period of sub-scanning LGATE...Line synchronization signal IPCLK indicating the effective image period of main scanning...Clock pulse signal lines 233, 234 output for each pixel , 235 and 236 are Q signals output from the scanner interface 120, and are as follows.

Address...Image write address information book consisting of n+m bits: Included bank...Image write bank specification information consisting of N bits WE...Image write strobe TOGGLIE...Toggle access (two memory The main body of the frame memory includes a mode determining section 300, a bank selecting section 400, and a bank selecting section 400. Address control section 500゜Data control section 600
．． RAM control section 700 and two bank memory sections 800
,900 are provided.

The configuration of the mode determining section 300 is shown in FIG. 4a.

Referring to FIG. 4a, this circuit includes two registers 301 connected to an internal data bus 210 (101).
, 302 and a logic circuit 303 for determining the mode. This circuit generates each mode signal according to the logic shown in Table 1 below according to the combination of states of various input signals, and outputs them to signal lines 304 to 308.

Table 1 In other words, the mode determining unit 300 identifies five modes (BUS mode, I(RD mode, HWR mode, MAC mode, and TOGGLE mode)) according to a signal applied from the outside, and indicates the mode. A signal is output.The operation of each mode is as follows.

BUS: A general-purpose computer accesses the frame memory via the general-purpose bus 101.

HRD: Reads data in the frame memory serially at high speed in synchronization with an external control signal.

) IWR... Image data is written randomly into the frame memory at high speed in synchronization with an external control signal.

MAC: Rewrites the entire contents of the frame memory to pre-specified values at high speed. The end of the operation is determined by the address control unit 5.
It is identified by the signal line 519 connected to 00.

TO[ll, GLIE... Performs serial toggle access to two bank memories 800 and 900 in the frame memory.

In this example, each of the bank memories (800, 900) has 6 or n+m
It includes three plane memories each having a storage capacity of bits and assigned to R2O and B respectively, and the three plane memories are connected in common to an n+m bit address bus, that is, in parallel.

Referring to FIG. 5b, if a different address area is allocated to each of the R, G, and B memory planes, the address space required to access them will increase according to the number of memory planes. are assigned to the same address in parallel, the address space becomes the same as the address space of one memory plane, regardless of the number of memory planes. In other words, when configured as shown in FIG. 5a, the number of address bus bits required for memory access is reduced.

Also in this example, the bank memories are connected in parallel to the general-purpose bus 101, as shown in FIG. 5c, and each bank memory is arranged in the same address space when viewed from the general-purpose bus 101. Of course, the selection of accessing a single bank memory selectively, rather than accessing a plurality of bank memories simultaneously, is controlled by the bank selector 400 shown in FIG.

A specific configuration of the bank selection section 400 is shown in FIG. 4b.

Referring to Figure 4b, this circuit includes latches 403.
Logic circuit 411. Data selector 409.410. Digital comparator 405, 406° bank specification switch 401
, 402 and gates 417, 418.

The bank designation switches 401 and 402 each consist of a mechanical switch that outputs an N-bit numerical value. In addition,
These switches may be constructed of, for example, non-volatile memory in which data can be rewritten by a general-purpose computer.

Each input terminal of the data selectors 409 and 410 has
Three sets of different N-bit bank selection information are applied, and one of them is selectively output by a data selector. The bank selection information output from the data selector 409 and the N-bit value output from the bank designation switch 401 are compared by the comparator 405, and if they match, a bank selection signal BSI is output. Similarly, the bank selection information output from the data selector 410 and the N-bit value output from the bank designation switch 402 are compared by the comparator 406, and if they match,
Bank selection signal BS2 is output.

One bank memory 80 is selected by bank selection signal BSI.
0 is selected, and the other bank memory 900 is selected by bank selection signal BS2.

Therefore, for example, if the bank designation switches 401 and 402 are set to 0 and 1, respectively, the signal lines 413,
When the bank selection information appearing at 414 is 0 and 1, bank memories 800 and 900 are accessible, respectively.

In this embodiment, one circuit board constituting the frame 11 memory is provided with two bank memories, so if, for example, four circuit boards are prepared, eight sets of bank memories can be provided. In other words, for each bank designation switch, for example 0. ■.

2.3. ．． By setting the values 4, 5.6, and 7, the bank memory corresponding to each bank designation switch is assigned to different banks 0, 1, 2, 3, 4°5.6, and 7, respectively.

A detailed explanation will be given later, but when reading and writing image information continuously, the address bus value is cleared to 0 every time the address bus value overflows, and the bank selection information is cleared accordingly. Incremented. That is, as the scanning position progresses, access is sequentially executed starting from the bank memory with the smallest bank value.

Therefore, for example, if eight bank memories are prepared in which address spaces of m bits I- in the main scanning direction and n bits in the sub-scanning direction are allocated as two-dimensional arrays, the bank values of the eight bank memories are allocated. 0, 1, 2, 3 respectively
, 4, 5, 6, and 7, the two-dimensional memory arrangement of the entire frame memory is as shown in FIG. 7b.

Therefore, when using this frame memory, continuous numerical values are normally assigned to the bank designation switches in order from 0. Thereby, a plurality of bank memories can be used as one continuous frame memory.

Furthermore, if the setting of the bank designation switch is changed between when writing image data and when writing successive image data, it becomes possible to edit one image in bank area units. For example, the 0th. 1st. Second
．． Third. 4th. Fifth. Set the bank values (bank designation switch values) of the sixth and seventh bank memories to 0, 1, respectively.
2, 3, 4 degrees 5.6 and 7 degrees, write the original image as shown in FIG. Second. Third. 4th. Fifth. Set the bank values of the sixth and seventh bank memories to 0.1, 2, and 0.1, respectively.
5, 6, 7. If the data in the frame memory is read out sequentially after updating to 2 and 3, the read image will be in a different order than the original, that is, the image will be moved, as shown in Figure 6b. Be what you are. Similarly, after writing an image with the same bank value as the former, 0. 1st. Second. Third. 4th゜5th. Bank values of the sixth and seventh bank memories.

If you read the image data after changing the values to 0, 1, 2, 8, 9, 5.6, and 7, the memory for bank values 8 and 9 will not be accessed, so the read image will be , is partially masked as shown in FIG. 6C. Also, after writing the same image with the same bank value as the former, switch the bank value to select only the third bank memory, write another image, return the bank value to the original, and read the image. , the read image is a partial composite of the first written image and the later written image. by this.

You can combine images.

In other words, according to this embodiment, editing processing such as moving, masking, and compositing images can be performed with the size of the bank area m of the frame 11 memory.

This process only requires switching the bank value.

Can be processed in a short time.

When a general-purpose computer accesses the frame memory from general-purpose bus 101, the access is performed after selecting the bank to be written by writing N-bit bank selection information to latch 403. When multiple boards are connected to the general-purpose bus, the same value is written to the latch 403 of each board at the same time.

The logic circuit 28411 identifies the current operating mode by referring to the mode signal, and selects the data selector 4 according to the result.
09. ．． The bank selection information selected by 410 is switched.

That is, in the BUS mode, HRD mode, HWR mode, and TOGGLH mode, the signal line 40
4, 235, 234 and 234 information is selected and cursed to signal lines 413 and 414.

Furthermore, since the mode signal MACM is applied to the input terminals of gates 417 and 418, in the MAC mode,
Regardless of the outputs of comparators 405 and 406, signal BSI
, BS2 becomes active and all bank memories can be accessed simultaneously.

In addition, in this embodiment, since the signal line through which bank selection information is passed is N bits, 2<N> bank memories can be connected to 1
Can be connected in parallel to two general-purpose buses. In other words,
The total memory capacity is 2 to the power of (N + n + m) ×
Frame memory up to 3 bytes can be constructed.

When 2 to the power of (N+n+m) x 3 bytes of memory is placed in a continuous address space, 1Usually, N + n
+ m + 2 bit address lines are required.

However, in this embodiment, each of the N banks is connected in parallel to the same address space, as shown in FIG. Therefore, the number of signal line bits required for the address bus to access this frame memory only needs to be n+m. In other words, N
The number of address bus bits required to access the frame memory is less than usual by +2 bits. As a result, even if a large-capacity frame memory is required, image processing can be controlled by a computer using a general-purpose bus with a small number of bits.

The specific configuration of the address control unit 500 in FIG.
As shown in the figure. Referring to FIG. 4C, this circuit includes three-state buffers 501 and 502, a data selector 5
04.505t Read address counter 506. A bank counter 507 and a logic circuit 518 are provided.

Three-state buffer 501 receives mode signal BUSM
is active, that is, in BUS mode, general-purpose bus 1
Address signal line 2 for n+m pins 1 to 1 connected to 01
11 signals are output onto the signal line 503. The other three-state buffer 502 outputs the signal of the n + m-bit address signal line 233 connected to the scanner interface onto the signal line 503 when the mode signal HWRM is active, that is, in the HWR mode.

The read address counter 506 has a concrete configuration shown in FIG. 4d, and includes an m-bit endless main scanning counter 507 and an n-bit endless sub-scanning counter 508.

The value held by the latch 509 is applied to the preset input terminal of the main scanning counter 507 as an offset value. The main scanning counter 507 indicates that the synchronization signal LGATE is H (
When the offset value is loaded (preset) and LGATE is switched to L, counting of clock pulses IPCLK is started.

The value held by the latch 511 is applied to the preset input terminal of the sub-scanning counter 508 as an offset value. The sub-scanning counter 508 detects that the synchronization signal FGATE is H(
When FGATE is out of the effective scanning range in the sub-scanning direction), the offset value is loaded (preset), and when FGATE is switched to L, counting of the synchronization signal FGATE is started (8th
(See figure a).

In addition, in the MAC mode, the signals FGATE and LGA
Regardless of the state of TE, the main scanning counter 507
At the rising edge of CLK (see FIG. 8B), the sub-scanning counter 508 performs a counting operation using the carry output 516 of 507 (see FIG. 8C).

Therefore, in this embodiment, address information (m+n bits) indicating the scanning position is automatically generated within the read address counter 506. Therefore, there is no need for an external device that inputs and outputs image data to specify a memory address.

In addition, the latches 509 and 511 hold OffSera 1 to
By setting the value to a value other than 0, it is possible to add an offset between the scanning position of the externally applied synchronization signal and the position at which the frame memory is accessed. By using this, editing processing such as image movement and masking becomes possible, as will be explained next.

For example, by performing a copy operation with the main scanning offset value and sub-scanning offset value set to O for both writing and reading to the frame memory, an image as shown in FIG. 9a is obtained. In this case, if you set the main scanning offset value to a and the sub-scanning offset value to b and perform copying operation A1 of the same image only when reading the image, as shown in Fig. 9b, for the former case, 2 to the a power (pixels) in the negative direction of the main scanning direction
, the recorded image is shifted by 2 to the b power (line) in the negative direction of the sub-scanning direction. Similarly, only when reading one image, if you set the main scanning offset value to m-C and the sub-scanning offset value to nd and perform the copying operation of the same image as the former, the 9th C
As shown in the figure, the recorded image is shifted by 2 C pixels in the positive direction of the main scanning direction and by 2 D lines in the positive direction of the sub-scanning direction with respect to the original image.

Referring again to Figure 4c. Address information used to access one bank memory 800 is output to signal line 516, and address information used to access the other bank memory 900 is output to signal line 517. The former address information is the information on the signal line 503 and the signal 'l551.
5 is selected by the data selector 504, and the latter address information is selected by the signal 850.
3 and the information on the signal line 515 are selected by the data selector 505. These data selectors 504 and 505 are determined according to a combination of the states of the mode signal and the bank signal. The correspondence between the state of each signal and the information appearing on signal lines 516 and 517 is
It is shown in Table 2 below.

Table 2 Sub-scanning counter 50 in read address counter 506
The carry output from 8 appears on signal line 519. This signal is counted by bank counter 507. Bank counter 507 receives synchronization signal FGATE.
When FGATE is H (when the scanning position is outside the sub-scanning effective image area), it is in a reset state, and when FGATE becomes L, signal line 5
Count 19 signals. The carry output of the sub-scanning counter appearing on the signal line 519 means an overflow of the n+m pinpoint address, and therefore indicates that access to the memory corresponding to one bank has been completed. In other words, 1
When memory access to all addresses in one bank memory is completed, a carry output is generated and the bank counter 50
7 counts up. The value output from bank counter 507 is used to select each bank memory in HRD mode. Therefore, the value is automatically updated to 0, 1, 2, 3.4 each time access to each bank is completed, so in HRD mode, a special bank selection signal is applied from the outside and it is sequentially updated. Memory access across banks can be performed continuously without performing switching processing.

The configuration of the data control section 600 in FIG. 3 is shown in FIG. 4e.

Referring to FIG. 4e, this circuit is comprised of three sets of buffer circuits 610, 630 and 650. The configurations of these buffer circuits 610, 630 and 650 are shown in FIG. 4f, respectively.

This is shown in Figures 4g and 4h.

First, the buffer circuit 610 will be explained with reference to FIG. 4f. This circuit includes registers 611, 612, 613 for holding designated colors for each of R, G, and B, six buffers 615 to 620, and a logic circuit 614. Each of the buffers 615 to 620 is a bidirectional three-state buffer, and each has two sets of input/output data terminals, a gate terminal G, and a direction control terminal DIR. A signal WRITE is commonly applied to each terminal DIR, and a logic circuit 614 is applied to each gate terminal.
output signals are applied respectively.

The logic circuit 614 receives the color signals RS, GS, and BS output from the registers 611, 612, and 613, and the signal BUSM.
, BSI, BS2 and AS, the gate of each buffer is controlled by the logic shown in Table 3 below.

Table 3 Also, the direction of the signal of each buffer to be turned on is determined by the control signal 1
Controlled by tlRITE, if WRITE is 0, data is allowed to pass in the direction from the bus 210 to each bank memory, and if WRITE is 1, data is allowed to pass in the direction from each bank memory to the bus 210.

In addition to the combinations shown in Table 3 above, color signals R8, G
Set all S and BS to O, and control signal ΣWRITE to 0.
If set to , if BSI is 0 and l3S2 is 1,
Three buffers (615, 616, 617) are turned on at the same time, and when BS1 is 1 and 13S2 is 0, the other three buffers (618, 610, 620) are turned on at the same time. Therefore, if this mode is set, a general-purpose computer connected to the general-purpose bus can simultaneously write data into three sets of R, G, and H memories.

In that case, compared to accessing each memory sequentially,
Write speed is tripled.

Next, the buffer circuit 630 will be explained with reference to FIG. 4g. This circuit includes six buffers 632°633.6
34,636,637 and 638. logic circuit 631,
635 as well as latches 642-644.

These buffers 632 , 633 , 634 , 63
6, 637, and 638, only the direction from each bank memory to the interface 202 is permitted. The three buffers 632 to 634 are controlled on/off by a logic circuit 631, and the remaining buffers 636, 637, and 638 are controlled on/off by a logic circuit 635. Latches 642-644 are connected to the signal I
The signals output from each buffer are latched in synchronization with the falling edge of PCLK.

In other words, the image data output from the bank memory 800 passes through the buffers 632 to 634 and is sent to the bank memory 900.
The image data output from 0 is sent to buffers 636 to 638.
is output to the page printer 105 connected to the interface 202.

Next, the buffer circuit 650 will be explained with reference to FIG. 4h. This circuit includes six buffers 652°653.6
54,656,657 and 658. Logic circuits 651 and 655° data selectors 662, 663, 664. and background color registers 665, 666 and 667. These buffers 652, 653, 654, 6
The direction of data through the 63 buffers 652, 657 and 658 is only allowed from the interface 203 to each bank memory.
4 is on/off controlled by logic circuit 651, and the remaining buffers 656, 657 and 658 are controlled by logic circuit 651.
On/off control is performed by 55.

When the signal MACM is 1, that is, when it is not in MAC mode,
The data selectors 662 to 664 control the signal lines 230 to 230.
232 data are applied to each buffer and the signal MACM
When is O, that is, in the MAC mode, the background color data output from the background color registers 665 to 667 is applied to each buffer.

That is, in the MAC mode, the data written to the memory can be fixed to any background color, so the same background color can be written to all addresses in the bank memory. Writing in that case is performed at high speed.

Therefore, for example, when an image read by an image scanner is printed as a hard copy using a page printer, the color of the background portion on the hard copy can be changed by executing the MAC mode beforehand.

This type of background color change can also be done by a general-purpose computer accessing and editing bank memory, but this would take a very long time to perform. In the embodiment, it is preferable to execute the MAC mode because processing can be performed in a shorter time.

Please refer to Table 4 below, which shows the signal lines connected to each bank memory in each signal state according to the operation of the data control unit 600.

Table 4 *: Connected to plane 0 of R5, GS, BS The configuration of the RAM control unit 700 in FIG. 3 is shown in FIGS. 41 and 4j. The circuit shown in FIG.
The circuit shown in FIG. 4j is the circuit that controls the other bank memory 900.

First, referring to FIG. 41, each signal line 710 to 717
The following signals appear respectively.

710: n-bit R for DRAM in 800
RAM for R-plane DRAM in AS/CAS address 711:800
S712: CAS for R-plane DRAM in 800: CAS713: G-plane DRAM in 800
G plane DRA in RAs714:800 for
CAS715 for M: rlAs716 for B-plane DRAM in 800: CAS717 for B-plane DRAM in 800: Read/write signal for DRAM in 800 (read is H,
(Writing is L) Furthermore, the following signals appear on each of the signal lines 760 to 768 shown in FIG. 4j.

760: n-bit R for DRAM in 900
RAM for R-plane DRAM in AS/cAs address 761:900
S762: CAS for R-plane DRAM in RI00 CAS763: G-plane DRAM in 900
G plane DRA in RAs764:900 for
CAS765 for M: RAS for B-plane DRAM in 900 CAS766 for B-plane DRA in 900 CAS767 for old two: Read/write signal for DRAM in 900 (reading is 1-1
, writing is L) The states of the signals appearing on each signal line 711-717 and 761-767 change as shown in Table 5 below, depending on various control signals and modes. In addition.

The meaning of each symbol shown in Table 5 is as follows.

A Near active state NA: Inactive state * 1: Only the 0 plane signals of R5, GS, and ELS are active * 2: Active state when WRITE is 0 * 3
: Active state at the rising edge of IPCLK *4:
At the falling edge of WIE, the signal line 516 and the fourth signal line on the input side of the address selector 702 shown in FIG.
The signal line 5 on the input side of the address selector 752 shown in Figure j
17, address information of n+m bits is applied to each. Address selector 702 selects n+m bits,
n bits are output to the signal line 720, other n bits are output to the signal line 721, and the remaining n bits are output to the signal line 722.
Output to. Similarly, address selector 752 selects n+
Of the m bits, n bits are output to a signal line 770, the other n bits are output to a signal line 771, and the remaining n bits are output to a signal line 772.

A specific configuration of the address selector 702 is shown in the fourth figure. Fourth, referring to the figure, in this example n+m is 24 bits, 11 of which are connected to signal line 720.
It is output as an AS signal, and the other 11 bits are connected to the signal line 72.
1 as the RAS signal, and the remaining 2 bits are output to the signal line 722. Also, in this example, latch 791
By switching the data held in the data selectors 792 and 794, the information output to the signal line 720 and the information output to the signal line 722 can be switched to three types each.

Referring again to FIG. 41, in the signal line 710 on the output side of the logic circuit 701, the n-bit CAS address output to the signal line 720 and the n-bit RAS address output to the signal line 721 are different from each other. Output at the right time. Similarly, in the signal line 760 on the output side of the logic circuit 750 shown in FIG. 4j, the n-bit CAS address output to the signal line 770 and the n-bit RAS address output to the signal line 771 are different. Output at the right time. Please refer to FIG. 9d for an outline of these timings.

The configuration of bank memory 800 in FIG. 3 is shown in FIG. 4Q.

Referring to FIG. 4Q, R, G, and B plane memories are implanted in memory arrays 810, 820, and 830, respectively.

Each memory array is composed of a large number of integrated circuits, and has a total storage capacity of 2 to the nth power x 2 to the m power. The row address and column address, which are commonly applied to all integrated circuits, each have n bits, and are applied to each terminal via an n-bit signal line 710. In addition, the signal line 71
8 is 2 to the fifth power (b=m−n), and each signal line is used to select each integrated circuit chip.

Therefore, each plane memory has 2 n dots x 2
This is equivalent to having 2 to the b power of memory blocks in a two-dimensional array of n-th power lines. Which memory block is accessed is selected by signal a718.

Referring again to the fourth address selector shown in the figure, in this embodiment, by switching the data held in the latch 791, the combination of addresses output to the signal lines 720 and 722 can be changed. That is, in the first combination, the 24-bit internal address A12 to A22
is selected as a CAS address, A12 and Al1 are selected as chip select addresses, and in the second combination, A12 to A22 are selected as CAS addresses, A23 and A24 are selected as chip select addresses, and the third In the combination, A13 to A23 are selected as CAS addresses, and A12 and A24 are selected as chip select addresses.

In other words, in the first combination, four memory blocks of 2 to the nth power x 2 to the 0th power of focus are consecutively lined up in the main scanning direction, and as shown in FIG. ) is four times the number of bits in the sub-scanning direction (vertical direction), forming a memory plane with a two-dimensional array long in the horizontal direction.

In the second combination, four memory blocks are arranged consecutively in the sub-scanning direction, and as shown in FIG. 10b, the number of bits in the sub-scanning direction is equal to the number of bits in the main scanning direction.
This doubles to form a memory plane with a vertically long two-dimensional array. Furthermore.

In the third combination, two memory blocks are consecutively arranged in the main scanning direction and two in the sub-scanning direction, and the number of bits in the main scanning direction and the sub-scanning direction is 2 to the nth power, respectively.
2, resulting in a square two-dimensional array as shown in Figure 10c.

Therefore, in this embodiment, the two-dimensional arrangement of the frame 11 memory can be changed according to the shape of the image to be processed. In general, even if the amount of information in the original image is within the storage capacity of the frame memory, if the two-dimensional arrangement of the frame memory and the shape of the original image do not match, the image at the edge in the main scanning direction or sub-scanning direction will be distorted. In order to process images of various shapes, the storage capacity of the frame memory must have sufficient margin for the amount of information of the image to be processed. but,
In this embodiment, since the two-dimensional arrangement of the frame memory can be changed, as long as the storage capacity is equivalent to that of the original image, the image can be read into the frame memory and processed without causing any loss of information.

[Effect] As described above, according to the present invention, it is possible to set an arbitrary offset to the addresses generated by the main scanning address generation means and the sub-scanning address generation means, so that it is possible to set an arbitrary offset to the addresses generated by the main scanning address generation means and the sub-scanning address generation means. By shifting the offset,
Image movement can be executed very quickly and easily.

[Brief explanation of the drawing]

FIG. 1 shows one type of image processing system 1 implementing the present invention.
1 is a block diagram showing the configuration of FIG. 2a, 2b, 2c, and 2d are flowcharts showing the operation of the general-purpose computer of FIG. FIG. 3 is a block diagram showing a specific configuration of the frame memory 106 in FIG. 1. Figures 4a, 4b, 4c, 4d, 4e,
Figure 4f, Figure 4g, Figure 4h, Figure 41, Figure 4j,
FIG. 4 and FIG. 4Q are block diagrams showing specific configurations of each component shown in FIG. 3. FIG. 5a shows R, G in one bank memory. FIG. 5B is a block diagram showing the connection of the plane memories of B, and a map showing the arrangement of addresses of each plane memory.
FIG. 5c is a block diagram showing the connection state of a plurality of bank memories. 6a, 6b, 6c, and 6d are plan views of recorded images showing the results of image editing processing by changing bank assignments. FIGS. 7a and 7b are maps showing address assignments for each bank memory. FIGS. 8a, 8b, and 8c are time charts showing examples of the operation timing of the counter 506. FIG. FIGS. 9a, 9b, and 9c are plan views of recorded images showing the results of image editing processing by changing offset values. FIG. 9d shows tie 11 showing the operation of the RAM control section 700.
It's a chat. FIGS. 10a, 10b, and 10c are plan views showing two-dimensional arrays in each state of the plane memory realized by switching the address selector 702. FIG. 100: Printer controller 101: General-purpose bus (general-purpose bus means) 102: Central processing unit 103: Storage device 104:
Image scanner 105: Page printer 106: Frame memory 108: Task processor 110: General-purpose computer (offset value updating means) 201.20
2,203: Interface 300: Mode determination section 400: Bank selection section 401.402: Bank specification switch 403: Latch 405.406: Digital comparator 507: Main scanning counter (main scanning address generation means) 5
08: Sub-scanning counter (sub-scanning address generation means) 50
9: Latch (main scanning offset value holding means) 511: Latch (sub scanning offset value holding means) 600: Data control section 700: RAM control section

Claims (1)

[Scope of Claims] Frame memory means comprising a main scanning address bus and a sub-scanning address bus for specifying the address of the memory to be accessed; main scanning offset value holding means; sub-scanning offset value holding means; said main scanning offset value holding means A main scanning address that counts pixel synchronization signals output from a device that accesses the memory after loading the value held by the memory device as an initial value, and applies the counted value to the main scanning address bus of the frame memory means. Generation means: After loading the value held by the sub-scanning offset value holding means as an initial value, it counts the line synchronization signal output from the device that accesses the memory, and stores the counted value in the sub-scanning offset value holding means. A frame memory device comprising: sub-scanning address generating means for applying to a scanning address bus; and offset value updating means for updating values held by the main-scanning offset value holding means and the sub-scanning offset value holding means.