JPH02108173A - Information processor - Google Patents

Abstract

PURPOSE:To output images by various output devices by writing information in respective addresses of a frame memory means through 1st-3rd interface means corresponding to respective modes. CONSTITUTION:An access control means 600 allows the frame memory means to be accessed through a 3rd interface means 201 in 1st mode according to mode information held in a mode holding means and writes image information which is inputted from a 1st interface means 203 in the frame memory means according in 2nd mode to applied address information. In 3rd mode, on the other hand, the information stored in the frame memory means is outputted from a 2nd interface means 202 in order in synchronism with a specific synchronizing signal and in 4th mode, preset fixed information is written in respective addresses of the frame memory means through a 3rd interface means 201. Consequently, various images can be outputted on various kinds of output devices.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that inputs image information, performs predetermined processing, and outputs the information to a predetermined output device.

[Prior Art] Various systems have been known in the past for inputting information such as one image and recording it with a hard copy device. For example, the input image may be an image of bit pattern information read by an image scanner, encoded image information in vector format created by a computer,
A PDL (Page Descript Language) created on a device that performs desktop publishing.
e) Image information written in code, etc. The size of the input image varies depending on the model and the situation at the time. Further, as hard copy devices, laser printers, inkjet printers, thermal printers, etc. are used, but these have different printing speeds and recording sizes.

[Problems to be Solved by the Invention] As mentioned above, in conventional devices, the formats and input/output speeds of input images and output images handled by individual systems vary. Although there is no problem with the system, it was not possible to handle various image information as input images and output those images to various types of output devices.

An object of the present invention is to provide an information processing device that can input images in various formats and output the images using various types of output devices.

[Means for Solving the Problem] In order to achieve the above object, in the present invention, five pits 1
- Frame memory means for storing image information consisting of a collection of pattern information; Raster conversion means for converting coded image data into the bit pattern of the image it represents;
first interface means for inputting image information consisting of a collection of bit pattern information into said frame memory means; second interface means for outputting image information stored in said frame memory means; a third interface means connected to the processing means; a mode holding means holding mode information indicating one of four or more modes; and a third interface means connected to the processing means; allows access to the frame memory means via the third interface means, and in the second mode, the image information inputted from the interface means of the previous storage 1 is used as the address information applied from said means. In a third mode, the information stored in the frame memory means is sequentially outputted from the second interface means in synchronization with a predetermined synchronization signal, and in a fourth mode, An access control means is provided for writing preset fixed information into each address of the frame memory means via the third interface means.

[Operation] According to the present invention, by specifying the second mode,
Image data output by an image scanner or the like can be written to the frame memory means, and by specifying the third mode, the image data on the frame memory means can be output to a page printer or the like. Also, the first
By specifying this mode, image data created on a computer, etc. can be written to frame memory means, and furthermore, by passing it through raster conversion means, coded data such as vector format can be converted to bit pattern image data. It can be converted and written to frame memory. Furthermore, by specifying the fourth mode, any data can be written to the entire area of the frame memory means.
This allows you to change the image background color.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

[Embodiment] FIG. 1 shows the configuration of one type of image processing system that implements the present invention.

Referring to FIG. 1, the system includes an image scanner 104. Page printer 105. A printer controller 100 and a general-purpose computer 110 are provided. The image scanner 104 main-scans and sub-scans a document image positioned on its reading surface, and converts image information into R.
(Red).

Each of G (green) and B (blue) is sequentially output as independent 8-bit time-series gradation information.

In this example, a laser printer is used as the page printer 105. Image scanner 104. Printer controller 100 and page printer 105 are commonly connected to bus 101 of general-purpose computer 110 .

General-purpose computer 110 is a commercially available computer and includes a central processing unit (CPU) 102. Storage device 103. It is equipped with a keyboard 111 and a CRT 112. The central processing unit 102 has a general-purpose bus 101, which connects an image scanner 104 and a printer controller 100.
and a page printer 105.

The printer controller 100 includes a raster processor 10
8. Skyana Interface 120. It includes a frame memory 1069, an image processing section 107, and a printer interface 121. The raster processor 108 is a device that performs data format conversion, and in this embodiment, a CAD (Computer Aided Detailed Data)
vector format data and D handled by sign) systems, etc.
T P (De+k Top Publishing
) PDL (Page Descr) handled by the system
It has a function of converting data in Raster, ie, Bitmap, format at high speed. In this example, a vector format or PDL file created by general-purpose computer 110 is used.
A raster processor 108 is used to convert various types of image information into raster.

Either the image data output from the image scanner 104 or the image data output from the raster processor 108 is input to the frame memory 106 via the scanner interface 120.

Roughly speaking, the frame memory 106 has a function of storing image data input from an interface 120 according to a control signal applied from the interface 120, and a function of storing image data input directly from the general-purpose computer 110 via the general-purpose bus 101. It has a function of storing image data and a function of outputting the image data stored in the memory in synchronization with a control signal applied from the image processing unit 107.

The image processing unit 107 performs input γ correction on the image data input from the frame memory 106.

Various conventionally known processes such as color correction, scaling (enlargement/reduction), filter processing, and one-gradation processing are performed.

Furthermore, in order to accommodate various formats of one image, parameters for various processes can be set by the general-purpose computer 110 via the general-purpose bus 101.

The system shown in FIG. 1 has four operating modes that can be broadly classified. That is, in the first operation mode, the flow of image data is 104-120-106-10.
7-121-105.

An image read by an image scanner 104 is recorded by a page printer 105. In other words, the system operates as a copying machine. Please refer to FIG. 2a, which shows the processing contents of the CPU of the general-purpose computer 110 in this case.

In the second mode of operation, the image data flow is 10
3-102-1 (ll-108-120-106-10
It becomes 7-421-105. That is, the contents of the image information file in vector format or PDL format, which is stored in advance in the storage device 103 of the general-purpose computer 110, is recorded by the page printer 105. In this case, the data is converted from vector format or PDL format to raster format by raster processor 108 and then sent to page printer 105 . Please refer to FIG. 2b, which shows the details of the processing performed by the general-purpose computer 110 in this case.

In the third mode of operation, the image data flow is 1
03-102-1ot-106-107-121-10
It becomes 5. This mode is used when image data previously created in bitmap format exists on the general-purpose computer 110 and the image is to be recorded by the printer 105. The details of the processing performed by the general-purpose computer 110 in this case are shown in FIG. 2c.

In the fourth mode of operation, the image data flow is 1
04-120-106-101-102-103. That is, in this case, image information read by the image scanner 104 can be stored in the storage device 103 on the general-purpose computer 110. Please refer to FIG. 2d, which shows the details of the processing performed by the general-purpose computer 110 in this case.

As described above, in the system shown in Figure 1, this single system converts images in various formats into image information in the formats required by various types of page printers, and outputs it. Therefore, it is extremely versatile and can be used for a variety of purposes.

Next, the frame memory 106 shown in FIG. 1 will be specifically explained. The configuration of this frame memory.

It is shown in Figure 3.

Referring to FIG. 3, this device includes a first interface 201. which is connected to a general-purpose bus 101 of a general-purpose computer. A second interface 202 connected to a page printer. and a third interface 203 connected to the image scanner side, and are connected to various external devices via these interfaces.

That is, the general-purpose computer 110 can access the frame memory via the general-purpose bus 101 and the interface 201, and image data input from the image scanner 104 is input to the frame memory via the interface 203, and is sent from the frame memory to the page printer. Direct data output occurs via interface 202.

The signals applied to each interface will be briefly explained. Note that the overlined symbol in the drawings means that the signal is active when the signal is at a low level, but the overline is omitted from the description in the specification.

The signals applied to signal lines 220, 221 and 222 are:
These are synchronization signals output from the page printer, and are as follows.

FGATE...Frame synchronization signal indicating the effective image period of sub-scanning LGATE...Line synchronization signal IPCLK indicating the effective image period of main scanning...Clock pulse signal lines 233, 234 output for each pixel , 235 and 236 are signals output from the scanner interface 120, and are as follows.

Address: Image write address information consisting of n+m bits Write bank: Image write bank specification information consisting of N bits WE: Image write strobe TOGGLE: Toggle access (two banks of memory The main body of the frame memory includes a mode determining section 300, a bank selecting section 400, and a bank selecting section 400. Address control unit 500° data control unit 600.
RAM control section 700 and two bank memory sections 800,
900 is equipped.

The configuration of the mode determining section 300 is shown in FIG. 4a.

Referring to FIG. 4a, this circuit includes two registers 30 connected to an internal data bus 210 (101).
1, 302 and a logic circuit 303 for determining the mode. This circuit generates each mode signal according to the logic shown in Table 1 below according to the combination of states of various input signals, and outputs them to signal lines 304 to 308.

Table 1 However, the state of the signal indicated by II pg is irrelevant, that is,
The mode determining unit 300 selects five modes (BUS mode, HRD mode, HW
R mode, MAC mode, and GGLH mode) and outputs a signal indicating the mode. The operation of each mode is as follows.

BUS: A general-purpose computer accesses the frame memory via the general-purpose bus 101.

HRD: Reads data in the frame memory serially at high speed in synchronization with an external control signal.

HWR: Writes image data randomly to the frame memory at high speed in synchronization with an external control signal.

MAC: Rewrites the entire contents of the frame memory to pre-specified values at high speed. The end of the operation is determined by the address control unit 5.
It is identified by the signal line 519 connected to 00.

TOGGLE...Performs serial toggle access to two bank memories 800 and 900 in the frame memory.

In this example, each of the bank memories (800, 900) is configured as shown in Figure 5a.

That is, each has a storage capacity of n+m bits, and R2O, B
It has three plane memories, each allocated to a .

They are connected in common to the n+m bit address bus, that is, in parallel.

Referring to FIG. 5b, if different address areas are assigned to each memory plane for R, G, and B, the address space required to access the memory planes will increase according to the number of memory planes. When allocated in parallel to the same address, the address space is the same as the address space of one memory plane, regardless of the number of memory planes.6 In other words, when configured as shown in Figure 5a, the memory access The number of bits of the address bus required is reduced.

Also in this example, the bank memories are connected in parallel to the general-purpose bus 101, as shown in FIG. 5c, and each bank memory is arranged in the same address space when viewed from the general-purpose bus 101. Of course, multiple bank memories are not accessed simultaneously, but access is made selectively to a single bank memory. This selection is controlled by bank selection section 400 shown in FIG.

A specific configuration of the bank selection section 400 is shown in FIG. 4b.

Referring to Figure 4b, this circuit includes latches 403.
Logic circuit 411. Data selector 409.410. Digital comparator 405, 406° bank specification switch 401
．． 402 and gates 417 and 418.

The bank designation switches 401 and 402 each consist of a mechanical switch that outputs an N-bit numerical value6.
These switches may be constructed of, for example, non-volatile memory in which data can be rewritten by a general-purpose computer.

Each input terminal of the data selectors 409 and 410 has
Three sets of different N-bit bank selection information are applied, and one of them is selectively output by a data selector. The bank selection information output from the data selector 409 and the N-bit value output from the bank designation switch 401 are compared by the comparator 405, and if they match, a bank selection signal BSI is output. Similarly, the bank selection information output from the data selector 410 and the N-bit value output from the bank designation switch 402 are compared by the comparator 406, and if they match,
Bank selection signal BS2 is output.

One bank memory 80 is selected by bank selection signal BSI.
0 is selected, and the other bank memory 900 is selected by bank selection signal BS2.

Therefore, for example, if the bank designation switches 401 and 402 are set to 0 and l, respectively, the signal lines 413,
When the bank selection information appearing at 414 is 0 and 1, bank memories 800 and 900 are accessible, respectively.

In this embodiment, one circuit board constituting the frame memory is provided with two bank memories, so if four circuit boards are prepared, for example, eight sets of bank memories can be provided. In other words, each bank designation switch has, for example, o, l.

2. By setting the numerical values 3, 4, 5, 6, and 7, the bank memory corresponding to each bank designation switch will be assigned to different banks Q, l, 2, 3, 4° 5.6, and 7, respectively. It will be done.

A detailed explanation will be given later, but when reading and writing image information continuously, the address bus value is cleared to 0 every time the address bus value overflows, and the bank selection information is cleared accordingly. Incremented. That is, as the scanning position progresses, access is sequentially executed starting from the bank memory with the smallest bank value.

Therefore, for example, if eight bank memories are prepared in which address spaces of m bits in the main scanning direction and n bits in the sub-scanning direction are allocated as two-dimensional arrays, the bank value allocation of each of the eight bank memories is set to 0. ,1,2,3,
4, 5, 6 and 7, the two-dimensional memory arrangement of the entire frame memory is as shown in Figure 7b.

Therefore, when using this frame memory, continuous numerical values are normally assigned to the bank designation switches in order from 0. Thereby, a plurality of bank memories can be used as one continuous frame memory.

Furthermore, by changing the setting of the bank designation switch when writing image data and when writing successive image data, it becomes possible to edit images in bank area units. For example, the 0th. 1st. Second
．． Third. 4th. Fifth. Set the bank values (bank designation switch values) of the sixth and seventh bank memories to 0, 1, respectively.
A document image as shown in FIG. 6a is written in the frame memory with settings of 2, 3, 4 degrees 5.6 and 7 degrees, and then 0. 1st. Second. Third. 4th. Fifth. Set the bank values of the sixth and seventh bank memories to 0.1, 2, and 0.1, respectively.
5, 6, 7. If the data in the frame memory is read out sequentially after updating to 2 and 3, the read image will be in a different order than the original, that is, the image will be moved, as shown in Figure 6b. Be what you are. Similarly, after writing an image with the same bank value as the former, 0. 1st. Second. Third. 4th゜5th. The bank values of the sixth and seventh bank memories are
If the image data is read after changing the values to 0, 1, 2, 8, 9, 5.6 and 7, the memory of bank values 8 and 9 will not be accessed, so the read image will be the 6th c. As shown in the figure, it is partially masked. Also, after writing the same image with the same bank value as the former, switch the bank value to select only the third bank memory, write another image, return the bank value to the original, and read the image. , the read image is a partial composite of the first written image and the later written image. by this.

You can combine images.

In other words, according to this embodiment, editing processing such as image movement, masking, and composition can be performed using the size of each bank area of the frame memory.

This process only requires switching the bank value.

Can be processed in a short time.

When a general-purpose computer accesses the frame memory from general-purpose bus 101, the access is performed after selecting the bank to be written by writing N-bit bank selection information to latch 403. When multiple boards are connected to the general-purpose bus, the same value is written to the latch 403 of each board at the same time.

The logic circuit 411 identifies the current operation mode by referring to the mode signal, and selects the data selector 40 according to the result.
9,410 to switch the selected bank selection information. That is, in the BUS mode, HRD mode, HV, 7R mode, and TOGGLH mode, the signal line 40
4, 235, 234 and 234 information are selected and appear on signal lines 413 and 414.

Also, since the mode signal MACM is applied to the input terminals of the gates 417 and 418, the MAC mode odor hair is
Regardless of the outputs of comparators 405 and 406, signal BSI
, BS2 becomes active and all bank memories can be accessed simultaneously.

In addition, in this embodiment, since the signal line through which bank selection information is passed is N bits, 2<N> bank memories can be connected to 1
Can be connected in parallel to two general-purpose buses. In other words,
As total memory capacity.

Frame 11 memory up to 2 to the (N+n+m) power x 3 bytes can be constructed.

When arranging 2 to the power of (N+n+m) x 3 bytes of memory in a continuous address space, 1Usually, N+n+m+
Requires 2-bit address lines.

However, in this embodiment, each of the N punctures is connected in parallel to the same address space, as shown in FIG. Therefore, the number of signal line bits required for the address bus to access this frame memory only needs to be n+m. In other words, N
The number of address bus bits required to access the frame memory is reduced by +2 bits compared to normal. As a result, even if a large-capacity frame memory is required, image processing can be controlled by a computer using a general-purpose bus with a small number of bits.

The specific configuration of the address control unit 500 in FIG.
As shown in the figure. Referring to FIG. 4C, this circuit includes three-state buffers 501 and 502, a data selector 5
04,505. Read address counter 506. A puncture counter 507 and a logic circuit 518 are provided.

Three-state buffer 501 receives mode signal BUSM
is active, that is, in BUS mode, general-purpose bus 1
n0m bit address signal line 21 connected to 01
A signal of 1 is output onto the signal line 503. The other three-state buffer 502 outputs the signal of the n+m-bit address signal line 233 connected to the scanner interface onto the signal line 503 when the mode signal HWRM is active, that is, in the HWR mode.

The read address counter 506 has a concrete configuration shown in FIG. 4d, and includes an m-bit endless main scanning counter 507 and an n-bit endless sub-scanning counter 508.

The value held by the latch 509 is applied to the preset input terminal of the main scanning counter 507 as an offset value. The main scanning counter 507 receives the synchronization signal L G AT
When E is H (indicating outside the effective scanning range in the main scanning direction),
Load (preset) the offset value and
When switching to L, it starts counting the clock pulse IPCLK.

The value held by the latch 511 is applied to the preset input terminal of the sub-scanning counter 508 as an offset value. The sub-scanning counter 508 detects that the synchronization signal FGATE is H (
(indicates outside the effective scanning range in the WIJ scanning direction), load (preset) the offset value and set FGATE to L.
When it switches to , it starts counting the synchronization signal FGATE (
(See Figure 8a).

In addition, in the MAC mode, the signals FGATE and LGA
Regardless of the state of TE, the main scanning counter 507
At the rising edge of CLK (see FIG. 8B), the sub-scanning counter 508 performs a counting operation using the carry output 516 of 507 (see FIG. 8C).

Therefore, in this embodiment, address information (m 10n bits) indicating the scanning position is automatically generated within the read address counter 506. Therefore, there is no need for an external device that inputs and outputs image data to specify a memory address.

Furthermore, by setting the offset values held by the latches 509 and 511 to a value other than O, it is possible to provide an offset between the scanning position of the synchronization signal applied from the outside and the position at which the frame memory is accessed. By using this, editing processing such as image movement and masking becomes possible, as will be explained next.

For example, if a copy operation is performed with the main scanning offset value and sub-scanning offset value set to O both when writing to the frame memory and when writing successively, an image as shown in FIG. 9a is obtained. When copying the same image by setting the main scanning offset value to a and the FPI scanning offset value to b only when reading one image, as shown in Figure 9b, 2 to the a power (pixels) in the negative direction
, the recorded image is shifted by 2 to the b power (line) in the negative direction of the sub-scanning direction. Similarly, only when reading one image.

Main scanning offset value is m-c, sub-scanning offset value is n
-d and copying the same image as the former, as shown in Figure 9c, 2 C pixels in the positive direction of the main scanning direction and 2 C pixels in the positive direction of the sub-scanning direction with respect to the original image. 2 d
The recorded image shifts by the square line.

Referring again to Figure 4c. Address information used to access one bank memory 800 is output to signal line 516, and address information used to access the other bank memory 900 is output to signal line 517. The former address information is selected by the data selector 504 from either the information on the signal 8503 or the information on the signal line 515, and the latter address information is the information on the signal 1IA50.
3 and the information on the signal line 515 are selected by the data selector 505. These data selectors 504 and 505 are determined according to the combination of states of the mode signal and bank signal. The correspondence between the state of each signal and the information appearing in signals 1!516 and 517 is shown in Table 2 below.

Table 2 Sub-scanning counter 50 in read address counter 506
The carry output from 8 appears on signal line 519. This signal is counted by a bank counter 507.The bank counter 507 receives a synchronization signal FGAT.
When E is H (when the scanning position is outside the sub-scan effective image area), it is in a reset state, and when FGATE becomes L, the signal on the signal line 519 is counted. The carry output of the sub-scanning counter appearing on the signal line 519 means an overflow of the n+m bit address, and therefore indicates that access to the memory corresponding to one bank has been completed. That is, when memory access to all addresses in one bank memory is completed, a carry output is generated and the puncture counter 507 counts up. The value output by the puncture counter 507 is:

Used to select each bank memory in HRD mode. Therefore, the value is automatically updated to 0, 1, 2, 3.4 each time access to each bank is completed, so in HRD mode, a special bank selection signal is applied from the outside and it is sequentially updated. Memory access across banks can be performed continuously without performing switching processing.

The configuration of the data control section 600 in FIG. 3 is shown in FIG. 4e.

Referring to FIG. 4e, this circuit is comprised of three sets of buffer circuits 610, 630 and 650. The configurations of these buffer circuits 610, 630 and 650 are shown in FIG. 4f, respectively.

This is shown in Figures 4g and 4h.

First, to explain the buffer circuit 610 with reference to FIG. 4F, the circuit includes registers 611, 612, 613 for holding designated colors for each of R, G, and B, six buffers 615 to 620, and a logic circuit. 614.

Each of the buffers 615 to 620 is a bidirectional three-state buffer, and each includes two sets of input/output data terminals, a gate terminal G, and a direction control terminal DIR. , a signal WRITE is commonly applied to each terminal DIR, and an output signal of the logic circuit 614 is applied to each gate terminal.

A logic circuit 614 receives color signals R8, GS, and BS output from registers 611, 612, and 613.

Based on the signals BUSM, BS l, BS2 and AS,
The gates of each buffer are controlled by the logic shown in Table 3 below.

Table 3 Also, the direction of the signal of each buffer to be turned on is determined by the control signal 1
Controlled by i1RITE, if WRITE is 0, data is allowed to pass in the direction from the bus 210 to each bank memory, and if WRITE is 1, data is allowed to pass in the direction from each bank memory to the bus 210.

In addition to the combinations shown in Table 3, one color signal R3, G
Set all S and BS to O, and set the control signal WRITE to 0.
, if BSl is O and BS2 is 1, then 3
Two buffers (615, 616, 617) are turned on at the same time, and the BSI is 1. If BS2 is 0, the other 3
The three buffers (618, 619, 620) are turned on at the same time. Therefore, if this mode is set, a general-purpose computer connected to the general-purpose bus can simultaneously write data into three sets of R, G, and B memories. In this case, the writing speed is three times faster than when each memory is accessed sequentially.

Next, the buffer circuit 630 will be explained with reference to FIG. 4g. This circuit includes six buffers 632°633.6
34,636,637 and 63g, logic circuit 63
1,635 and latches 642-644. These buffers 632 , 633 , 634 ,
The only direction of data allowed to pass through 636 , 637 , and 638 is from each bank memory to the interface 202 . The three buffers 632 to 634 are controlled on/off by a logic circuit 631, and the remaining buffers 636, 637, and 638 are controlled on/off by a logic circuit 635. Latches 642 to 644 latch the signals output from each buffer in synchronization with the falling edge of signal IPCLK.

In other words, the image data output from the bank memory 800 passes through the buffers 632 to 634 and is sent to the bank memory 900.
The image data output from 0 is sent to buffers 636 to 638.
is output to the page printer 105 connected to the interface 202.

Next, the buffer circuit 650 will be explained with reference to FIG. 4h. This circuit includes six buffers 652°653.6
54,656,657 and 658. Logic circuits 651 and 655° data selectors 662, 663, 664. and background color registers 665, 666 and 667. These buffers 652, 653, 654, 6
The direction of data passing through 56, 657 and 658 is only allowed from the interface 203 to each bank memory. 3 buffers 652, 653 and 65
4 is on/off controlled by logic circuit 651, and the remaining buffers 656, 657 and 658 are controlled by logic circuit 651.
On/off control is performed by 55.

When the signal MACM is 1, that is, when it is not in MAC mode,
The data selectors 662 to 664 control the signal lines 230 to 230.
232 data are applied to each buffer and the signal MACM
When is 0, that is, in the MAC mode, the background color data output from the background color registers 665 to 667 is applied to each buffer.

That is, in the MAC mode, the data written to the memory can be fixed to any background color, so the same background color can be written to all addresses in the bank memory. Writing in that case is performed at high speed.

Therefore, for example, when an image read with an image scanner is hard-copied with a page printer.

If the MAC mode is executed prior to that, the color of the background portion on the hard copy can be changed.

This type of background color change can also be done by a general-purpose computer accessing and editing bank memory, but in that case it would take a very long time to perform the process, so this method is not recommended. In the embodiment, it is preferable to execute the MAC mode because processing can be performed in a shorter time.

Please refer to Table 4 below, which shows the signal lines connected to each bank memory in each signal state according to the operation of the data control unit 600.

Table 4 *: Connected to the O plane of R5, GS, and BS The configuration of the RAM control unit 700 in FIG. 3 is shown in FIGS. 41 and 4j. The circuit shown in FIG. 80
The circuit shown in FIG. 4j is the circuit that controls the other bank memory 900.

First, referring to FIG. 41, each signal line 710 to 717
The following signals appear respectively.

710: DRAM in 800 L and n-bit RAS/CAS address 711: RA for DRAM in R plane in 800
S712: CAS for R-plane DRAM in 800: CAS713: G-plane DRAM in 800
G-plane DRA in RAS714:800 for
CAS715 for M: RAS716 for B-plane DRAM in 800: CAS717 for B-plane DRAM in 800: Read/write signal for DRAM in 800 (reading is H1 writing is L) Also, each signal shown in FIG. 4j The following signals are cursed on lines 760-768, respectively.

760: n-bit R for DRAM in 900
RAM for R-plane DRAM in AS/CAS address 761:900
S762: CAS for R-plane DRAM in 900 CAS763: G-plane DRAM in 900
RAS764 for: D of G plane in 900
CAS765 for RAM: B in 900 RAS766 for DRAM in plane: B in 900
CAS767 for plain DRAM: 900
Read/write signal for DIilAM (read: H2 @ write: L) The states of the signals appearing on each signal line 711 to 717 and 761 to 767 are shown in Table 5 below according to various control signals and modes. It changes like this. In addition, the meaning of each symbol shown in Table 5 is as follows.

A near active state NA: Inactive state *1: Only the 0 plane signals of R5, GS, and BS are active *2: Active state when IdRITE is 0 *
3: Active state at the rising edge of ZPCLK *4
: Active state at the falling edge of 1ilE. Address information of n+m bits is applied to each of the signal line 516 on the input side of the address selector 702 shown in FIG. 41 and the signal line 517 on the input side of the address selector 752 shown in FIG. 4J. be done. The address selector 702 outputs n bits out of the %n+m bits to a signal line 720, the other n bits to a signal fi721, and the remaining n bits to a signal line 722. Similarly, address selector 752 outputs n bits out of n+m bits to signal line 770, the other n bits to signal line 771, and the remaining n bits to signal line 772.

A specific configuration of the address selector 702 is shown in the fourth figure. Fourth, referring to the figure, in this example n+m is 24 bits, 11 of which are connected to signal 8720.
It is output as an AS signal, and the other 11 bits are connected to the signal line 72.
1 as a RAS signal, and the remaining 2 bits are output as a signal fi722. Also, in this example, latch 79
By switching the data held at 1, the data selectors 792 and 794 can be controlled, and the information output to the signal line 720 and the information output to the signal line 722 can be switched to three types each.

Referring again to FIG. 41, in the signal line 710 on the output side of the logic circuit 701, the n-bit CAS address output to the signal line 720 and the n-bit RAS address output to the signal line 721 are different from each other. Output at the right time. Similarly, in the signal line 760 on the output side of the logic circuit 750 shown in FIG. 4j, the n-bit CAS address output to the signal line 770 and the n-bit RAS address output to the signal line 771 are different. Output at the right time. Please refer to FIG. 9d for an outline of these timings.

The configuration of bank memory 800 in FIG. 3 is shown in FIG. 4Q.

Referring to FIG. 4Q, each of the R, G, and B plane memories is composed of memory arrays 810, 820, and 830, respectively.

Each memory array is composed of a large number of integrated circuits, and has a total storage capacity of 2 to the nth power x 2 to the m power. The row address and column address, which are commonly applied to all integrated circuits, each have n bits, and are applied to each terminal via an n-bit signal line 710. In addition, the signal line 71
8 is 2 to the b power (b=m−n), and each signal line is used to select each integrated circuit chip.

Therefore, each plane memory has 2 n dots x 2
This is equivalent to having 2 to the b power of memory blocks in a two-dimensional array of n-th power lines. A signal line 718 selects which memory block to access.

Referring again to the fourth address selector shown in the figure, in this embodiment, by switching the data held in the latch 791, the combination of addresses output to the signal lines 720 and 722 can be changed. That is, in the first combination, the 24-bit internal address A14 to A24
is selected as a CAS address, Al1 and A13 are selected as chip select addresses, and in the second combination, A12 to A22 are selected as CAS addresses, A23 and A24 are selected as chip select addresses, and the third In the combination, A13 to A23 are selected as CAS addresses, and A12 and A24 are selected as chip select addresses.

In other words, in the first combination, four memory blocks of 2 to the nth power x 2 to the first power bits are consecutively lined up in the main scanning direction, and as shown in FIG. ) is four times the number of bits in the sub-scanning direction (vertical direction), forming a memory plane with a two-dimensional array long in the horizontal direction.

In the second combination, four memory blocks are arranged consecutively in the sub-scanning direction, and as shown in FIG. 10b, the number of bits in the sub-scanning direction is equal to the number of bits in the main scanning direction.
This doubles to form a vertically long two-dimensional memory plane. Furthermore, in the third combination, two memory blocks are arranged consecutively in the main scanning direction and two in the sub-scanning direction, and the number of bits in the main scanning direction and the sub-scanning direction are respectively 2 to the n power x 2. This results in a square two-dimensional array as shown in FIG. 10c.

Therefore, in this embodiment, the two-dimensional arrangement of the frame memory can be changed according to the shape of the image to be processed. In general, even if the amount of information in the original image is within the storage capacity of the frame memory, if the two-dimensional arrangement of frame 11 memory and the shape of the original image do not match, the image at the edge in the main scanning direction or sub-scanning direction will be distorted. In order to process images of various shapes, it is necessary to provide a sufficient margin in the storage capacity of the frame memory for the amount of information of the image to be processed, since the information will not fit in the frame memory and will be lost. However, in this embodiment, since the two-dimensional arrangement of the frame memory can be changed, as long as the storage capacity is equivalent to that of the original image, the image can be read into the frame memory and processed without causing any loss of information.

[Effects] As described above, according to the present invention, image data input as bit patterns from an image scanner, etc., and image data encoded as vectors and PDL generated by a computer can be handled in one system. , output image data can be output to a common output device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one type of image processing system implementing the present invention. Figures 2a, 2b, 2c and 2d. 2 is a flowchart showing the operation of the general-purpose computer of FIG. 1; FIG. 3 is a block diagram showing a specific configuration of the frame memory 106 in FIG. 1. Figures 4a, 4b, 4c, 4d, 4e,
Figure 4f, Figure 4g, Figure 4h, Figure 41, Figure 4j,
FIG. 4 and FIG. 4Q are block diagrams showing specific configurations of each component shown in FIG. 3. FIG. 5a shows R, G in one bank memory. FIG. 5B is a block diagram showing the connection of the plane memories of B, and FIG. 5B is a map showing the arrangement of addresses of each plane memory.
FIG. 5c is a block diagram showing the connection state of a plurality of bank memories. Figures 6a, 6b, 6c and 6d. FIG. 7 is a plan view of a recorded image showing the result of image editing processing by changing bank assignment. FIGS. 7a and 7b are maps showing address assignments for each bank memory. FIGS. 8a, 8b, and 8c are time charts showing examples of the operation timing of the counter 506. FIG. FIGS. 9a, 9b, and 9c are plan views of recorded images showing the results of image editing processing by changing offset values. FIG. 9d is a time chart showing the operation of the RAM control section 700. FIGS. 10a, 10b, and 10c are plan views showing two-dimensional arrays in each state of the plane memory realized by switching the address selector 702. FIG. 100: Printer controller 101: General-purpose bus 102: Central processing unit 103: Storage device 104: Image scanner 105: Page printer 106: Frame memory (frame memory means)
108: Raster processor (raster conversion means) 110:
General-purpose computer (image processing means) 201: Interface (third interface means) 202: Interface (second interface means) 203: Interface (first interface means) 300
:Mode determination section (mode holding means) 400:Bank selection section 401.402:Bank specification switch 403:Latch 405.406:Digital comparator 600:Data control section (access control means) 700:R
AM control section 800.900: Bank memory section ゛・Voice knee/Figure 2a, Figure 9, Figure 2 ([81 Figure a, Figure 4d, Figure e, Figure 50 ['71 Figure ζ, Figure b] Fig. 1a] Ob Fig. 10 (Fig.

Claims (1)

[Claims] Frame memory means for storing image information consisting of a collection of bit pattern information; Raster conversion means for converting coded image data into the bit pattern of the image it represents; consisting of a collection of bit pattern information a first interface means for inputting image information into the frame memory means; a second interface means for outputting the image information stored in the frame memory means; a third interface means for connecting the frame memory means with a predetermined image processing means. interface means; mode holding means for holding mode information indicating one of four or more modes; and, depending on the mode information held in the mode holding means,
In a first mode, access to the frame memory means is permitted via said third interface means, and in a second mode, image information input from said first interface means is applied from said means. in a third mode, sequentially outputting the information stored in the frame memory means from the second interface means in synchronization with a predetermined synchronization signal; In a fourth mode, an information processing apparatus comprising: access control means for writing preset fixed information into each address of the frame memory means via a third interface means.