JPH02108172A - Frame memory device - Google Patents

Abstract

PURPOSE:To utilize a general computer equipped with a general bus for control and image processing as it is by dividing a frame memory into plural banks and arranging the banks at the same addresses in parallel. CONSTITUTION:The bank memory means 800 and 900 are connected to the address bus of a general bus in parallel. Then identification numbers specified previously for the banks need to be written as a bank selection number in a selection bank information holding means from a data bus by respective bank specification switch means so that a computer accesses the bank memory means 800 and 900. For the purpose, different identification numbers are assigned to the bank specification switch means 401 and 402 to switch the bank memory means which are accessed. Consequently, the banks can be connected to the general bus consisting of a small number of bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame memory device used for storing image information and the like, and particularly to address assignment of a large number of memory elements included therein.

[Prior Art] For example, when attempting to perform various editing processes on an image read by an image scanner before printing, the information is input sequentially as time-series information, so all of the information must be The information is temporarily stored in memory, and then the memory in which the information is stored is accessed to perform editing processing. This type of memory is called frame memory.
Typically, very large storage capacity is required. for example,
When reading an A3 size image at a resolution of 16 pixels/mm, approximately 4 Mbytes are required even for two gradations of emitted color, and a color image requires at least 12 Mbytes.

[Problems to be Solved by the Invention] When performing complex image editing processing, the processing needs to be performed by a microcomputer or a general-purpose computer. However, since the frame memory has a very large storage capacity, its address space is considerably larger than that of a general computer, and in order to access the entire frame memory from the computer, the computer's address bus must be expanded. It won't happen. Therefore, general-purpose buses such as Mult, 1-Bus and VME-B
A computer equipped with an UG cannot be used as an image processing device as it is, and the hardware of the image processing device must be rebuilt.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a large-capacity frame memory device that can be accessed in its entirety even by a general computer using a general-purpose address bus with a small number of bits.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a general-purpose bus means connected to a predetermined processing means and including an address bus and a data bus; a plurality of connected bank memory means; bank designation switch means provided in each bank memory means and holding its own unique identification number; information applied to the data bus of the general-purpose bus means as a bank selection number selected bank information holding means for holding the selected bank information; comparison means provided in each bank memory means for comparing the identification number output from the bank designating switch means and the bank selection number output from the selected bank information holding means; and Access control means is provided for permitting access to the bank memory means with which the comparison results of the comparison means match and prohibiting access to the bank memory means that do not match.

[Operation] According to the present invention, since a plurality of bank memory means are connected in parallel to the address bus of the general-purpose bus, from the viewpoint of the processing means, that is, the computer, each bank memory means has the same address space. will be placed in In order for the computer to access each bank memory means, it is necessary to write the identification number previously designated to that bank by each bank designation switch means from the data bus to the selected bank information holding means as a bank selection number. be.

Therefore, by assigning different identification numbers to the respective bank designation switch means, the computer can switch the bank memory means to be accessed by switching the bank selection number written in the one selected bank information holding means.

Therefore, even if the total storage capacity of the frame memory connected to the address bus is very large, the address space required for the general-purpose address bus is 1.
Only one banked memory address space is required. In other words, for example, if a bank memory with a capacity of 1 MB is stored in 16
When a bank is prepared, the storage capacity of the frame memory is 16 Mbytes, but only 1 Mbyte of address space is required for the general-purpose bus, and the address space for the general-purpose bus is reduced. As a result, even when configuring a large-capacity frame memory, it can be directly connected to a general-purpose bus with a small number of bits (small address space), and there is no need to change the hardware on the processing unit side. .

In a preferred embodiment of the invention described below, each bank memory means has R (red), G (green) and B
(blue) and connect them in parallel to the address bus. Further, each plane memory means is provided with selected plane information holding means that can set plane selection information from the data bus, and control is performed so that access is permitted only to the plane selected by the plane selection information. According to this, the address space required for the general-purpose bus is further reduced to 1/3.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

[Embodiment] FIG. 1 shows the configuration of one type of image processing system that implements the present invention.

Referring to FIG. 1, the system includes an image scanner 104. Page printer 105. A printer controller 100 and a general-purpose computer 110 are provided. The image scanner 104 main-scans and sub-scans a document image positioned on its reading surface, and converts one image information into R.
(Red).

Each of G (green) and B (blue) is sequentially output as independent 8-bit time-series gradation information.

In this example, a laser printer is used as the page printer 105. Image scanner 104, printer controller 100, and page printer 105 are commonly connected to bus IO1 of general-purpose computer 1.10.

General-purpose computer 110 is a commercially available computer and includes a central processing unit (CPU) 102. Storage device 103. It is equipped with a keyboard 111 and a CRT1]2. The central processing unit 102 has a general-purpose bus 101, which connects an image scanner 104 and a printer controller 100.
and a page printer 105.

The printer controller 100 includes a raster processor 10
8. Skyana Interface 120. It includes a frame memory 1062, an image processing section 107, and a printer interface 121. The raster processor 108 is a device that performs data format conversion, and in this embodiment, a CAD (Computer Aided Detailed Data)
vector format data handled by systems such as sj, gn) and DTP (Desk Top Publishing).
g) PDR handled by the system (Page Des
crjpt; Data in Language (He) format,
It has a function of converting image data into raster, ie, bitmap format image data at high speed. In this example, a raster processor 108 is used to convert various image information in vector format or PDL format created by general-purpose computer 110 into raster.

Either the image data output from the image scanner 104 or the image data output from the raster processor 108 is input to the frame memory 106 via the scanner interface 120.

Roughly speaking, the frame memory 106 has a function of reading image data input from an interface 120 according to a control signal applied from the interface 120, and image information directly input from a general-purpose computer 110 via a general-purpose bus 101. It has a function to read the image data stored in the memory, and a function to output the image data stored in the memory in synchronization with the control signal applied from the image processing unit 107.

The image processing unit 107 performs input γ correction on the image data input from the frame memory 106.

Various conventionally known processes such as color correction, scaling (enlargement/reduction), filter processing 9, and darkening processing are performed.

Also to accommodate various formats of images.

Parameters for various processes can be set by a general-purpose computer 110 via a general-purpose bus 101.

The system shown in FIG. 1 has four operating modes that can be broadly classified. That is, in the first operation mode, the flow of image data is 104-12O-L06-+
It becomes 07-121-105.

An image read by an image scanner 104 is recorded by a page printer 105. In other words, the system operates as a copying machine. Please refer to FIG. 2a, which shows the processing contents of the CPU of the general-purpose computer 110 in this case.

In the second mode of operation, the image data flow is 10
3-102-101-108-120-106-107
-121-105. In other words, general-purpose computer 1
The contents of the image information file in vector format or PDL format stored in advance in the storage device 103 of 10 are
It is recorded by the page printer 105. The data in this case is sent to the page printer 105 after being converted from the vector format or PDL format to the Rask format by the Rask processor 108 . Please refer to FIG. 2b, which shows the details of the processing performed by the general-purpose computer 110 in this case.

In the third mode of operation, the image data flow is 1
03-102-101-106-107-121-10
It becomes 5. This mode is used when image data previously created in bitmap format exists on the general-purpose computer 110 and the image is to be recorded by the printer 105. The details of the processing performed by the general-purpose computer 110 in this case are shown in FIG. 2c.

In the fourth mode of operation, the image data flow is 1
04-120-106-1ot-102-103. That is, in this case, image information read by the image scanner 104 can be stored in the storage device 103 on the general-purpose computer 110. The details of the processing performed by the general-purpose computer 110 in this case are shown in FIG. 2d, which is referred to in t).

As described above, in the system shown in Figure 1, this single system converts images in various formats into image information in the formats required by various types of page printers, and outputs it. Therefore, it is extremely versatile and can be used for a variety of purposes.

Next, the frame memory 106 shown in FIG. 1 will be specifically explained. The configuration of this frame memory is shown in FIG.

Referring to FIG. 3, this device includes a first interface 201. which is connected to a general-purpose bus 101 of a general-purpose computer. A second interface 202 connected to a page printer. and a third interface 203 connected to the image scanner side, and are connected to various external devices via these interfaces.

That is, the general-purpose computer 110 can access the frame 11 memory via the general-purpose bus 101 and the interface 201, and image data input from the image scanner 104 is input to the frame memory via the interface 203, and from the frame 11 memory, the frame 11 memory can be accessed. Direct data output to is done via interface 202.

The signals applied to each interface will be briefly explained. Note that an overlined symbol in one drawing means that the signal is active when the signal is at a low level, but the overline is omitted from the description in the specification.

The signals applied to signal lines 220, 221 and 222 are:
These are synchronization signals output from the page printer, and are as follows.

FGATE: Frame synchronization signal indicating the effective image period of sub-scanning GATE: Line synchronization signal indicating the effective image period of main scanning IPCLK: Clock pulse signal line 233 output for each pixel; The signals applied to 234, 235, and 236 are output from the scanner interface 120, and are as follows.

Address: Image write address information consisting of n+m bits Write bank: Image write bank specification information consisting of N bits WE: Image write strobe TOGGLE: Toggle access (two banks of memory The main body of the frame memory includes a mode determining section 300, a bank selecting section 400 . Address control unit 500° data control unit 600.
RAM control section 700 and two bank memory sections 800,
900 is equipped.

The configuration of the mode determining section 300 is shown in FIG. 4a.

Referring to FIG. 4a, this circuit includes two registers 301 connected to an internal data bus 210 (101).
, 302 and a logic circuit 303 for determining the mode. This circuit generates each mode signal using the linear logic shown in Table 1 in accordance with the combination of states of various input signals and outputs them to signal lines 304-308.

Table 1 However, the state of the signal indicated by -'' is irrelevant. In other words, the mode determining section 300
It identifies five modes (BUS mode, HRD mode, HWR mode, MAC mode, and TOGGLE mode) and outputs a signal indicating the mode. The operation of each mode is as follows.

BUS: A general-purpose computer accesses the frame memory via the general-purpose bus 101.

HRD: Reads data in the frame memory serially at high speed in synchronization with an external control signal.

1-I WR: Writes image data to the frame memory randomly at high speed in synchronization with an external control signal.

MAC: Rewrites the entire contents of the frame memory to pre-specified values at high speed. The end of the operation is determined by the address control unit 5.
It is identified by the signal line 519 connected to 00.

TOGGLrE...Performs serial toggle access to two bank memories 800 and 900 in the frame memory.

In this example, each of the bank memories (800, 900) is configured as shown in Figure 5a.

That is, each has a storage capacity of n+m bits, and R2O, B
The three plane memories are connected in common to an n+m bit address bus, that is, in parallel.

Referring to FIG. 5b, if a different address area is assigned to each memory plane of R, G, and B, the address space required to access the memory plane increases according to the number of memory planes. are assigned to the same address in parallel, regardless of the number of memory planes.

The address space is the same as the address space of one memory plane 6 Thus, when configured as shown in FIG. 5a, the number of address bus bits required for the memory access thread 5 is reduced.

Also in this example, the bank memories are connected in parallel to the general-purpose bus 101, as shown in FIG. 5c, and each bank memory is arranged in the same address space when viewed from the general-purpose bus 101. Of course, multiple bank memories are not accessed simultaneously, but access is made selectively to a single bank memory. This selection is controlled by bank selection section 400 shown in FIG.

A specific configuration of the bank selection section 400 is shown in FIG. 4b.

Referring to Figure 4b, this circuit:

Latch 403. Logic circuit 411. Data selector 409
．． 410. Digital comparators 405, 406, bank designation switches 401, 402, and gates 417, 418 are provided.

Bank designation switches 401 and 402, respectively.

It consists of a mechanical switch that outputs an N-bit numerical value. Note that these switches may be configured with, for example, a nonvolatile memory whose data can be rewritten by a general-purpose computer.

Each input terminal of the data selectors 409 and 410 has
Three sets of different N-bit bank selection information are applied, and one of them is selectively output by a data selector. The bank selection information output from the data selector 409 and the N-bit value output from the bank designation switch 401 are compared by the comparator 405, and if they match, the bank selection signal BSI is output. Similarly, the bank selection information output from the data selector 410 and the N-bit value output from the bank designation switch 402 are compared by the comparator 406, and if they match,
Bank selection signal BS2 is output.

One bank memory 80 is selected by bank selection signal BSI.
0 is selected, and the other bank memory 900 is selected by bank selection signal l3S2.

Therefore, for example, if the bank designation switches 401 and 402 are set to O and l, respectively, the signal lines 413,
When the bank selection information appearing at 414 is 0 and 1, bank memories 800 and 900 are accessible, respectively.

In this embodiment, one circuit board constituting the frame memory is provided with two bank memories, so if four circuit boards are prepared, for example, eight sets of bank memories can be provided. That is, if you set the values of, for example, 0, 1° 2.3, 4, 5.6, and 7 to each bank designation switch.

The bank memory corresponding to each bank designation switch is
They are assigned to different banks 0, 1, 2, 3, 4°5.6 and 7, respectively.

A detailed explanation will be given later, but when reading and writing image information continuously, the address bus value is cleared to 0 every time the address bus value overflows, and the bank selection information is cleared accordingly. Incremented. That is, as the scanning position progresses, access is sequentially executed starting from the bank memory with the smallest bank value.

Therefore, for example, if eight bank memories are prepared in which address spaces of m bits in the main scanning direction and n bits in the sub-scanning direction are allocated as two-dimensional arrays, the bank value allocation of each of the eight bank memories is set to 0. ,1,2,3,
4.5.6 and 7, the two-dimensional memory arrangement of the entire frame memory is as shown in Figure 7b.

Therefore, when using this frame memory, continuous numerical values are normally assigned to the bank designation switches in order from 0. Thereby, a plurality of bank memories can be used as one continuous frame memory.

Furthermore, if the setting of the bank designation switch is changed between writing and reading image data, it becomes possible to edit the image in the bank area. For example, No. O1 No. 1. Second
．． Third. 4th. Fifth. Set the bank values (bank designation switch values) of the sixth and seventh bank memories to 0, 1, respectively.
2, 3, 4 degrees 5.6 and 7 degrees, write the original image as shown in FIG. Second. Third. 4th. Fifth. Set the bank values of the sixth and seventh bank memories to 0.1.2, respectively.
5, 6, 7, 2, and 3, and then sequentially read out the data in frame 11 memory, the read image is as follows.
As shown in FIG. 6b, the original is in a different order, that is, it has been moved. Similarly, after writing an image with the same bank value as the former, the O1 1st . Second. Third.
4th゜5th. Bank values of the sixth and seventh bank memories.

If you read out the image data after changing the values to 0, 1, 2, 8, 9, 5.6 and 7, the memory for bank values 8 and 9 will not be accessed, so the image to be read will be the 6th C. As shown in the figure, it is partially masked. Also, after writing the same image with the same bank value as the former, switch the bank value to select only the third bank memory, write another image, return the bank value to the original, and read the image. , the read image is a partial composite of the first written image and the later written image. This allows images to be combined.

In other words, according to this embodiment, editing processing such as image movement, masking, and composition can be performed using the size of each bank area of the frame memory.

This process can be performed in a short time because it only requires switching the bank value.

When a general-purpose computer accesses the frame memory from general-purpose bus 101, the access is performed after selecting the bank to be written by writing N-bit bank selection information to latch 403. When multiple boards are connected to the general-purpose bus, the same value is written to the latch 403 of each board at the same time.

The logic circuit 411 identifies the current operating mode by referring to the mode signal, and selects the data selector 4 according to the result.
09,419 to be selected. That is, in the BUS mode, I (RD mode, HWR mode, and TOGGLE mode).

Information on signal lines 404, 235, 234 and 234 is selected and appears on signal lines 413 and 414, respectively.

Furthermore, since the mode signal MACM is applied to the input terminals of gates 417 and 418, in the MAC mode,
Regardless of the outputs of comparators 405 and 406, signal BSI
, BS2 becomes active and all bank memories can be accessed simultaneously.

In addition, in this embodiment, since the signal line through which bank selection information is passed is N bits, 2<N> bank memories can be connected to 1
6 that can be connected in parallel to 2 general-purpose buses, i.e.
As a total memory capacity, a frame memory up to 2 to the power of (N+n+m)×3 bytes can be constructed.

When arranging 2 to the power of (N+n+m) x 3 bytes of memory in a continuous address space, normally N + n
+ m + 2 bit address lines are required.

However, in this embodiment, each of the N banks is connected in parallel to the same address space, as shown in FIG. Therefore, the number of signal line bits required for the address bus to access this frame memory only needs to be n+m. In other words,
The number of address bus bits required to access the frame memory is smaller than usual by N+2 bits. As a result, even if a large-capacity frame 11 memory is required, image processing can be controlled by a computer using a general-purpose bus with a small number of bits.

The specific configuration of the address control unit 500 in FIG.
As shown in the figure. Referring to FIG. 4C, this circuit includes three-state buffers 501 and 502, a data selector 5
04,505. Read address counter 506. A bank counter 507 and a logic circuit 518 are provided.

Three-state buffer 501 receives mode signal BUSM
is active, that is, in BUS mode, general-purpose bus 1
n+m bit address signal line 21 connected to 01
A signal of 1 is output onto the signal line 503. The other three-state buffer 50.2 receives a mode signal 1-(W
When the RM is active, that is, in the HWR mode, the signal from the n+m bit address signal line 233 connected to the scanner interface is output onto the signal line 503.

The read address counter 506 has a concrete configuration shown in FIG. 4d, and includes an m-bit endless main scanning counter 507 and an n-bit endless sub-scanning counter 508.

The value held by the latch 509 is applied to the preset input terminal of the main scanning counter 507 as an offset value. The main scanning counter 507 receives the synchronization signal L G AT
When F is H (indicating outside the effective scanning range in the main scanning direction), the offset value is loaded (preset) and LGAT
When E switches to L, it starts counting the clock pulses IPCLK.

The value held by the latch 511 is applied to the preset input terminal of the sub-scanning counter 508 as an offset value. The sub-scanning counter 508 receives the synchronization signal FGATE from I-
When it is 1 (indicating outside the effective scanning range in the sub-scanning direction), load (preset) the offset value and set FGATE to L.
When it switches to , it starts counting the synchronization signal FGATE (
(See Figure 8a).

In addition, in the MAC mode, the signals FGATE and LGA
Regardless of the state of TE, the main scanning counter 507
At the rising edge of CLK (see FIG. 8b), the sub-scanning counter 508 performs a counting operation using the carry output 516 of 507 (see FIG. 8c).

Therefore, in this embodiment, address information (m+n bits) indicating the scanning position is automatically generated within the read address counter 506. Therefore, there is no need for an external device that inputs and outputs image data to specify a memory address.

Furthermore, by setting the offset values held by the latches 509 and 511 to values other than 0, an offset can be added between the scanning position of the synchronization signal applied from the outside and the position at which the frame memory is accessed. By using this, editing processing such as image movement and masking becomes possible, as will be explained next.

For example, if a copy operation is performed with the main scanning offset value and WJ scanning offset value set to 0 for both writing and reading to the frame memory, and an image as shown in FIG. 9a is obtained. In addition, when copying the same image by setting the main scanning offset value to a and the sub-scanning offset value to b only when reading the image, as shown in Fig. 9b, the difference in the main scanning direction with respect to the former 2 to the a power (pixels) in the negative direction,
The recorded image is shifted by 2 to the b power (lines) in the negative direction of the sub-scanning direction. Similarly, when copying the same image as the former with the main scanning offset value set to m-c and the sub-scanning offset value set to nd only during image reading, the 9th c
As shown in the figure, the recorded image is shifted by 2 C pixels in the positive direction of the main scanning direction and by 2 D lines in the positive direction of the sub-scanning direction with respect to the original image.

Referring again to Figure 4c. Address information used to access one bank memory 800 is output to signal line 516, and address information used to access the other bank memory 900 is output to signal line 517. The former address information is obtained by selecting either the information on the signal line 503 or the information on the signal line 515 by the data selector 504, and the latter address information is obtained by selecting either the information on the signal line 503 or the information on the signal line 515. is selected by the data selector 505. These data selectors 504 and 505 are determined according to the combination of states of the mode signal and bank signal. The following Table 2 shows the correspondence between the states of each signal and the information cursed by the signal lines 516 and 517.

Sub-scan counter 50 in read address counter 506 in Table 2
The carry output from 8 appears on signal line 519. This signal is counted by bank counter 507. The puncture counter 507 receives the synchronization signal FGATE.
When it is OFF (when the scanning position is outside the sub-scanning effective image area), it is in a reset state, and when FGATE becomes L, the signal on the signal line 519 is counted. The carry output of the sub-scanning counter appearing on the signal line 519 means an overflow of the n+m bit address, and therefore indicates that access to the memory corresponding to one bank has been completed. That is, when memory access to all addresses in one bank memory is completed, a carry output is generated and the puncture counter 507 counts up. puncture counter 507
The value output by is used to select each bank memory in 1-I RD mode. Therefore, the value changes to 0, 1, 2, 3.4 each time the access to each bank is completed.
In HRD mode, memory access across banks can be performed continuously without applying a special external bank selection signal and sequentially switching between banks. can.

The configuration of the data control section 600 in FIG. 3 is shown in FIG. 4e.

Referring to FIG. 4e, this circuit is comprised of three sets of buffer circuits 610, 630 and 650. The configuration of these buffer circuits 610, 630 and 65゛0 is as follows:
Figure 4f, respectively.

This is shown in Figures 4g and 4h.

First, the buffer circuit 610 will be explained with reference to FIG. 4f. This circuit includes registers 611, 612, 613 for holding designated colors for each of R, G, and I3, six buffers 615 to 620, and a logic circuit 614. Each of the buffers 615 to 620 is a bidirectional three-state buffer, and each has two sets of input/output data terminals, a gate terminal G, and a direction control terminal DIR.
It is equipped with A signal WRITE is commonly applied to each terminal DIR, and a logic circuit 614 is applied to each gate terminal.
output signals are applied respectively.

The logic circuit 614 receives the color signals R3, GS, and BS output from the registers 611, 612, and 613, and the signal BUSM.
, BSI, BS2 and AS, the gate of each buffer is controlled by the logic shown in Table 3 below.

Table 3 Also, the direction of the signal of each buffer to be turned on is determined by the control signal W
Controlled by RITE, if RITE is 0, bus 2
Data is allowed to pass in the direction from 10 to each bank memory, and if WRITHE is 1, data is allowed to pass in the direction from each bank memory to bus 210.

In addition to the combinations shown in Table 3 above, color signals R5, G
Set all S and BS to O, and set the control signal WRITE to 0.
, if BSI is 0 and BS2 is 1, then 3
Two buffers (615, 616, 617) are turned on at the same time, and the BSI is 1. If BS2 is 0, the other 3
The three buffers (618, 619, 620) are turned on at the same time. Therefore, if this mode is set, a general-purpose computer connected to the general-purpose bus can simultaneously write data into three sets of R, G, and H memories. In this case, the writing speed is three times faster than when each memory is accessed sequentially.

Next, the buffer circuit 630 will be explained with reference to FIG. 4g. This circuit includes six buffers 632°633.6
34, 636, 637 and 638, logic circuit 63
1,635 and latches 642-644. These buffers 632, 633, 634, 636
, 637, 638, only the direction from each bank memory to the interface 202 is permitted. Three buffers 632 to 634 are logic circuits 63
1 and the remaining buffer 636
637 and 638 are on/off controlled by a logic circuit 635. The latches 642 to 644 are
The signals output from each buffer are latched in synchronization with the falling edge of CLK.

In other words, the image data output from the bank memory 800 passes through the buffers 632 to 634 and is sent to the bank memory 900.
The image data output from 0 is sent to buffers 636 to 638.
is output to the page printer 105 connected to the interface 202.

Next, the buffer circuit 650 will be explained with reference to FIG. 4h. This circuit includes six buffers 652°653.6
54,656,657 and 658. Logic circuits 651 and 655° data selectors 662, 663, 66/1 and background color registers 665, 666 and 667 are provided. These buffers 652,653,654
, 656, 657, and 658, only the direction from the interface 203 to each bank memory is permitted. The three buffers 652, 653 and 654 are controlled on/off by a logic circuit 651, and the remaining buffers 656, 657 and 658 are controlled on/off by a logic circuit 655.

When the signal MACM is 1, that is, when it is not in MAC mode,
The data selectors 662 to 664 control the signal lines 230 to 230.
232 data are applied to each buffer and the signal MΔCM
When is O, that is, in the MAC mode, the background color data output from the background color registers 665 to 667 is applied to each buffer.

That is, in the MAC mode, the data written to the memory can be fixed to any background color, so the same background color can be written to all addresses in the bank memory. Writing in that case is performed at high speed.

Therefore, for example, when an image read by an image scanner is printed as a hard copy using a page printer, the color of the background portion on the hard copy can be changed by executing the MAC mode beforehand.

This kind of background color change can also be done by a general-purpose computer accessing and editing the bank memory, but in that case it would take a very long time to perform the process, so this example In this case, it is preferable to execute the MAC mode because the processing can be performed in a shorter time.

Please refer to Table 4 below, which shows the signal lines connected to each bank memory in each signal state according to the operation of the data control unit 600.

Table 4 *: Connected to plane 0 of R5, GS, BS The configuration of the RAM control unit 700 in FIG. 3 is shown in FIGS. 41 and 4j. The circuit shown in FIG.
The circuit shown in FIG. 4j is the circuit that controls the other bank memory 900.

First, referring to FIG. 41, each signal line 710 to 717
The following signals appear respectively.

710: n-bit R for DRAM in 800
[t for R-plane DRAM in AS/CAS address 711:800
CAS713 for R-plane DRAM in AS712:800: DIIAM in G-plane in 800
IIAS714 for: CAS715 for G-plane DRAM in 800: RAS716 for B-plane DRAM in 800: CAS717 for B-plane ORAM in 800
Read/write signal for DRAM in 0 (read: ■t, write: L) Further, the following signals appear on each of the signal lines 760 to 768 shown in FIG. 4j.

760: RAS/CAS address of n pin 1 to DRAM in 900 761: R for DrlAM of R plane in 900
AS762: R-plane DRAM in 900 CAS763: G-plane DRA in 900
1ilAs764 for M: CAS765 for G-plane DRAM within 900: B within 900
RAS766 for plain DRAM: 900
CAS767 for B-plane ORAM in:
Read/write signals for the DRAM in 900 (read is H, write is L) The states of the signals appearing on each signal line 711 to 717 and 761 to 767 are shown in Table 5 below according to various control signals and modes. Change as shown. The meaning of each symbol shown in Table 5 is as follows. 6A near active state NΔ: Non-active state *1: Only the 0 plane signals of R5, GS, BS are active *2: When WRITE is 0 Active state*3
: Active state at the rising edge of IPCLK *4:
At the falling edge of WE, the signal line 516 on the input side of the address selector 702 shown in FIG.
Signal line 51 on the input side of address selector 752 shown in the figure
7 are applied with n+m bits of address information. The address selector 702 selects n out of n0m bits.
The bit is output to a signal line 720, the other n bits are output to a signal line 721, and the remaining n bits are output to a signal line 722. Similarly, address selector 752 selects n+m
Of the bits, n bits are output to a signal line 770, the other n bits are output to a signal line 771, and the remaining n bits are output to a signal line 772.

A specific configuration of the address selector 702 is shown in the fourth figure. Fourth, referring to the figure, in this example n+m is 24 bits, 11 of which are connected to signal line 720.
It is output as an AS signal, and the other 11 bits are connected to the signal line 72.
1 as the RAS signal, and the remaining 2 bits are output to the signal line 722. Also, in this example, latch 791
By controlling the data selectors 792 and 794, the information output to the signal line 720 and the information output to the signal line 722 can be switched to three types each.

Referring again to FIG. 41, in the signal line 710 on the output side of the logic circuit 701, the n-bit CAS address output to the signal line 720 and the n-bit RAS address output to the signal line 721 are different from each other. Output at the right time. Similarly, in the signal line 760 on the output side of the logic circuit 750 shown in FIG. 4j, the n-bit CAS address output to the signal line 770 and the n-bit RAS address output to the signal line 771 are different. Output at the right time. Please refer to FIG. 9d for an outline of these timings.

The configuration of bank memory 800 in FIG. 3 is shown in FIG. 4a.

Referring to FIG. 4Q, each of the R, G, and B plane memories is composed of memory arrays 810, 820, and 830, respectively.

Each memory array is composed of a large number of integrated circuits, and has a total storage capacity of 2 to the nth power x 2 to the m power. The row address and column address, which are commonly applied to all integrated circuits, each have n bits, and are applied to each terminal via an n-bit signal line 710. In addition, the signal line 71
8 is 2 to the fifth power (b=m−n), and each signal line is used to select each integrated circuit chip.

Therefore, each plane memory has 2 n dots x 2
This is equivalent to having 2 to the b power of memory blocks in a two-dimensional array of n-th power lines. A signal line 718 selects which memory block to access.

Referring again to the fourth address selector shown in the figure, in this embodiment, by switching the data held in the latch 791, the combination of addresses output to the signal lines 720 and 722 can be changed. That is, in the first combination, the 24-bit internal address A14 to A24
is selected as the CAS address, Al1 and A13 are selected as the chip select address, in the second combination, ζA12 to A22 are selected as the CAB address, A2.3 and A24 are selected as the chip select address, and the third In the combination, A13 to A23 are CAS
A12 and A24 are selected as addresses for chip selection.

In other words, in the first combination, four memory blocks of 2 to the nth power x 2 to the first power bits are consecutively lined up in the main scanning direction, and as shown in FIG. ) is four times the number of bits in the sub-scanning direction (l/1 direction), forming a memory plane with a two-dimensional array long in the horizontal direction.

In the second combination, four memory blocks are arranged consecutively in the sub-scanning direction, and as shown in FIG. 10b, the number of bits in the sub-scanning direction is equal to the number of bits in the main scanning direction.
This doubles to form a vertically long two-dimensional memory plane. Furthermore.

In the third combination, two memory blocks are consecutively arranged in the main scanning direction and two in the sub-scanning direction, and the number of bits in the main scanning direction and the sub-scanning direction is 2 to the nth power, respectively.
2, resulting in a square two-dimensional array as shown in Figure 10c.

Therefore, in this embodiment, the two-dimensional arrangement of the frame memory can be changed according to the shape of the image to be processed. In general, even if the amount of information in the original image is within the storage capacity of the frame memory, if the two-dimensional arrangement of the frame memory and the shape of the original image do not match, the image at the edge in the main scanning direction or sub-scanning direction will be In order to process images of various shapes, the storage capacity of the frame memory must have sufficient margin for the amount of information of the image to be processed. However, in this embodiment, since the two-dimensional arrangement of the frame memory can be changed, as long as the storage capacity is equivalent to that of the original image, the image can be read into the frame memory and processed without causing any loss of information.

[Effect] As described above, according to the present invention, the frame memory is divided into multiple banks and each bank is arranged in parallel at the same address, so even if the storage capacity of the entire frame memory is large, the memory The number of address bits required to access can be reduced, so a general computer equipped with a general-purpose bus can be used as is for control and image processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one type of image processing system implementing the present invention. 2a, 2b, 2c, and 2d are flowcharts showing the operation of the general-purpose computer of FIG. FIG. 3 is a block diagram showing a specific configuration of the frame memory 106 in FIG. 1. Figure 4a, Figure 4b, Figure 4c, Figure 4d, Figure 4e 2
Figure 4f, Figure 4g, Figure 4h, Figure 41, Figure 4j,
FIG. 4 and FIG. 4Q are block diagrams showing specific configurations of each component shown in FIG. 3. FIG. 5a shows R, G in one bank memory. FIG. 5B is a block diagram showing the connection of the plane memories of B, and a map showing the arrangement of addresses of each plane memory.
FIG. 5c is a block diagram showing the connection state of a plurality of bank memories. 6a, 6b, 6c, and 6d are plan views of recorded images showing the results of image editing processing by changing bank assignments. FIGS. 7a and 7b are maps showing address assignments for each bank memory. FIGS. 8a, 8b, and 8c are time charts showing examples of the operation timing of the counter 506. FIG. FIGS. 9a, 9b, and 9c are plan views of recorded images showing the results of image editing processing by changing offset values. FIG. 9d shows tie 11 showing the operation of the RAM control section 700.
It's a chat. FIGS. 10a, 10b, and 10c are plan views showing two-dimensional arrays in each state of the plane memory realized by switching the address selector 702. FIG. 100: Printer controller 101: General-purpose bus (general-purpose bus means) 102: Central processing unit 103: Storage device 104:
Image scanner 105: Page printer 106: Frame memory 108: Task processor 110: General-purpose computer 201, 202, 203: Interface 300:
Mode determination section 400: Bank selection section 401.402
: Bank designation switch (bank designation switch means) 403 : Latch (selected bank information holding means) 405.4
06: Digital comparison device (comparison means) 600: Data control section

Claims (2)

[Claims] (1) General-purpose bus means connected to a predetermined processing means and including an address bus and a data bus; connected in parallel to the address bus of the general-purpose bus means;
a plurality of bank memory means; bank designation switch means provided in each bank memory means and holding its own unique identification number; selection for holding information applied to the data bus of the general-purpose bus means as a bank selection number bank information holding means; comparison means provided in each bank memory means for comparing the identification number outputted by the bank designation switch means and the bank selection number outputted by the selected bank information holding means; and the comparison means A frame memory device comprising: access control means for permitting access to bank memory means whose comparison results match and prohibiting access to bank memory means for which the comparison results do not match. (2) Each of the bank memory means is connected to three or more plane memory means, and a selected plane information holding means that is connected to each of them and holds information applied to the data bus of the general-purpose bus as plane selection information. The access control means permits access to the plane memory means selected by the plane selection information among the bank memory means to which access is permitted, and prohibits access to other plane memory means. A frame memory device according to claim (1).