KR100228788B1 - Dynamic structure method and circuit of memory in color printing system - Google Patents

Abstract

The present invention provides data buses which are used as data input / output paths of cyan, magenta, and yellow color data in order to efficiently utilize memory in a printing system using a surface sequential method; A predetermined number of memories arranged in a row direction are commonly connected to each data bus; In the first mode, a selected row of memories connected to each data bus is connected to the corresponding data bus. In the second mode, the same number of memories as the number of data buses in a row of memory are connected to each data bus. It has a control means for controlling to be connected one by one.

Description

Dynamic Configuration Method and Circuit of Memory in Color Printing System

1 is a block diagram showing a memory configuration in a color printing system according to the prior art.

2 is a table for explaining memory selection in accordance with the present invention.

3 is a circuit block diagram for explaining the configuration of the memory circuit of the present invention.

4 is a detailed circuit diagram of a decoder circuit in FIG. 3, and

FIG. 5 is a detailed circuit diagram of the data pass buffer of FIG.

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to the field of color printing systems for printing printing data applied from an image processing system and the like, and more particularly, to a construction method and apparatus for efficiently utilizing a memory used in a printing system using a surface sequential method. will be.

Typically, color printers are known in the art for thermal sublimation, ink jet, silver salt photography, electrophotographic methods, and the like. Among them, an electrophotographic printer or a thermal sublimation printer is attracting more attention from users because it shows excellent performance as a color image output device. Such printers typically perform printing by surface sequential method. That is, the surface sequential means printing three types of basic dyes C, M, and Y one by one in turn. Thus, the color to be printed is made by first printing a cyan color on one side and then printing the magenta and yellow colors on top of each other.

In order to print the color to be printed on the printing paper as described above, the printer usually needs a memory for storing the color image. For example, to store A4 paper size (8.5 "x 11") natural color images at 300 dpi (dots per inch), the memory capacity is about 8.5 Mbyte per color (C, M, Y). The total memory capacity should be about 25.5Mbytes. This is because 8 bits of C, M, and Y are required to express natural colors of one pixel, that is, 24 bits of capacity are required.

Conventionally, as shown in FIG. 1, twelve memories having one RAM memory capacity of 2 Mbytes are installed in the printer. An operation for circuit configuration and printing of a conventional memory will be described below with reference to FIG.

In FIG. 1, color information C, M, and Y necessary for printing are sequentially stored in a memory 100 having a total memory capacity of 24 Mbytes. In the case of storage, C is inputted as D [0: 7], M as D [8:15], and Y as D [16:23]. When the stored color data is read and printed, the stored color data is read from C. That is, when printing C, C data is sequentially output from RAMs 0, 3, 6, and 9 of the memory 100 and applied to the output terminal of the printer. Next, M is output from RAM 1, 4, 7, and 10, and then Y is output from RAM 2, 5, 8, and 11 in turn and sent to the output terminal. Here, a total of 23 bits is required for an address, and 21 bits of [20: 0] are commonly applied to each RAM. The upper two bits of the 23-bit address are used to generate a chip selector / CS (chip select) signal of the memory 100. Here, the selection logic of the four chip selector signals / CS1- / CS3 is shown in Table-1 below.

Table-1

According to the memory configuration of FIG. 1, the operation of storing data in the memory is such that the color data corresponding to the next pixel can be stored after outputting all three color data of C, M, and Y three times. It was. That is, after all three color data constituting one pixel are read, the storage operation is sequentially performed again. Therefore, before the read time period of the data corresponding to the Y color of the previous cycle is over, even if the memory space of C and M is empty, the data cannot be input in advance. In this case, the input color data to be stored is received in units of C, M, and Y 24 bits. Therefore, even if you want to print a number of different pictures, the printer can store the image data in memory, then print them all, and then store the next image. Therefore, the waiting time for printing is long and the empty memory space cannot be utilized in advance.

Therefore, as mentioned above, the memory configuration in the conventional printer has a problem in that the overall printing performance is not good. As a result, the speed of the printing operation did not meet the expectations of the user.

Accordingly, an object of the present invention is to provide a dynamic configuration method of a memory in a printer that can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a memory configuration method capable of increasing the printing speed of a printer.

According to the present invention for achieving the above objects, the data bus is used as a data input and output path of each of the cyan, magenta, yellow color data; A predetermined number of memories arranged in a row direction are commonly connected to each data bus; In the first mode, a selected row of memories connected to each data bus is connected to a corresponding data bus. In the first mode, the same number of memories as the number of data buses in a row of memories are connected to each data bus. Control means for controlling to be connected one by one is provided in an apparatus. The memories comprise a memory member for reading and writing the color data in response to a read and write signal, wherein the memory member is a matrix structure of M rows and N columns (where M and N are natural numbers of two or more, and M or N is equal to the desired number of colors), each of which has an address terminal, a read and write terminal, a chip select terminal, and a data output terminal. The control means includes: signal generation means for receiving and decoding decoded address data from the applied address data, and generating chip select signals to be provided to the respective memories by multiplexing the decoded signals and a mode signal applied thereto; It is connected to the data output terminal of the memory corresponding to the column 2 to the column N-1 in the memory member, respectively, and distributes data of the memories in response to the mode signal, the chip select signal, the read and write signals. And a data distribution means for storing the color data when at least three of the memories belonging to the first row in the memory member are empty.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, specific details will be set forth in order to provide a thorough understanding of the present invention. For those skilled in the art, the above description will be apparent and will be fully practiced without these details. In addition, well-known circuits and their functions are descriptive in order not to obscure the present invention.

Referring back to FIG. 1 for a more complete understanding of the present invention, since cyan, magenta, and yellow color data must be output from the memory 100 in order in the surface sequential method, first, the RAM 0, 3, 6, 9 will be emptied. Even if these RAMs are empty after all the cyan colors are output, in the conventional method, since the data buses of RAM 0, 3, 6, and 9 are connected to D [0: 7], the data of cyan can be stored in this empty RAM. Even if you can not save the data of M, Y. This is because the M and Y data are provided through buses D [8:15] and D [16:23], respectively. Therefore, it is the aspect of the present invention that the structure of the memory circuit is created so that cyan, magenta, and yellow color data constituting one pixel can be stored when there is an empty RAM memory. In the embodiment of the present invention for solving the problems of the prior art, the configuration of the memory circuit shown in FIG. 3 and the 2 (a), (b) of FIG. 2 to control the read and write operations of each memory. Two mode and address offsets are provided as shown.

Referring to FIG. 3, memory members 301-312 for reading and writing cyan, magenta and yellow color data in response to read and write signals are made of volatile memories such as RAM having a matrix structure of three rows and four columns. The volatile memories each have an address terminal ADD, a read and write terminal R / W, a chip select terminal / CS and a data output terminal D. Thus, the number of the memory members used in this embodiment is 12 RAM memories, each having a capacity of 2 megabytes. In addition, the RAM memory will be described as performing input / output in units of 8 bits.

The decoder circuit 300 receives and decodes the decoding address data ADD [22:21] from among the address data ADD [22: 0] to be applied, and is provided to the respective memories by multiplexing the decoded signals and the applied mode signal. Generates chip select signals / CS0-CS11. Here, the internal configuration of the decoder circuit 300 is shown in FIG. 4, which is composed of a 2: 4 decoder 400 and 2: 1 multiplexers M1-M12. The outputs of the decoder 400 of FIG. 4 are offset to 0M, 1M, 2M, and 3M, respectively, which correspond to the contents of FIG. 2 (b). The mode signal may be provided by a controller (not shown). In this embodiment, the mode signal is divided into 0th and 1st modes. The connection between the decoder 400 and the multiplexers 410; M1-M12 according to FIG. 4 satisfies the table state of FIG.

Data pass buffers 320-325 used for data distribution are respectively connected to the data output terminals D of memories corresponding to the second to third columns in the memory member, and the mode signal and the chip select signals CS0. One of CS11, distributing data of the memories in response to the read and write signals R / W. Here, each data pass buffer has the same structure, which is shown in FIG. Referring to FIG. 5, an ora gate 504 and an ora gate 505 having a negative input may receive the mode signal and the chip select signal, respectively. The buffers 500 and 501 connected to the output of the gates 504 and 505 with the out enable terminal / OE are respectively bidirectional tri-state buffers having an 8-bit input output. Here, if the mode signal is logic "low", buffer 500 is enabled, and if the mode signal is high, buffer 501 is enabled.

The memory structure configured as described above can be read and written by two mode signals. In addition, when RAMs 0, 3, and 6 of FIG. 3 are empty, a mode signal is provided high to store cyan, magenta, and yellow data. That is, in FIG. 2 (a), mode 1 is shown. When a user moves straight to the left by finding a position where an address offset is 0, RAM 0, 3, and 6 are designated. The next free RAM memory is RAM 9, 1, and 4, which will be easily understood if the number of the memory corresponding to the portion whose address offset is indicated by M is found. This read write operation of the memory is essentially achieved by the circuit configuration as shown in FIG.

Therefore, the memory circuit according to the present embodiment makes it possible to efficiently use the utilization of the memory in the color printer using the surface sequential method, and contributes to the speed of printing. For example, assuming that one page image of C, M, Y color data is stored in a memory member under mode 0, reading of data starts under mode 0 at the time of printing. At this time, since the read operation is performed from the C data, the RAMs 0, 3, and 6 storing the C data are emptied first. At this point, the controller provides the mode signal as 1 at the time between data reads in mode 0, with 8 bits of cyan data in RAM 0, 8 bits of magenta data in RAM 3, and 8 bits of yellow data in RAM 6. To be stored. In this case, the data are simultaneously stored in the RAMs 0, 3, and 6. Thus, the cyan data is stored in RAM 0, 9, 7, 5 in turn, the magenta data is stored in RAM 3, 1, 10, 8, and the yellow data is stored in RAM 6, 4, 2, 11, in turn. . By this operation, since image data to be printed next can be stored in an empty memory even during the printing operation, the overall memory use efficiency can be increased, thereby improving the printing speed.

As described above, the present invention has been illustrated according to the drawings and described in accordance with the embodiments, but the present invention is not limited thereto, and various changes and modifications can be made without departing from the basic definition of the present invention. Anyone with ordinary knowledge will be able to see clearly. For example, the principles of the present invention can be applied to the field of laser printing systems or image scanning.

Claims (6)

An image forming apparatus for printing preset first, second and third color data on a paper, comprising: a memory member for reading and writing the first, second and third color data in response to a read and write signal, wherein The memory member is made up of volatile memories having a matrix structure of M rows and N columns, where M and N are natural numbers of two or more, and M or N is equal to the desired number of colors, and the volatile memories are each address terminals. A lead and write terminal, a chip select terminal and a data output terminal; Signal generation means for receiving and decoding decoded address data from the applied address data, and generating chip select signals to be provided to the respective memories by multiplexing the decoded signals and the applied mode signal; Connected to data output terminals of some of the memories in the memory member, and including at least data distribution means for distributing data of the memories in response to the mode signal, the chip select signal, the read and write signals; And storing the first, second and third color data when at least three memories are empty during reading and outputting the memory. 2. The apparatus of claim 1, wherein said signal generating means comprises: a decoder for receiving and decoding said decoding address; And a multiplexer each connected to an output terminal of the decoder to provide one of the chip select signals, respectively. 3. The memory circuit of claim 2, wherein the decoding address is the remaining higher bits other than the address directly applied to the memory among the address data to be applied. A memory circuit of a color video printer; Data buses used as data input / output paths of cyan, magenta, and yellow color data, respectively; A predetermined number of memories arranged in a row direction are commonly connected to each data bus; In the first mode, a selected row of memories connected to each data bus is connected to a corresponding data bus. In the first mode, the same number of memories as the number of data buses in a row of memories are connected to each data bus. And a control means for controlling to be connected one by one. 5. The method of claim 4, wherein the control means generates chip select signals to be provided to the respective memories by receiving and decoding decoded address data among the applied address data, and multiplexing the decoded signals and the applied mode signal. Signaling means for performing; Memory distributing means for distributing data of said memories. A method of storing color data in a color video printer; Preparing data buses used as data input / output paths of cyan, magenta, and yellow color data, and a predetermined number of memories arranged in a row direction to each data bus; In the first mode, a selected row of memories connected to each data bus is connected to a corresponding data bus. In the first mode, the same number of memories as the number of data buses in a row of memories are connected to each data bus. And controlling the data to be connected one by one, storing the color data when at least three of the memories belonging to one row of the memories are empty.