JPH02108168A - Frame memory device - Google Patents

Abstract

PURPOSE:To correspond to images in various shapes by switching combinations of two-dimensional arrays of a frame memory, i.e. the number of bits in a main scanning direction and the number of bits in a subscanning direction. CONSTITUTION:The correspondence between address information outputted by a device which attains access and address information applied to memory assemblies 800 and 900 is switched. The order of access to memory elements in the memory assemblies 800 and 900 is varied according to the switching to change memory arrays. Namely, this is equivalent to the alternation of the constitution of addresses in the memory assemblies 800 and 900 when viewed from the side of the device which attains the access, the bit capacity of one row of memory in the main scanning direction and the bit capacity of one column of the memory in one column in the subscanning direction vary, so that the two-dimensional arrays of the memory change. Consequently, various images which differ in the longitudinal/lateral ratio of the two-dimensional array can be stored by using the memory assemblies 800 and 900 of the same constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame memory device used to store image information and the like, and particularly to changing the memory arrangement.

[Prior Art] For example, when attempting to perform various editing processes on an image read by an image scanner before printing, the information is input sequentially as time-series information, so all of the information must be The information is temporarily stored in memory, and then the memory in which the information is stored is accessed to perform editing processing. This type of memory is called frame memory.
Typically, a very large storage capacity is required, e.g.
When reading an A3 size image with a resolution of 16 pixels/mm, approximately 4 Mbytes are required even for a single color with two gradations, and a color image requires at least 12 Mbytes.

[Problem to be solved by the invention] This type of frame memory has a very large storage capacity;
It is extremely expensive. Therefore, it is desirable to effectively utilize this type of device for various purposes.

However, in conventional Frame As memory, the number of bits of row addresses and column addresses are fixed so that they match the vertical and horizontal dimensions of the maximum size of an image input by an image scanner, etc. Therefore, two-dimensional images larger than a predetermined size cannot be stored. Therefore, for example, even if an image has an area corresponding to the number of bits (capacity) smaller than the storage capacity of the frame memory, either the vertical or horizontal size is several times larger than the other. If it is large enough, the entire image cannot be stored because it exceeds the maximum dimension.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a frame memory device that can change the configuration of a two-dimensional array so as to adapt to differences in the aspect ratio of images to be handled.

[Means to solve the problem] In order to achieve the above object, in the present invention.

General-purpose bus means connected to a predetermined processing means and including an address bus and a data bus; mutually different addresses specified by a first set of address buses of arbitrary N bits and a second set of address buses of N bits, respectively; The memory device includes a plurality of memory units each having a large number of memory elements arranged in a plurality of memory units, and includes a third set of address buses for specifying a memory unit to be accessed. a first set of N-bit signals extracted from signals on an address bus of a device accessing the memory assembly and applied to a first set of address buses of the memory assembly; Address selection means; extracts a second set of signals of N bits other than the first set of signals from among the signals of the address bus of the device accessing the memory assembly, a second address selection means for extracting a third set of signals excluding the first and second sets of signals from among the signals of the address bus of the device accessing the memory assembly; third address selection means for applying to a third address bus of the memory assembly; and retaining and responsive to information applied to a data bus of the general purpose bus;

Said 1st. controlling the second and third address selection means;
Address recombination means is provided for switching the combination of allocation to each group of signals of the signal group of the address bus of the device accessing the memory assembly.

[Operation] According to the present invention, the information set in the address recombination means is switched via the general-purpose bus.

A device (e.g., a CPU) that accesses the memory assembly.

Since the combination of bits of the address information actually applied to the memory assembly can be rearranged to match the number of bits in the main scanning direction and the sub-scanning direction of the scanner, a two-dimensional array suitable for the image can be set.

The address generated by the accessing device is generally updated sequentially from a small value to a large value as it scans in the main scanning direction and sub-scanning direction, so the address information must be applied to the memory assembly as is. For example, each memory element within the memory assembly is accessed in a predetermined order. However, in the present invention, since the correspondence between the address information output by the accessing device and the address information actually applied to the memory assembly is rearranged, the order in which each memory element within the memory assembly is accessed is changed according to the rearrangement. is changed, and the memory array changes.

In other words, from the perspective of the accessing device, this is equivalent to changing the address configuration within the memory assembly, and the bit capacity of the memory for one line in the main scanning direction and one line in the sub-scanning direction are changed.
The bit capacity of the column memory changes, and the two-dimensional array of memory changes. As a result, various images having different vertical/horizontal ratios in a two-dimensional array can be stored using a memory assembly having the same configuration.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

[Embodiment] FIG. 1 shows the configuration of one type of image processing system that implements the present invention.

Referring to FIG. 1, the system includes an image scanner 104. Page printer 105. A printer controller 100 and a general-purpose computer 110 are provided. The image scanner 104 main-scans and sub-scans a document image positioned on its reading surface, and converts one image information into R.
(Red).

Each of G (green) and B (blue) is sequentially output as independent 8-bit time-series gradation information.

In this example, a laser printer is used as the page printer 105. Image scanner 104, printer controller 100, and page printer 105 are commonly connected to bus 101 of general-purpose computer 110.

The general-purpose computer 110 is a commercially available computer, and includes a central processing unit (CPU) 102. Storage device 103.
It is equipped with a keyboard 111 and a CRT 112. The central processing unit 102 has a general-purpose bus 101, which connects an image scanner 104 and a printer controller 10.
0 and page printer 105.

The printer controller 100 includes a task processor 10
8. Skyana Interface 120. It includes a frame memory 1062, an image processing section 107, and a printer interface 121. The raster processor 108 is a device that performs data format conversion, and in this embodiment, a CAD (Computer Aided Detailed Data)
vector format data and D handled by sign) systems, etc.
T P (Desk Top Publishing
) PDL (Page Descr) handled by the system
ipt Language) format data as raster,
That is, it has a function of converting into bitmap format image data at high speed. In this example, general-purpose computer 1
A raster processor 108 is used to convert various types of image information in vector format or PDL format created by 10 into raster.

Either the image data output from the image scanner 104 or the image data output from the raster processor 108 is input to the frame memory 106 via the scanner interface 120.

Roughly speaking, the frame memory 106 has a function of storing image data input from an interface 120 according to a control signal applied from the interface 120, and a function of storing image data input directly from the general-purpose computer 11O via the general-purpose bus 101. It has a function of storing image data and a function of outputting the image data stored in the memory in synchronization with a control signal applied from the image processing unit 107.

The image processing unit 107 performs input γ correction on the image data input from the frame memory 106.

Various conventionally known processes such as color correction, scaling (enlargement/reduction), filter processing 9, and darkening processing are performed.

Also to accommodate various formats of images.

Parameters for various processes can be set by a general-purpose computer 110 via a general-purpose bus 101.

The system shown in FIG. 1 has four operating modes that can be broadly classified. That is, in the first operation mode, the flow of image data is 104-120-106-40.
7-121-105, and the image read by the image scanner 104 is recorded by the page printer 105. In other words, the system operates as a copying machine. The processing content of the CPU of the general-purpose computer 110 in this case is
Please refer to Figure a.

In the second mode of operation, the image data flow is 10
3-102-101-108-120-106-107
-121-105. In other words.

The contents of an image information file in vector format or PDL format, which is stored in advance in storage device 103 of general-purpose computer 110, is recorded by page printer 105. In this case, the data is converted by the Rask processor 108 from vector format or PDL format to Rask format and then sent to the page printer LO5.The details of the processing of the general-purpose computer 110 in this case are shown in FIG. 2b. I want to be

In the third mode of operation, the image data flow is 1
03-102-101-106-107-121-10
It becomes 5. This mode is used when image data previously created in bitmap format exists on the general-purpose computer 110 and the image is to be recorded by the printer 105. The details of the processing performed by the general-purpose computer 110 in this case are shown in FIG. 2c.

In the fourth mode of operation, the image data flow is 1
04-120-106-101-102-103. That is, in this case, image information read by the image scanner 104 can be stored in the storage device 103 on the general-purpose computer 110. The contents of the processing of the general-purpose computer 110 in this case are shown in FIG. 2d, so the VA is referred to.

As described above, in the system shown in Figure 1, this single system converts images in various formats into image information in the formats required by various types of page printers, and outputs it. Therefore, it is extremely versatile and can be used for a variety of purposes.

Next, regarding the frame memory 10G in FIG.

I will explain in detail. The configuration of this frame memory is
As shown in the figure.

Referring to FIG. 3, this device includes a first interface 201. which is connected to a general-purpose bus 101 of a general-purpose computer. The second interface 202 is connected to a page printer. and an image scanner, and are connected to various external devices via these interfaces.

That is, the general-purpose computer 110 can access the frame memory via the general-purpose bus 101 and the interface 201, image data input from the image scanner 104 is input to the frame memory via the interface 203, and data is transferred from the frame memory to the page printer. Direct data output occurs via interface 202.

The signals applied to each interface will be briefly explained. In addition, symbols with overlines in the drawings mean that they are active when the signal is at a low level, but please note that the overlines are omitted in the illustrations in 1B 6 Signals. The signals applied to lines 220, 221 and 222 are
These are the 43rd synchronization issues output from the page printer, and they are as follows.

FGATE...Frame synchronization signal indicating the effective image period of sub-scanning LGATE...Line synchronization signal IPCLK indicating the effective image period of main scanning...Clock pulse signal lines 233, 234 output for each pixel , 235 and 236 are signals output from the scanner interface 120, and are as follows.

Address: Image write address information consisting of n+m bits Write bank: Image write bank specification information consisting of N bits WE: Image write strobe TOGGLE: Toggle access (two banks of memory The main body of the frame memory includes a mode determining section 300, a bank selecting section 400 . Address control unit 500° data control unit 600.
RAM control section 700 and two bank memory sections 800,
900 is equipped.

The configuration of the mode determining section 300 is shown in FIG. 4a.

Referring to FIG. 4a, this circuit includes two registers 301 connected to an internal data bus 210 (101).
, 302 and a logic circuit 303 for determining the mode. This circuit generates each mode signal according to the logic shown in Table 1 below according to the combination of states of various input signals, and outputs them to signal lines 304 to 308.

Table 1 However, the state of the signal indicated by -'' is irrelevant. In other words, the mode determining unit 300 selects five modes (BUS mode, HRD mode, HWR mode, MAC mode, and TOGGLE mode) according to the signal applied from the outside. ) and outputs a signal indicating that mode.The operation of each mode is as follows.

BUS: A general-purpose computer accesses the frame memory via the general-purpose bus 101.

HRD: Reads data in the frame memory serially at high speed in synchronization with an external control signal.

HWR: Writes image data randomly to the frame memory at high speed in synchronization with an external control signal.

MAC...The entire content of the frame memory is rewritten to a pre-specified value at high speed. The operation is terminated by the address control unit 5.
It is identified by the signal line 519 connected to 00.

TOGGLH: Performs serial toggle access to two bank memories 800 and 900 in the frame memory.

In this example, each of the bank memories (800, 900) is configured as shown in Figure 5a.

That is, each has a storage capacity of n0m bits, and R2O, B
The three plane memories are connected in common, that is, in parallel, to an n0m-bit address bus.

Referring to FIG. 5b, if different address areas are assigned to each memory plane for R, G, and B, the address space required to access the memory planes will increase according to the number of memory planes. When allocated to the same address in parallel, the address space becomes the same as the address space of one memory plane, regardless of the number of memory planes. In other words, when configured as shown in FIG. 5a, the number of address bus bits required for memory access is reduced.

Also in this example, the bank memories are connected in parallel to the general purpose bus 101, as shown in FIG. 5c, and each bank memory is located in the same address space when viewed from the general purpose bus 101. Of course, multiple bank memories are not accessed simultaneously, but access is made selectively to only one bank memory. This selection is controlled by bank selection section 400 shown in FIG.

A specific configuration of the bank selection section 400 is shown in FIG. 4b.

Referring to Figure 4b, this circuit:

Latch 403. Logic circuit 411. Data selector 409
．． 410. Digital comparators 405, 406, bank designation switches 401, 402, and gates 417, 418 are provided.

Bank designation switches 401 and 402, respectively.

It consists of a mechanical switch that outputs an N-bit numerical value. Note that these switches may be constructed of, for example, a nonvolatile memory whose data can be rewritten by a general-purpose computer.

Each input terminal of the data selectors 409 and 410 has
Three sets of different N-bit bank selection information are applied, and one of them is selectively output by a data selector. and bank selection information output from the data selector 409.

The N-bit value output from the bank designation switch 401 is compared by the comparator 405, and if the two match, the bank selection signal BSI is output. Similarly, the bank selection information output from the data selector 410 and the N-bit value output from the bank designation switch 402 are transmitted to the comparator 40.
6 compared.

If both match, bank selection signal BS2 is output.

One bank memory 80 is selected by bank selection signal BSI.
0 is selected, and the other bank memory 900 is selected by bank selection signal BS2.

Therefore, if the bank designation switches 401 and 402 are set to 0 and l, respectively, the signal lines 413,
When the bank selection information appearing in 414 is 0 and 1, bank memories 800 and 900 are accessible, respectively.

In this embodiment, one circuit board forming the frame memory W is provided with two bank memories, so if four circuit boards are prepared, for example, eight sets of bank memories can be provided. In other words, if you set the values of 0, 1° 2.3, 4, 5.6, and 7 to each bank designation switch, the bank memory corresponding to each bank designation switch will be assigned to different banks 0, 1, respectively. ,2,3,
Assigned to 4°5.6 and 7.

A detailed explanation will be given later, but when reading and writing image information continuously, the address bus value is cleared to O every time the address bus value overflows, and the bank selection information is cleared accordingly. Incremented. That is, as the scanning position progresses, access is sequentially executed starting from the bank memory with the smallest bank value.

Therefore, for example, if eight bank memories are prepared in which address spaces of m bits in the main scanning direction and n bits in the sub-scanning direction are allocated as two-dimensional arrays, the bank value allocation of each of the eight bank memories is set to 0. ,1,2,3,
4, 5.6 and 7, the two-dimensional memory arrangement of the entire frame memory is as shown in Figure 7b.

Therefore, when using this frame memory, consecutive numerical values are normally assigned to the bank designation switches in order from 0. Thereby, a plurality of bank memories can be used as one continuous frame memory.

Furthermore, by changing the setting of the bank designation switch when writing and reading image data, it becomes possible to edit images in bank area units. For example, the 0th. 1st. Second
．． Third. 4th. Fifth. Set the bank values (bank designation switch values) of the sixth and seventh bank memories to 0, 1, respectively.
2, 3, 4 degrees 5.6 and 7 degrees, write the original image as shown in FIG. Second. Third. 4th. Fifth. Set the bank values of the sixth and seventh bank memories to 0.1, 2, and 0.1, respectively.
5, 6, 7, 2, and 3, and then sequentially read out the data in the frame memory, the read out images will be in a different order than the original, that is, in the moving process, as shown in Figure 6b. Be what you are. Similarly, after writing an image with the same bank value as the former, the O9 1st. Second. Third. 4th゜5th. The bank values of the sixth and seventh bank memories are
If the image data is read after changing to 0, 1, 2, 8, 9, 5, 6, and 7, the memory of bank values 8 and 9 will not be accessed, so the read image will be the 6th c. As shown in the figure, it is partially masked. Also, after writing the same image with the same bank value as the former, switch the bank value to select only the third bank memory, write another image, return the bank value to the original, and read the image. , the read image is a partial composite of the first written image and the later written image. by this.

You can combine images.

In other words, according to this embodiment, editing processing such as image movement, masking, and composition can be performed using the size of each bank area of the frame memory.

This process can be performed in a short time because it only requires switching the bank value.

When a general-purpose computer accesses the frame memory from general-purpose bus 101, the access is performed after selecting the bank to be written by writing N-bit bank selection information to latch 403. When multiple boards are connected to the general-purpose bus, the same value is written to the latch 403 of each board at the same time.

The logic circuit 411 identifies the current operation mode by referring to the mode signal, and selects the data selector 40 according to the result.
9,410 to switch the selected bank selection information. That is, BUS mode, HRD mode, HWR mode and TO
In the GGLH mode, the signal lines 404,
235, 234 and 234 information is selected and signal line 4
13 and 414.

Furthermore, since the mode signal MACM is applied to the input terminals of gates 417 and 418, in the MAC mode,
Regardless of the outputs of comparators 405 and 406, signal BSI
, BS2 becomes active and all bank memories can be accessed simultaneously.

In addition, in this embodiment, since the signal line through which bank selection information is passed is N bits, 2<N> bank memories can be connected to 1
Can be connected in parallel to two general-purpose buses. In other words,
As total memory capacity.

A frame memory of up to 2 to the power of (N + n + m) x 3 bytes can be constructed.

When arranging 2 to the power of (N+n+m) x 3 bytes of memory in a continuous address space, normally N+n+m+
A 2-bit address line is required.

However, in this embodiment, as shown in Figure 7a.

Since each of the N banks is connected in parallel to the same address space, and the three memory planes of each bank are connected in parallel to the same address space as described above, it takes an address to access this frame memory. The number of bits of the signal line required for the bus is only n+m, that is, the number of bits of the address bus required to access the frame memory is smaller than usual by N+2 bits. As a result, even if a large-capacity frame memory is required, image processing can be controlled by a computer using a general-purpose bus with a small number of bits.

The specific configuration of the address control unit 500 in FIG.
As shown in the figure. Referring to FIG. 4C, this circuit includes three-state buffers 501 and 502, a data selector 5
04,505. Read address counter 506. A bank counter 507 and a logic circuit 518 are provided.

Three-state buffer 501 receives mode signal BUSM
is active, that is, in BUS mode, general-purpose bus 1
n+m bit address signal line 21 connected to 01
A signal of 1 is output onto the signal line 503. The other three-state buffer 502 outputs the signal of the n+m pit address signal line 233 connected to the scanner interface onto the signal line 503 when the mode signal HWRM is active, that is, in the HWR mode.

The read address counter 506 has a concrete configuration shown in FIG. 4d, and includes a 1 m-bit endless main scanning counter 507 and an n-bit endless sub-scanning counter 508.

The value held by the latch 509 is applied to the preset input terminal of the main scanning counter 507 as an offset value. The main scanning counter 507 indicates that the synchronization signal LGATE is H (
(indicating outside the effective scanning range in the main scanning direction), the offset value is loaded (preset), and when LGATE is switched to L, counting of clock pulses JPCLK is started.

The value held by the latch 511 is applied to the preset input terminal of the sub-scanning counter 508 as an offset value. The sub-scanning counter 508 detects that the synchronization signal FGATE is H (
When the offset value is loaded (preset) L and FGATE is switched to L, counting of the synchronization signal FGATE is started (see FIG. 8a).

In addition, in the MAC mode, the signals FGATE and LGA
Regardless of the state of TE, the main scanning counter 507
At the rising edge of CLK (see FIG. 8b), the sub-scanning counter 508 performs a counting operation using the carry output 516 of 507 (see FIG. 8c).

Therefore, in this embodiment, address information (m+n bits) indicating the scanning position is automatically generated within the read address counter 506. Therefore, there is no need for an external device that inputs and outputs one image data to specify a memory address.

Furthermore, by setting the offset values held by latches 509 and 511 to values other than 0, it is possible to add an offset between the scanning position of the synchronization signal applied from the outside and the position at which the frame memory is accessed. By using this, editing processing such as image movement and masking becomes possible, as explained in the first section.

For example, if a copy operation is performed with the main scanning offset value and sub-scanning offset value set to O both when writing to the frame memory and when writing successively, an image as shown in FIG. 9a is obtained. In addition, when copying the same image by setting the main scanning offset value to a and the sub-scanning offset value to b only when reading the image, as shown in FIG. 9b,
In contrast to the former, the recorded image is shifted by 2.89c pixels) in the negative direction of the main scanning direction and by 2.sup.b (lines) in the negative direction of the sub-scanning direction. Similarly, only when reading images.

When copying the same image as the former with the main scanning offset value set to m-c and the sub-scanning offset value set to nd, as shown in Fig. 9c, the original image will be moved in the main scanning direction. 2 C pixels in the positive direction, 2 in the positive direction of the sub-scanning direction
The recorded image is shifted by the d-th power line.

Referring again to Figure 4c. Address information used to access one bank memory 800 is output to signal line 516, and address information used to access the other bank memory 900 is output to signal line 517. The former address information is obtained by selecting either the information on the signal line 503 or the information on the signal line 515 by the data selector 504, and the latter address information is obtained by selecting either the information on the signal line 503 or the information on the signal line 515. is selected by the data selector 505. These data selectors 504 and 505 are determined according to the combination of states of the mode signal and bank signal. The correspondence between the state of each signal and the information appearing on the signal lines 516 and 517 is shown in Table 2 below.

Table 2 Sub-scanning counter 50 in read address counter 506
The carry output from 8 appears on signal line 519. This signal is counted by puncture counter 507. Bank counter 507 receives synchronization signal FGATE.
When FGATE is H (when the scanning position is outside the sub-scanning effective image area), it is in a reset state, and when FGATE becomes L, signal line 5
Count 19 signals. The carry output of the sub-scanning counter appearing on the signal line 519 means an overflow of the n+m bit address, and therefore indicates that access to the memory corresponding to one bank has been completed. In other words, 1
When memory access of all addresses in one bank memory is completed, a carry output is generated and the puncture counter 50
7 counts up. The value output by the puncture counter 507 is used to select each bank memory in the HRD mode. Therefore, the value is automatically updated to 0, 1, 2, 3, 4 each time access to each bank is completed, so in HRD mode, a special bank selection signal is applied from the outside and it is sequentially updated. Memory access across banks can be performed continuously without performing switching processing.

The configuration of the data control section 600 in FIG. 3 is shown in FIG. 4e.

- Referring to FIG. 4e, this circuit consists of three sets of buffer circuits 610, 630 and 650. The configuration of these buffer circuits 610, 630 and 650 is as follows:
Figure 4f, respectively.

This is shown in Figures 4g and 4h.

First, the buffer circuit 610 will be explained with reference to FIG. 4f. This circuit includes registers 611, 612, 613 for holding designated colors for each of R, G, and B, six buffers 615 to 620, and a logic circuit 614. Each of the buffers 615 to 620 is a bidirectional three-state buffer, and each includes two sets of input/output data terminals, a gate terminal G, and a direction control terminal DIR. A signal VRITH is commonly applied to each terminal DIR, and an output signal of the logic circuit 614 is applied to each gate terminal.

The logic circuit 614 receives the color signals R5, GS, and BS output from the registers 611, 612, and 613, and the signal BUSM.
, BSI, BS2 and AS, the gate of each buffer is controlled by the logic shown in Table 3 below.

Table 3 Also, the direction of the signal of each buffer that is turned on is controlled by the control signal RITE; if WRITE is O, data is allowed to pass in the direction from the bus 210 to each bank memory, and if WRITE is 1, each Data is allowed to pass in the direction from the bank memory to the bus 210.

In addition to the combinations shown in Table 3 above, color signals R8, G
Set all S and BS to 0, and set the control signal WRITE to 0.
, if BSl is O and BS2 is 1, then 3
When three buffers (615, 616, 617) are turned on at the same time and BSI is l and BS2 is 0, the other three buffers (615, 616, 617)
The three buffers (618, 619, 620) are turned on at the same time. Therefore, if this mode is set, a general-purpose computer connected to the general-purpose bus can simultaneously write data into three sets of R, G, and B memories. In this case, the writing speed is three times faster than when each memory is accessed in order.

Next, the buffer circuit 630 will be explained with reference to FIG. 4g. This circuit includes six buffers 632°633.6
34, 636, 637 and 638, logic circuit 63
1.635 and latches 642-644. These buffers 632, 633, 634, 636
, 637, 638, only the direction from each bank memory to the interface 202 is permitted. Three numbers 632 to 634 are logic circuits 63
1 and the remaining buffer 636
637 and 638 are on/off controlled by a logic circuit 635. Latches 642-644 are connected to the signal I PC
The signals output from each buffer are latched in synchronization with the falling edge of LK.

In other words, the image data output from the bank memory 800 passes through the buffers 632 to 634 and is sent to the bank memory 900.
The image data output from 0 is sent to buffers 636 to 638.
is output to the page printer 105 connected to the interface 202.

Next, the buffer circuit 650 will be explained with reference to FIG. 4h. This circuit includes six buffers 652°653.6
54,656,657 and 658. Logic circuits 651 and 655° data selectors 662, 663, 664. and background color registers 665, 666 and 667. These buffers 652, 653, 654, 6
The direction of data passing through 56, 657 and 658 is only allowed from the interface 203 to each bank memory. 3 buffers 652, 653 and 65
4 is on/off controlled by logic circuit 651, and the remaining buffers 656, 657 and 658 are controlled by logic circuit 651.
On/off control is performed by 55.

When the signal MACM is 1, that is, when it is not in MAC mode,
The data selectors 662 to 664 control the signal lines 230 to 230.
232 data are applied to each buffer and the signal MACM
When is 0, that is, in the MAC mode, the background color data output from the background color registers 665 to 667 is applied to each buffer.

That is, in the MAC mode, the data written to the memory can be fixed to any background color, so the same background color can be written to all addresses in the bank memory. What to write in that case.

Runs fast.

Therefore, for example, when an image read by an image scanner is printed as a hard copy using a page printer, the color of the background portion on the hard copy can be changed by executing the MAC mode beforehand.

This kind of background color change can also be done by a general-purpose computer or computer accessing and editing bank memory, but in that case it takes a very long time to execute the process, so this is not possible. In the embodiment, it is preferable to execute the MAC mode because processing can be performed in a shorter time.

Please refer to Table 4 below, which shows the signal lines connected to each bank memory in each signal state according to the operation of the data control unit 600.

Table 4 *: Connected to plane 0 of R5, GS, BS The configuration of the RAM control unit 700 in FIG. 3 is shown in FIGS. 41 and 4j. The circuit shown in FIG. 80
The circuit shown in FIG. 4j is the circuit that controls the other bank memory 900.

First, referring to FIG. 41, each signal line 710 to 717
The following signals appear respectively.

710: n-bit R for DRAM in 800
AS/CAS address 711: R plane (i') DRAM in 800 RAS 712: 800 (7) R plane D
CAS713 for RAM: G within 800 RAS714 for DRAM of plane: G within 800
CAS715 for P/N DRAML:
171B within 800 L/-N DRAMi: RA for
S716: Read/write signal for B plane DRAM in 800 CAS717: Read/write signal for DRAM in 800 (reading is H9 writing is L) In addition, each of the signal lines 760 to 768 shown in FIG. 4j has the following signals. appears.

760: n-bit R for DRAM in 900
RAM for R-plane DRAM in AS/CAS address 761:900
S762: CAS for R-plane DRAM in 900: CAS763: G-plane DRA in 900 vs. RAS764: G-plane DRA in 900
CAS765 for M: RAS766 for B-plane DRAM in 900: CAS767 for B-plane DRAM in 900: Read/write signal for DRA in 900 (reading is H2 writing is L) Each signal line 711 to 717 and 761 The states of the signals appearing in 767 change as shown in Table 5 below, depending on various control signals and modes. In addition.

The meaning of each symbol shown in Table 5 is as follows.

A Near active state NA: Inactive state *1: Only the 0 plane signals of R5, GS, and BS are active *2: Active state when IIRITE is 0 *
3: Active state at the rise of IPCL*
4: Active state at falling edge of IIH The signal line 516 on the input side of the address selector 702 shown in FIG. 41 and the signal line 517 on the input side of the address selector 752 shown in FIG. 4j each contain n+m bits of address information. applied. Address selector 702 outputs n bits out of n+m bits to signal line 720, outputs the other n bits to signal line 721, and outputs the remaining n bits to signal line 720.
Output to 22. Similarly, the address selector 752 is
Of the n+m bits, n bits are output to the signal line 770, the other n bits are output to the signal line 771, and the remaining n bits are output to the signal line 771.
The bit is output to signal line 772.

A specific configuration of the address selector 702 is shown in the fourth figure. Fourth, referring to the figure, in this example n+m is 24 bits, 11 of which are connected to signal line 720.
It is output as an AS signal, and the other 11 bits are connected to the signal line 72.
1 as the RAS signal, and the remaining 2 bits are output to the signal line 722. Also, in this example, latch 791
By switching the data held in the data selectors 792 and 794, the information output to the signal line 720 and the information output to the signal line 722 can be switched to three types each.

Referring again to FIG. 41, in the signal line 710 on the output side of the logic circuit 701, the n-bit CAS address output to the signal line 720 and the n-bit RAS address output to the signal line 721 are different from each other. Output at the right time. Similarly, in the signal line 760 on the output side of the logic circuit 750 shown in FIG. 4j, the n-bit CAS address output to the signal line 770 and the n-bit RAS address output to the signal line 771 are different. Output at the right time. Please refer to FIG. 9d for an outline of these timings.

The configuration of the bank memory 800 in FIG. 3 is shown in FIG. 4Q.
Referring to FIG. 4Q, each of the R, G, and B plane memories is composed of memory arrays 810, 820, and 830, respectively.

Each memory array is composed of a large number of integrated circuits, and has a total storage capacity of 2 to the nth power x 2 to the m power. The row address and column address, which are commonly applied to all integrated circuits, each have n bits, and are applied to each terminal via an n-bit signal line 710. In addition, the signal line 71
8 is 2 to the fifth power (b=m−n), and each signal line is used to select each integrated circuit chip.

Therefore, each plane memory has 2 n dots x 2
This is equivalent to having 2 to the b power of memory blocks in a two-dimensional array of n-th power lines. A signal line 718 selects which memory block to access.

Referring again to the fourth address selector shown in the figure, in this embodiment, by switching the data held in the latch 791, the signal line 72o.

The combination of addresses output to 722 can be changed. That is, in the first combination, 24-bit internal addresses Δ14 to A24 are selected as CAS addresses, and A12 and A13 are selected as chip select addresses, and in the second combination, AI2 to A22 are selected as CAS addresses. A23 and A24 are selected as chip select addresses, and in the third combination, AI
3 to A23 are selected as CAS addresses, and A12 and A24 are selected as chip select addresses.

That is, in the first combination, n fi! of 2! Four memory blocks of X 2 to the 8th power bits are arranged consecutively in the main scanning direction, and as shown in FIG. The number of bits is four times the number of bits, and a horizontally long two-dimensional array memory plane is configured.

In the second combination, four memory blocks are arranged consecutively in the sub-scanning direction, and as shown in FIG. 10b, the number of bits in the sub-scanning direction is equal to the number of bits in the main scanning direction.
This doubles to form a vertically long two-dimensional memory plane. Furthermore, in the third combination, two memory blocks are arranged consecutively in the main scanning direction and two in the sub-scanning direction, and the number of bits in the main scanning direction and the sub-scanning direction are each 2 to the n power. ×2, resulting in a square two-dimensional array as shown in Figure 10c.

Therefore, in this embodiment, the two-dimensional arrangement of the frame memory can be changed according to the shape of the image to be processed. In general, even if the amount of information in the original image is within the storage capacity of the frame memory, if the two-dimensional arrangement of the frame memory and the shape of the original image do not match, the image at the edge in the main scanning direction or sub-scanning direction will be In order to process images of various shapes, the storage capacity of the frame memory must have sufficient margin for the amount of information of the image to be processed. However, in this embodiment, since the two-dimensional arrangement of the frame memory can be changed, as long as the storage capacity is equivalent to that of the original image, the image can be read into the frame memory and processed without causing any loss of information.

[Effects] As described above, according to the present invention, it is possible to switch the combination of the two-dimensional arrangement of the frame memory, that is, the number of bits in the main scanning direction and the number of bits in the sub-scanning direction. On the other hand, it is possible to handle images of various shapes without providing a particularly large amount of storage capacity.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of one type of image processing system implementing the present invention.6 FIG. 2a, FIG. 2b,
FIGS. 2c and 2d are flowcharts showing the operation of the general-purpose computer of FIG. FIG. 3 is a block diagram showing a specific configuration of frame 11 memory 106 shown in FIG. Figures 4a, 4b, 4c, 4d, 4e,
Figure 4f, Figure 4g, Figure 4h, Figure 41, Figure 4j,
Figure 4 and Figure 4Q are block diagrams showing specific nitric acid of each component shown in Figure 3. FIG. 5a shows R, G in one bank memory. FIG. 5B is a block diagram showing the connection of the plane memories of B, and a map showing the arrangement of addresses of each plane memory.
FIG. 5C is a block diagram showing the connection state of a plurality of bank memories. Figures 6a, 6b, 6c and 6d. FIG. 7 is a plan view of a recorded image showing the result of certain processing on image M by changing bank assignment. FIGS. 7a and 7b are maps showing address assignments for each bank memory. FIGS. 8a, 8b, and 8c are time charts showing examples of the operation timing of the counter 506. FIG. FIGS. 9a, 9b, and 9c are plan views of recorded images showing the results of image editing processing by changing offset values. FIG. 9d is a time chart showing the operation of the RAM control section 700. FIG. 10a, FIG. 1ob, and FIG. 10c are plan views showing a two-dimensional array in each state of the plane memory realized by switching the address selector 702. 100: Printer controller 101: General-purpose bus (general-purpose bus means) 102: Central processing unit 103: Storage device 104:
Image scanner 105: Page printer 106: Frame memory 108: Task processor 110: General-purpose computer 201, 202, 203: Interface 300:
Mode determination section 400: Bank selection section 401.402
:Bank specification switch 403:Latch 405.406:Digital comparator 600:Data control section 700:RAM control section

Claims (1)

[Claims] General-purpose bus means connected to a predetermined processing means and including an address bus and a data bus; a first set of address buses of arbitrary N bits and a second set of address buses of N bits, respectively; A memory assembly including a plurality of memory units each having a plurality of memory elements located at specified different addresses, and comprising a third set of address buses for specifying a memory unit to be accessed; a device for accessing the memory assembly; a first address selection means for extracting a first set of N-bit signals from the signals of the address bus of the memory assembly and applying the extracted signal to the first set of address buses of the memory assembly; a device for accessing the memory assembly; a second address selection means for extracting a second set of N-bit signals other than the first set of signals from among the signals of the address bus of the memory assembly and applying the extracted signals to the second address bus of the memory assembly; A third set of signals excluding the first and second sets of signals of the address bus of the device accessing the memory assembly.
third address selection means for extracting and applying a set of signals to a third address bus of said memory assembly; and retaining information applied to a data bus of said general purpose bus;
In accordance with the information, controlling the first, second and third address selection means to switch the combination of allocation to each set of signals of the address bus signal group of the device accessing the memory assembly; A frame memory device comprising: address recombination means;