JPS63244484A - Data transfer system - Google Patents

Abstract

PURPOSE:To attain high speed sequential access by using the page mode of a dynamic RAM. CONSTITUTION:A data is read from the dynamic RAM in the page mode and written in a high speed memory 13. Then the data read from the high speed memory 13 is shifted by a shift circuit 16 so as to be coincident with a bit location of a destination side in response to the mask values. Then the data is written continuously in the RAM, and a first and end processing is subjected to read modefy write and the intermediate part is written in the unit of words in the page mode. Thus, high speed transfer is attained without expanding the bus width and since the system is suitable for large scale circuit integration, the hardware is miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a data transfer method suitable for use in transferring image data.

(Prior Art) When handling high-resolution image data, the amount of data becomes enormous, and hardware that enables high-speed data transfer is required. Data transfer speed is largely determined by memory access time and data path width. An example of operation when image data is transferred to an arbitrary bit position will be briefly explained using FIG. 2. That is, first ■
Read the data shown in and write data a. Next, read the data in ■ and combine it with the remaining part of ■ to create data b.

It required processing such as writing C, reading ■ and writing d and a in the same manner. In the figure, a dotted line indicates the position of a word/underly.

(Problem to be solved by the invention) According to the above conventional example, when WRITE of source data and destination data is used, the third
As shown in the timing chart shown in fig.

It is necessary to update the address every time, and therefore, when transferring sequential large-capacity data such as images, there is a speed disadvantage that cannot be ignored.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a data transfer system that performs sequential access at high speed by using the target mode of a dynamic RAM.

[Structure of the Invention] (Means for Solving the Problems) The present invention uses the page mode of the dynamic RAM to transfer sequential block data in a dynamic RAM from a source to a destination location. The structure is such that high-speed data transfer is achieved by successively reading source data into a high-speed memory and then writing the data successively to a destination stain/address position. In addition, by having the above functions, the time required for 91 block transfers is shortened,
Furthermore, by repeating this block transfer, multidimensionally arranged data can be transferred.

(Operation) In the above configuration, data is first read from the dynamic RAM in the υ page mode and written to the high speed memory.

Then, the data read out through this high-speed memory is selected according to the mask value and shifted by a shift circuit so that it matches the bit position on the testing side. The data is then continuously written into the dynamic RAM.

Perform read modify write once at the beginning and once at the end,
Middle part k Write in word units in page mode.

This enables high-speed transfer without expanding the bus width, making it suitable for LSI implementation and helping to reduce costs.

(Example) Examples of the present invention will be described in detail below.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 11 and 12 are buffers (input/output cells).

Buffers 11.12 have the function of separating the external data bus and internal delta bus.

13 is a register file that holds source data. 14 is a register. As will be described later, the data read from the destination data is stored in the register 14 before data is written to the destination address position t when a read/modify/write is performed.

15 is a selector. The selector 15 receives the output of the register file 13 as an input, and selects data to be input to the barrel shifter 16 according to the output of a mask data generation circuit 18, which will be described later. The barrel shifter 16 can rotate data by an arbitrary length.

17 is a selector. The output of the barrel shifter 16 and the output of the register 14 are supplied to the selector 17 as inputs, and depending on the mask value output from the mask data generation circuit 18, it selects and outputs one of the two. That is, source and destination data are selected for read mode 7 eye write. The mask data generation circuit 18 specifies the bit position of valid data. Reference numeral 19 denotes an address generation circuit that specifies the address t of transfer data in the dynamic RAM.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. When transferring two-dimensional data such as an image, the data is usually scanned in the horizontal direction, and transferred in the vertical direction repeatedly in the horizontal direction. In this case, since the addresses are continuous in the horizontal direction, the page mode of the dynamic RAM as shown in FIG. 46-1 can be used. In page mode, the cycle time can be shortened because it is only necessary to input the address on the RAS side once. The operation of the circuit shown in FIG. 1 will be explained by exemplifying the case where the data shown in FIG. 2 is transferred in page mode.

First, data is read from the data bus connected to dynamic RAM K in υ page mode.

The data shown in FIG. 2 pass through the data buffer 12' and are stored in the -register file 13 one after another. When reading data for one scan on the source side is completed, the data is written in the memory on the destination side in page mode. This means that the selector 15 selects the data to be written from the data read out from the register file 13 according to the simulator value. In FIG. Shift the bit position to match the destination bit position. Selector 1
The data passed through 7 is outputted through the output buffer 11 and written to the dynamic RAM.

However, when writing the data of a, the data on the left side of a is also written, so it is necessary to perform read-modify-write. Therefore, when writing data continuously, it is necessary to perform read-modify-write once at the beginning and once at the end, and write the intermediate portion in word units in page mode. When performing read-modify-write, the destination data is read and held in the register 14 before writing to the destination address location.

When writing data to the destination address position, a pattern indicating the bit position to be written is created from the mask generation circuit 18, and the bit to be written is determined according to the mask pattern.

The output of the register 14 is selected by the selector 17 for bits that do not write the output of the barrel shifter 16 . Also,
In order to perform these operations, the register file 13 has 1
It needs to have a larger capacity than the scanned data and have a sufficiently fast access time.

[Effects of the Invention] As explained above, in the conventional method of performing read and write operations alternately, the access time of the dynamic RAM was a bottleneck, and there was no way to increase the transportation speed other than by widening the path width. When transferring data in a rectangular area such as image data, 1. By using the method of the present invention, approximately 2.
You can get double the transfer speed. Furthermore, the method of the present invention is suitable for LSI integration and can reduce the bus width to half that of the conventional method, thereby making it possible to downsize the hardware and helping to reduce costs.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, and Figures 2 to 4 are diagrams cited to explain the operation of the embodiment of the present invention. An example of the timing when performing the operation and an example of the timing of the target mode are shown. 11.12... Buffer, 13... Register file, 14... Register % 15.17... Selector, 16... Para shifter, 18... Mask data generation time -10-

Claims (4)

[Claims] (1) When transferring sequential block data stored in the dynamic RAM, the source data is read out continuously by using page mode,
This data transfer method is characterized by continuously writing the data to the destination location. (2) Continuously read the source data stored in the dynamic RAM in page mode, select the register file in which it is stored and the data read through this register file according to the mask value, and select the destination 2. The data transfer method according to claim 1, further comprising a shift circuit for matching the bit position on the side, and a write control circuit for continuously writing the output of the shift circuit into a dynamic RAM. (3) The write control circuit reads the destination data before writing data to the destination address position, and selects a register in which the obtained data is stored and either the register output or the shift circuit output according to the mask pattern. 3. The data transfer method according to claim 2, further comprising a selector for selectively outputting one of the data. (4) The data transfer method according to claim 1, wherein multidimensional array data is transferred by repeatedly performing the block transfer.