JPS636644A - Frame buffer memory - Google Patents

Abstract

PURPOSE:To rewrite the data on an optional specific picture element in a single word at a high speed by adding a write command register to a frame buffer in addition to a write data register. CONSTITUTION:The write address received from a write data generating circuit is stored in an address register 6 and a write address Aw is supplied to an IC memory 1. While the write data are successively sent at a high speed via a data bus 9 and fetched by a write data shift register 3 to be sent to each corresponding buffer register 2. Thus the write data is given to each IC memory 1. The write command to be issued to the IC memories are fetched successively to a shift register 5 and a write command is delivered individually to the IC memory. Thus it is possible to rewrite optionally the data within a single word.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame buffer memory for a CRT display Llf, and particularly to a frame buffer memory (hereinafter also simply referred to as a frame buffer) with an improved access method.

[Conventional technology]

Fig. 3 is a block diagram showing a conventional example of a Fi7 frame buffer readout circuit, Fig. 3A is an explanatory diagram for explaining the relationship between a CRT screen and display data, and Fig. 4 is a block diagram showing a conventional example of a frame buffer writing circuit. It is a diagram.

In Figure 3, 1 (la to lh) is an IC (semiconductor)
The IC memory 1a is a CRT shown in FIG. 3A.
For example, pixels po and po' on the screen 12.

Stores the display data of PO “...” and saves it to IC memo I.
J1b is the same pixel PI, PI', PI"...
. . . Similarly, memory IC~1h stores data for pixels P2゜P2', P2'...~P7. P7'
, P7', . . . n data are stored respectively. Note that the reference numeral 11 in FIG. 3 indicates a shift register.

That is, the IC memory 1 is conventionally used as a frame buffer of a CRT display device. but,
The time it takes to read IC memory 1 is 1 on the CRT monitor.
Since it is long compared to the display time of the dots, multiple IC memories 1 were allocated in the raster direction (usually horizontal direction) of the screen, and those IC memories 1 were read out in parallel in synchronization with the scanning of the electron beam. The data is converted into high-speed serial data by a shift register 11 and sent to a CRT monitor.

In this way, since high-speed serial data for CRT display is required, multiple IC memories (with frame buffer):
In the example shown in FIG. 3, a configuration is adopted in which 8 pixels) are read out in parallel, and on the CRT display screen 12 shown in FIG. 3A, data for eight consecutive pixels in the horizontal direction are read out at the same time. If data for eight pixels read simultaneously is called a word, the frame buffer requires reading in units of words. For this reason, if data is written to the frame buffer in units of 7-modes, the hardware becomes simpler and the time required to write data per pixel is shorter. However, in order to send write data for one word to the 7-frame buffer at the same time, K requires a large number of data lines. Register 3 (3a-3m)
A method is exclusively adopted in which a buffer register 2 (2a to 2n) and the like are provided, and one word of write data is serially written.

FIG. 5 is a waveform diagram showing the write timing of FIG. 4. In this example, the write address sent via the address bus 8 from the write data generation circuit (not shown) is
It is stored in the address register 6 at timing T1 in FIG. 5 and supplied to the IC memories 1a to 1n. Further, a write command from the write data generation circuit is also stored in the write command storage register 7 at timing T1 and supplied to the IC memories 11 to 1n. On the other hand, the write data from the write data generation circuit is transmitted via the data bus 9 to po data, Pi data, and P2 data.

・・・・・・It is sent in order at high speed. This data is taken in by the shift registers 3a to 3m, and T1
Each corresponding buffer register 2 (2a
2n), and write data is given to each IC memory 1a to 1n. And P in Meko Recycle 1
Data O to P7 are simultaneously written to the IC memories 1a to 1n.

[Problem that the invention seeks to solve]

As described above, in the conventional 7-frame buffer access method, by providing a shift register and a buffer register for write data, it is possible to write data at high speed without using a large number of data lines. be. However, since writing is performed in units of one word, there is a problem in that only specific pixel data within one word cannot be changed.

Therefore, it is an object of the present invention to provide a frame buffer memory that can quickly exchange data of a specific pixel within one word without using a large number of data lines.

[Means for solving problems]

A command writing means for individually giving a data writing command to each IC memory is provided so that pixel data at a predetermined position can be changed for each word.

[Effect]

By newly providing the frame buffer with a command writing means consisting of a shift register for writing commands and a buffer register in addition to a shift register for writing data and a buffer register, one It is possible to rewrite data of a specific pixel within a word at high speed.

[Embodiments of the invention]

FIG. 1 is a block diagram showing an embodiment of the frame buffer memory according to the present invention, particularly its write circuit, and FIG. 21 is a time chart for explaining its operation. In Figure 1, 3 (3a to 3m) is a shift register for write data, 2 (2a to 2n) is a buffer register for write data, 1 (la to In) is an IC memory, 6 is an address register, and Aw is a write address. , 5 (5a to 5m) are shift registers for write commands, and 4 (4 & to 4n) are buffer registers for fill commands.

With this configuration, the write data generation circuit (not shown)
The write address as shown in Figure 2 (a) sent from
It is stored in the address register 6 at the timing of T1 in FIG. 2, and the write address Aw is IC memo') 1 (1a
~In). Also, the write data is data for po via data bus 9.

Data for Pl, data for P2, etc., and Figure 2 (
They are sent in sequence at high speed as shown in b). This data is sequentially taken in by the write data shift registers 3 (3a to 3m) and transferred to the corresponding buffer registers 2 (2a to 2n) at timing T1, and is transferred to each IC memory IJI.
Write data is given to (la to in). - way, I
Write commands to the C memory are sent from a write data generation circuit (not shown) to a write command for ICC memory l, a write command for IC memo 1.11 b, a write command for IC memo IJ l c, and so on. As shown in figure (c)! 1
− is sent at high speed. This write command is sequentially taken into the write command shift register 5 (51 to 5m), and T1
Write command buffer register 4 (1~
4n) KE is sent and a write command is output to each IC memory individually. In the example in Figure 2, IC memo + J1d, Ig, l
Since only the write command for h is "1", the data write in memory cycle 1 is IC memo + Jld.

Executed only for 1g and lh.

In this way, according to the present invention, data rewriting of only any specific pixel within one word can be executed at high speed.

〔Effect of the invention〕

According to this invention, the frame buffer is newly provided with a shift register and a buffer register for writing commands in addition to a shift register and a buffer register for data to be filled in, so that a large amount of data can be stored. ! This provides an advantage in that data of any specific pixel within one word can be replaced at high speed without using.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining its operation, FIG. 3 is a block diagram showing a conventional example of a frame buffer readout circuit, and FIG.
The figure is an explanatory diagram for explaining the relationship between the first surface of the CRTlffl and display data, Figure 4 is a block diagram showing a conventional example of a frame buffer writing circuit, and Figure 5 is a time diagram for explaining the operation of Figure 4. It is a chart. Code explanation 1 (1a to 1n)...IC memory, 2 (2a to 2n)
, 4(41~4n)...ノ(Zuffa register, 3(3
3~3m), 5 (5&~5m), 11...
Shift register, 6...Address register, 7...
Write command storage register, 8... Address no.
9...Data bus, 10...Write command line, 12.
・・CRT display screen. Agent Patent Attorney Akio Namimoto Attorney Kiyoshi Matsuzaki Figure 3 Figure 3A

Claims (1)

[Scope of Claims] Writing for serially writing and reading data into each semiconductor memory that stores display data in units of words consisting of a predetermined number of pixels connected in the horizontal direction of a CRT screen corresponding to each pixel; A frame buffer memory provided with a readout circuit is characterized in that a command writing means is provided for individually giving a data write command to each of the semiconductor memories, and the change of pixel data at a predetermined position is made variable for each word. and frame buffer memory.