JPS6059385A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an image display device capable of scrolling display contents when displaying image information output from a digital computer or the like.

[Background of the invention]

An example of a conventional image display device is shown in FIG. 1. In this figure, 21 is Cp'U, and 2 is a display circuit.

5 is a display such as a CRT, 11 is a signal path for the CPU 1 to supply address signals to each circuit, ie, an address bus, and 12 is a signal path, ie, a data bus, through which the CPU 1 sends and receives data to and from each circuit. . The display circuit 2 includes a display timing pulse generation circuit 21. which generates a synchronization signal of a video signal and a display address signal. A display address switching circuit 221 that alternately switches between the address bus 11 and the display address bus 25 to which the display timing pulse generation circuit 21 supplies display address signals and outputs the display address switching circuit 221. A display RAM 25 that stores display data. It is constituted by a video signal circuit 24 that converts display data read out from the display RAM 25 into a video signal that can be displayed on the CRT 5.

Next, the operation of this image display device will be described.

Assume that the operation of CpUl is known.

The display circuit 2 will be mainly explained below. This circuit employs a known display method known as a cycle steal display method. this is.

In this method, the display address switching circuit 22 alternately connects the address bus 11 and the display address bus 25 to the display RAM 25 in synchronization with the fcpU clock, and performs display through the gaps in which the CPU 1 rewrites data.

That is, the display data of the address output from CpUl is read and written to the CPU period rU to which the address bus 11 is connected. During the display period when the display address bus 25 is connected, the display data at 1/s output from the 1 display timing pulse generation circuit 21 is read out and input to the video signal circuit 24. The display data is converted into a video signal by this circuit and displayed as an image on the screen of the CBr4. Therefore, this method has the advantage that CPVl can access the display RAM 25 without being limited to a specific period and can perform stable display.

In the image display device configured as described above, scroll display is performed by the CpU+ transferring display data. The situation will be explained using FIGS. 2 and 3. First, as shown in Figure 2, what are the characters and figures displayed on the 5 screens?

The data is stored as display data at an address in the display RAM 2s corresponding to the display position. For example, the data representing T in the first row and second column is at address (0001), and the data representing D in the 25th row and 80th column is at address (07CF). Therefore, if the CPU 1 rewrites the display data at a certain address to another address, the display position will shift by one.

In other words, it is displayed in a scrolling manner. For example, if you want to vertically scroll the display upwards, (o 0
50 ), address data (0000) to address 6,
(0051), address 6 is (oool), and then repeat the same operation to rewrite the display data to be scrolled to an address 80 addresses lower. K3 diagram (
A) shows the result of vertically scrolling the portion of FIG. 1 left-h by one line in this manner. If the amount of movement is changed to the first location, horizontal scrolling display as shown in FIG. 5<b> is also possible. In other words, the difference between the forwarding destination address and the forwarding source address (hereinafter referred to as offset) can be arbitrarily determined (
(This allows you to scroll the display in any direction, vertically, horizontally, or diagonally.

Scroll displays such as partial scroll, partial scroll, and window scroll can be easily handled by limiting the area where one display data is transferred. The partial scroll display is a display method in which, for example, up to the fifth line is displayed in a fixed manner, and only the second, sixth and subsequent lines are scrolled, as shown in FIG. In addition, window scroll display is a method in which scrolling is performed only in a specific section on one screen, and in the example shown in Figure 5, only the data in columns 51 to 70 of rows 6 to 20 are scrolled. .

The method of scrolling one display data by software transfer as described above enables extremely flexible scroll display. However, this method has the disadvantage that as the amount of display data increases, a large amount of time is required to transfer it, resulting in a slow scrolling speed. In particular, in recent years, single display devices have become increasingly high-definition and display colors are multicolored, and the amount of data displayed per display is increasing significantly. Take, for example, a display device in which one screen consists of 640 x 400 pixels.

The storage capacity required is 52 bytes. A certain Cp
If U transfers one byte of display data at a rate of 20 μ3, it will take over 0.6 seconds to scroll one line across one screen. For color display, red, blue,
If each color of green had one side of memory, it would take an additional five times this amount, or about two seconds. This means that even if a 25-line character string is scrolled line by line, it will take nearly a minute to reach from the bottom to the top. As described above, data transfer using only software poses the problem that a practical scrolling speed cannot be obtained when the amount of data to be handled increases.

However, in order to improve the above-mentioned scrolling speed, there is also a method of performing scrolling display using hardware. Its features include, for example, as seen in Japanese Patent Application Laid-open No. 56-65182, it is equipped with a scroll counter that generates a display address in sequence, and a latch that sets its initial value.

If the initial value set in this latch is rewritten from the first address of the first line to the first address of the second line, one display will be performed from the second line. In other words, the screen has been vertically scrolled by one line. In this way, since the display data is not actually transferred, the scrolling speed and the amount of data are unrelated, and speeding up can be achieved. Furthermore, in the above patent, a latch, a comparison circuit, etc. are added.

Partial scrolling display is also possible.

However, with the above-described hardware method, scrolling display such as horizontal or diagonal scrolling or window scrolling is not possible. In other words, although the scrolling speed can be increased, there is a disadvantage in that the flexibility of the scrolling display is lost.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image display device that eliminates the above-mentioned drawbacks and can perform high-speed scrolling display without losing the flexibility of the scrolling function realized by software transfer.

[Summary of the invention]

In order to achieve the above object, the present invention includes a holding means for temporarily holding display data read out using a transfer source address output by a CPU, and an address converting means for calculating and outputting a transfer destination address from the transfer source address. , the transfer source address and transfer address are switched and the display RAM
and address switching means for supplying the address. Thereby, when the CPU accesses the display data on the display RAM, the data is held in the holding means, and
A transfer destination address is calculated by the address conversion means. Here, the address switching means performs switching so that the transfer destination address is supplied to the 1 display RAM, and the display data held in the holding means is written to the address. In other words, the CPU only reads display data.

Actual data transfer is performed automatically and redundantly by the circuit described above.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 6 to 8. FIG. 6 is a block diagram showing one embodiment of the present invention, and FIG. 7 is a timing chart thereof.

'In FIG. 6, the same reference numerals are used for the same circuit parts as in FIG. 1. 51 is a mode control circuit that controls each circuit in the scroll mode; 52 is an address offset register that stores the offset value of the transfer address;
55 is an address latch that holds the transfer source address;
34 is an adder circuit that adds the offset value set in the address offset register 52 and the transfer source address held in the address latch 56 and outputs the result as a transfer destination address; A transfer address switching circuit which switches the output address of the adder circuit 54 and supplies it to the display address switching circuit 22; 56 is a data latch that temporarily holds display data accessed by CpUl; 57 is a data bus 12 during a scroll display period; This is a gate circuit that separates the display circuit from the internal data bus 40 of the display circuit.

Next, the operation of the CPU+ shown in FIG. 7 will be briefly described. FIG. 7(a) shows the clock signal applied to CpUl and the display circuit 2. FIG.

In the cycle steal nice play method, this clock signal is used by the CPU 1 to store the display RAM 25 during the HL period.
is accessed and displayed during the LowW period. The numbers above are an example of C' p U 1 requiring 50 steps to access certain data. In this case, instructions and operands are read in the first six clocks and analyzed in the first clock, and data is accessed in the last clock.

Assuming that the CPU 1 operates as described above, the operation of this embodiment will be explained below. First, before starting the scroll display,
CpU+ sets an offset value in address offset register 62.

At this time, if the offset value is negative, that is, the transfer address is lower than the transfer source address, write a value obtained by taking the two's complement of 16 bits as the offset value. The addition circuit 54 performs substantial subtraction, and the transfer destination address is correctly calculated.

Examples of offset values to be set include -80 for the upward vertical scrolling display shown in Figure 6 (a), that is (FFBO), and -80 for the upward vertical scrolling display shown in Figure 5 (a), For example, (FFFF), 6 can be written to the 7 dress offset register 62.

Next, the CpU+ accesses a predetermined register assigned to the mode control circuit 51 to
tells it to enter scroll mode. Then,
The gate circuit 67 closes its gate and disconnects the data bus 12 from the internal data bus 40 of the display circuit. this is,
This is to prevent conflict between the display data output to the internal data bus 40 and other data on the data buffer 12.

Now, if the CPU 1 executes an instruction to access display data to be transferred, the address of the data is output to the address bus 11 at the fifth clock (FIG. 7(C)). This address is taken into the address launch 56 as a transfer source address and simultaneously supplied to the display RAM 23 via the transfer address switching circuit 55 and the display address switching circuit 22. In this way, the display data is output to the internal data bus 40, but since it is separated from the data bus 11 by the gate circuit 37, the CPU 1 does not take in this data. Instead, the data latch 56 captures and holds this display data 7. When the display data launch is completed, the transfer address switching circuit 66 to which the address bus 11 has been connected
is switched, and the adder circuit 54 is connected (7th box)). The output of the adder circuit 64 at this time is as follows.

The address is the sum of the transfer source address held in the address latch 5B and the offset value set in the address offset register 62, that is, the transfer destination address. This transfer destination address is supplied to the display RAM 25 via the display address switching circuit 22, and at the same time, the RAM enters the write state (FIG. 7(d)).

Therefore, the display data held in the data latch 5B is written to the transfer destination address, and finally the transfer address switching circuit 66 connects the address bus 11 again to the transfer address 71.
End the transfer of byte display data (Figure 5 (a))
.

The above is the procedure for transferring 1 byte of display data and scrolling display. Therefore, in order to scroll the entire screen upward by one line, CpUl should perform the following processing. First, as described above, set 6 (FFBO) in the address offset register 52, and set the mode control circuit 1 to 6.
Access the register and set it to scroll mode. After that, the read command (or write command) is executed sequentially from the first character data of the second line until reaching the last character, that is, in the example of Fig. 2, (005[1), from address 6 to (nBsl, address 6). )'ff: Just repeat. Every time a read instruction is executed, the accessed data is (o o s o ), 6 to (OooO), 6.
(oosl), from 6 (aool), 6.・・・・・・
(07CF), 6 to (0771?), 6 are automatically transferred, and the result is a vertical scroll display. The horizontal scrolling display is almost the same. It is only necessary to change the offset value to (FFFF)16 and read out one display data always starting from the second column of each row. In other words, the first line is (0001) from 16 (oo4F)
Up to 16, the second line is (oo5+), 6J: ri (oo9
F),, 'z...' If you read up to the last line, all the characters on one screen will be shifted one character to the left.

Window scrolling can also be easily realized. for example.

As shown in FIG. 8, the 61st column of the 6th row to the 20th row
Suppose you want to scroll display only the section in the 70th column. In that case, the only difference is that reading of display data is limited to the above range. For vertical scroll display, after the same initial settings as above, first set (
olFE), from 6 (0225), read up to 6 1
Next, move to the 8th line (024E) and from 6 (0275)
, up to 6, and repeat the same move 1@ until you reach 6 (066s) on the 20th line. Horizontal scrolling display also
It is easy to imagine that it could be done in a similar way.

To end the scroll display and cancel the scroll mode, the register of the mode control circuit 61 is accessed again. In this way, the transfer address switching circuit 65 becomes fixedly connected to the address bus 11, and the gate circuit 57
opens the gate.

The substantial configuration of the display circuit 2 is the same as that shown in FIG.

In other words, CpU+ can be read as normal 1: to the display RAM 25.

In addition, in the above explanation, 7. The means by which the CpU 1 notifies the display circuit 2 of entering and canceling the crawl mode is to access a predetermined register assigned to the mode control circuit 51 . Another method is to kill a memory area for scroll display in addition to the memory area for normal display, and execute the above-mentioned automatic data transfer only when the CPU accesses the display data in that memory area. can also be considered.

In short, any means may be used as long as the CPU can notify the display circuit of the start and end of scroll display.

〔Effect of the invention〕

According to the present invention, data transfer accompanying scroll display is
This is done automatically by the address signal that the CPU accesses the display data. Therefore, in the case of conventional transfer using only software, two operations were required: reading one display data and writing to a new address, but since the transfer can be performed only by the push-out or write operation, the time can be halved. In other words, the scrolling speed is doubled, resulting in a significant performance improvement.Furthermore, by simply changing the offset value settings, you can scroll in any direction (vertical, horizontal, diagonal), and by limiting the area accessed by the CPU, you can display partial scrolling. , window scrolling display is also possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional image display device, FIG. 2 is a diagram showing the correspondence between display positions of display data and addresses,
Figures 3 to 5 are diagrams showing seven display examples of various scrolls;
5 is a block diagram showing one embodiment of the present invention. FIG. 7 is a timing chart showing the operation of the embodiment, and FIG. 8 is a display example of window scrolling. + 7 CPU, 2 i display circuit, 26; display RAM,
51. Mode control circuit, 62; Address offset register, 65; Address latch, 54; Adder circuit, 65;
Transfer address switching circuit, 661 data latch, 57; gate circuit. Representative Patent Attorney Taku Takahashi / Figure 2 Figure 3

Claims (1)

[Claims] 1. A central processing unit, a storage means for storing 1 image information, and 1.
In an image display device comprising display gamma address generation means for generating a display address, and display means for displaying image information read from the storage means by the display address generation means on a CRT (cathode ray tube), the center holding means for temporarily holding the image information read out from the storage means according to the transfer source address output by the processing device; address converting means for inputting the transfer source address and outputting the transfer destination address; and address switching means for switching between the address and the destination address and supplying the same to the storage means,
When the central processing unit outputs the transfer source address to the storage means, the image information of the address is held in the holding means, and at the same time, the address switching means switches from the transfer source address to the transfer destination address and supplies it to the storage means. . An image display device, characterized in that the image information held in the holding means is written into the storage means. 2. The address conversion means includes a holding means capable of holding an arbitrary value, and an arithmetic means that calculates a transfer source address output from the central processing unit and a value held in the holding means and outputs a transfer destination address. An image display device according to claim 1, comprising: