JPS6073583A - Split display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to display data (luminance signal, coordinate designation data)
The present invention relates to a split display device that inputs information, writes it to a display memory, reads out the contents of the display memory, displays it on a display device, and can be applied to a large screen display device in which a large number of display devices are arranged.

[Technical background of the invention and its problems]

The conventional display method, as shown in Figure 2 (,), is a method in which the drives are connected for each display from A to X on the time axis, and the data saving time is shortened. It's long,
This method was unsuitable for large screen displays with a large number of display devices arranged.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks of the conventional art, and it is possible to display display data such as luminance signal specification data at high speed and in separate sections, and to display a large screen with a large number of display devices arranged. It is an object of the present invention to provide a split display device in which the number of memory refreshes can be obtained arbitrarily, and which does not require much higher-speed bandwidth than a display device in which a display device such as a CRT is controlled.

[Summary of the invention]

The divided display device of the present invention divides the display into a plurality of parts,
After receiving the display data, the write/read control circuit writes it into each memory divided corresponding to the display device, and writes the contents of the memory corresponding to each display device simultaneously for each display device.

Display data is serially outputted so that it can be read out by a loading/reading control circuit, and is stored in a shift register in each display.

[Embodiments of the invention]

Embodiments of the split display device of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment. 1 in the figure is display data, which corresponds to brightness data and coordinate instruction data.

This display data 1 is input to the memory write control circuit 2 and the write/read control circuit 3, and the output of the write/read control circuit 3 is input to the memory write control circuit 2, the memory 5, and the memory read. The signal is output to the control circuit 4.

The write/read control circuit 3 outputs a write/read signal which is the basic timing of writing and reading. When display data 1 is input to the memory write control circuit 2 during the write period, the memory write control circuit The memory write address is transferred from memory 2 to memory 5.

Furthermore, when the write/read control circuit 3 is outputting a read signal, the contents of the memory 5 are read out by the memory read control circuit 4 and transferred to the display 6.

FIG. 3 is a block diagram showing the block diagram of FIG. 1 in more detail, and the configuration will be further described in detail with reference to FIG. In FIG. 3, the same parts as in FIG. 1 are designated by the same reference numerals.

The display data 1, memory write control circuit 2, write/read control circuit 3, and memory read control circuit 4 are the same as those shown in FIG. It differs from FIG. 1 in the following points.

That is, during the write period, the write address 2a output from the memory write control circuit 2 is transferred to the write address register 7, and the output of the write address register 7, that is, the write address 7a multiplexer 8 and decoder 9
I am trying to output it to .

Further, the display data 2b is transferred from the memory write control circuit 2 to the memories 5m and 5b.

Further, the write/read control circuit 3 outputs a write/read signal 3a to the multiplexer 8. Then, the memory read address 4a is transferred from the memory read control circuit 4 to the read address register 10, and the read address 10a is transferred from the read address register 10 to the multiplexer 8. There is.

Write/read address 8 from multiplexer 8
a is transferred to the memories 5a and 5b, and a write chip select signal 9a is also transferred from the decoder 9.

Furthermore, the set clock 4b is outputted from the memory read control circuit 4 to the register 11.12, and the shift clock 4e and P/S (a
p parallel/series) registers 13 and 14.

The outputs of the memories 5h and 5b are input to the registers 11 and 12. The outputs of the registers 11 and 12 are input to the P/S registers 13 and 14, respectively, and the outputs of the P/S registers 13 and 14 are displayed on the display 6a.

6b, respectively.

The display device 6 includes a plurality of display devices 6m, 6 as shown in FIG.
It is divided into b. Although only two are shown in FIG. 3 for convenience of illustration, the number is not limited. This display 6a.

6b corresponds to P/S registers 13 and 14, registers 1 and 12, and memories 5a and 5b.

The display 6 has a Pβ register 13.1 as shown in FIG.
4, the output of the shift register 20 is once transferred to the driver 30.
In addition, this driver 30 also drives a display device 40.

Next, the operation of the split display device of the present invention configured as described above will be explained. When explaining this operation, the third
I will explain this based on the diagram. When the display r-ri1 is input to the memory write control circuit 2, the write/read control circuit 3 outputs the data as shown in FIG. ), a write/read signal 3a, which is the basic timing for writing and reading, is generated and sent to the multiplexer 8.

The display data 1 inputted during the write period is outputted to the memory write address 1/2a by the memory write control circuit 2 and temporarily stored in the write address register 7.

A write address 7a is sent from this write address register 7 to a multiplexer 8 and a decoder 9. As a result, the write chip select signal 9a from the decoder 9 is sent to the memory 5h.

5b to select the chips of memories 5a and 5b, and write address 8 from multiplexer 8.
a is sent to the memories 5a and 5b, and addresses of the memories 5a and 5b are specified.

Therefore, the display data 1 input to the memory write control circuit 2 is transferred from the memory write control circuit 2 to the memory 5m as display data 2b.

5b are sequentially written to the designated addresses of the selected chips.

Next, a case will be described in which the display data written in the memories 5a and 5b is read out in this manner. To read the display data 1 written in the memories 5m and 5b, the read address 4a is sent from the memory read control circuit 4 during the read period of the write/read signal 3a (during the period R in FIG. 4(1)). It is output and temporarily stored in the read address register 10.

During this read period, multiplexer 8
By selecting and outputting the read address 10a stored in the read address register 10 during the read period of the read signal 3&, the leading address of each memory chip of the memories 5a and 5b is designated.

In this FIG. 3, 0 of the memory 5a corresponding to the display 6a is shown.
Addresses 0 to 09 are designated, and addresses 00 to 09 of the memory 5b corresponding to the display 6b are designated.

With this designation, the output terminals A17 to A9 of each memory chip
(Fig. 4 (2) to Fig. 4 α1)) and XO to X9 (Fig. 4 a to Fig. 4 (c)) simultaneously output the contents of 00 to 09.

Output terminals AO to A9 of this memory 5a. The contents 00 to 09 output from the output terminals XO to x9 of the memory 5b are set clocks 4b output from the memory read control circuit 4.
Otherwise, they are stored in registers 11 and 12, respectively, as shown in FIGS. 4(a) and 4(c). This register 11
．． The contents of the 12 parallels are transferred to P/S registers 13.14 respectively.

In this way, registers 11.12 are stored in memories 5a, 5
At the same time that the contents 00 to 09 of b are stored and transferred to the register 13.14, the shift clock 4c is sent from the memory read control circuit 4 to the register 13.14.

As a result, the contents of Pδ registers 13 and 14 are changed to (
(to) and shifted as shown in Figure 4 (c), respectively.
Serial data is transferred to the displays 6a and 6b. P/
The outputs of the S shift registers 13 and 14 drive a display device 40 (see FIG. 5) through a driver 30 for display.

As is clear from the above, in the present invention, the display device 6 is divided into a plurality of units (for example, A to As shown in b), by simultaneously outputting the signals, an optimal display (shown as a non-display period and a display period in FIG. 4(c)) is performed for a display in which the display devices are arranged in a polygonal arrangement.

Therefore, the number of times the memory 6 is refreshed can be obtained arbitrarily, and in FIG. 2(b), the display time T of each surface water layer AX can be arbitrarily selected and displayed.

〔Effect of the invention〕

As described above, according to the divided display device of the present invention, the display device is divided into a plurality of parts, and the display data is received and written into each divided memory corresponding to the surface water layer by the write/read control circuit. The display data is serially output so that the contents of the memory corresponding to each display can be read by the write/read control circuit for each display, and the display data is stored in the shift register in each display. Therefore, display data can be displayed at high speed and divided, a large screen display with a large number of display devices can be displayed, and the memory can be refreshed any number of times.

Further, compared to a display device controlled by a display device such as a CRT, it does not require a high-speed bandwidth.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a split display device according to the invention, FIG. 2 is a diagram showing a comparison of display data output times between the conventional split display device and the split display device according to the present invention, and FIG. FIG. 4 is a time chart for explaining the operation of the split display device of the present invention, and FIG. 5 is a block diagram showing the structure of the display in the improved split display device. It's inside. 2...Memory write control circuit, 3...Write/
Read control circuit, 4... memory read control circuit,
5, '5 a, 5 b-・-)-E:su, 6.6
Th. 6b... Display, 11.12... Register, 13°14... Luhe register.

Claims (1)

[Claims] M number of display devices, a memory write control circuit that receives display data to be displayed on each of the plurality of display devices and writes the display data into each memory corresponding to each display device, and a memory write control circuit that writes the display data to each memory corresponding to each display device; A split display device having means for simultaneously reading data in parallel, converting it into serial data, and supplying the converted data to each of the display devices at the same time corresponding to each of the display devices.