JPS60181784A - Video ram - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dynamic semiconductor memory structure video RA.
Give M 1 meter and 4.

[Technical background of the invention and its problems]

In recent years, Texas Instruments has developed a dynamic RAM with 7 real output functions for video signals.
An IC named 5'rTMs 4161 J has been developed and is commercially available. The internal structure of this IC is shown in block form in FIG. 1 (the specific structure will be explained later).

The above IC? -Video RA of Sonal Computer etc.
The problems when using it as M are the following 1), 2
) can be mentioned.

1) The data line of the CPU has a parallel bit structure of 8 bits, 16 bits, etc., whereas the data line of the RAM has a 1 bit structure.

2) The data transfer time of the CPU is less than or equal to the cycle time of the RAM.

For this reason, in order to match the transfer speeds of the CPU and the upper RAM, it is necessary to arrange the RAMs in parallel by the width of the data bus. An example of this configuration is shown in Figure 2 (
Note that the specific configuration will be explained later).

As mentioned above, 41 RAMs arranged by the width of the data bus
In the 4-channel system, a shift register is not required in addition to the RAM, and an external IC is required.

In this way, when a conventional dynamic RAM with a serial output function for video signals is used as a video RAM for a personal computer, etc.
As mentioned above, since it is necessary to line up the RAM by the width of the data bus, the overall configuration of the video RAM becomes unnecessarily large, and an external IC is required, which makes the overall configuration of the device complicated. This caused the inconvenience of becoming

In addition, in the above-mentioned configuration in which multiple video RAMs are arranged in parallel, it is possible to use a contested area other than the area used as the video RAM as the main memory, but the difference between ξ and the main memory of the CPU is memory access and
Competition with the video RAM access of the CRTC (display controller) occurs, resulting in the disadvantage that the processing speed of the CPU is greatly affected.

[Purpose of the invention]

The present invention was developed in view of the above-mentioned circumstances, and it is possible to handle video signals with a bit width that is compatible with the path structure of the CPU. It is an object of the present invention to provide a video RAM that can simplify the overall configuration of the device by eliminating the need for circuit elements.

[Breaking the bag of invention]

The present invention relates to a dynamic memory device having a serial output terminal for video signals, in which the data input terminal of the memory array is arranged in a multi-bit 9 parallel configuration that is compatible with the data bus width of the CPU. The optimization and external design are intended to reduce the number of circuit elements and simplify the device configuration accordingly.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings. First, before explaining the embodiment of the present invention, a conventional video RAM structure using an existing dynamic RAM will be explained with reference to FIGS. 1 to 4 and FIG. Figure 1 shows a Texas computer with an output function for video signals that is already commercially available.
Dynamic RAM manufactured by Instruments;
It is a block diagram of TMS4161. In the diagram, 11 is 2
56 bits x 256 bits (64K
It is a memory array of bits. Reference numeral 12 is a 256-bit shift register for obtaining serial output, and four sets of outputs from the 0th bit, 64th bit, 128th bit, and 192nd bit are obtained. A control logic (CTL) 13 controls row/column addresses, read/write, and data input/output between the memory array and the shift register. 14 is the address dart (
Add-GATE), and the output is switched between row and column by the signal from the control logic 13, and the serial output selection address A6. It outputs A7. 15 is a serial output dart, and one of the four outputs from the shift register 12 is sent to address A6. Select with A7,
5 out.

16 is a 5-out dart and is controlled by the SOE number.

FIG. 2 is a block diagram showing the connection between the TMS 4161 and the CPU. In the figure, 21 is a CPU, there are m address buses (m bits), and n data buses (n bits). 22 is a fli'l 1fll signal line, which is used for input/output control with the memory, I, and 'o. 23 is m address buses.

24 is n data buses. A memory control logic 25 generates a control signal 46 from the CPU z and a signal for the memory, and also controls the address bus 23.

26 sends signals such as control SOE for memory control'. 27 are eight address buses time-divided for row/column use.

28 is n dynamic RAMs written in parallel corresponding to the bit width (n) of the data bus 24; TMS 4
The memory consists of 161 reeds, one for each of the 24 data buses.
Two TMS 4161 are connected.

FIG. 3 is a block diagram showing a part of the video RAM machine 411) used to obtain a video signal from the memory 28 in FIG. 2. In the figure, number 3 indicates n TMS 4161 (hereinafter referred to as memory IC) that constitute the memory 28.
It is. 32 is a clock generator for video (which becomes the Go history of No. B.33 is a frequency division logic that divides the clock (CLK) from the clock generator 32 by n, and n'ff1 cycle is used. The clock is supplied to the SCK☆il+i child of IC31... of each memory, and the clock is supplied to the shift register 34 as the timing (Th number) for loading 5out of each memory IC31... to the shift register 34. 34 is a shift register, which sets 5out of each memory IC 31 with a pulse from the frequency division logic 33, shifts it according to a clock signal, and outputs it (SO).

FIG. 4 is a conceptual diagram of the video RAM 46 shown in FIG. In the figure, numeral 41 is a memory array, which has a configuration in which 256 rows and 256 columns are n41Ij (the width of the data bus).

42 is a shift register within the memory IC 31 . Reference numeral 43 corresponds to 34 in FIG. 3, and is an n-bit shift register outside the memory (externally attached).

In this way, in the conventional configuration, the memory IC(T
MS 4161) 31... were arranged in parallel by the number (n (14.1)) corresponding to data 11, and an n-bit shift register was provided externally.The operation of the above conventional configuration will be described later. .

Next, an example of the tree brother ψj will be explained.

FIG. 5 is a conceptual diagram of a video RAM according to the present invention. In the figure, 51 is a memory array, and one memory has n
It receives a data bus from the mainland, but has a 256-bit configuration for both rows and columns. 52 is a 256-bit shift register.

Figure 6 shows TMS4161 with the same structure as in Figure 5.
This is a block diagram of the case where the data line 60 is applied to n bits. The configuration shown in FIG. 6 is hereinafter referred to as RAM-1. In the figure, 6) is a memory array that can be randomly accessed in units of n bits. 62 is a 256-bit shift register, with the 0th bit being the 0th bit.

A total of four outputs are obtained from the 64th bit, 128th bit, and 192nd bit. 63 is control logic (CTL)
Controls address, row/column address, read/write, and data input/output between the memory array and shift register. 64 is the r-) circuit for address (Add-GATE)
The output can be switched between row and column by the signal from the control logic 63, and the serial output selection address A can be used.
6. It outputs A7. 65 is a serial output dart, and among the four outputs from the shift register 62, one A6. Select with A7 and make 5 out. 66 is a dart for Bout, and is controlled in both directions.

Figure 7 shows how the data bus is overlapped with the address bus in time division.
Block diagram when the number of pins is prevented from increasing (RAM
-2). In the figure, number 7 is 256 bits x 2
Although it is a 56-bit memory array, because the data bus is connected to the address, random access is performed at about 8-bit QL. 72 is a 256-bit shift register, with the 0th bit and 64th bit.

A total of four outputs are turned on from the 128th bit and the 192nd bit. 73 is a control 10 knock (CTL), which is used for data/address, row/column address, and read/address.
Write and control data input/output between the memory array and the shift register ηij. 74 is a dart circuit (Add-Data-GATE) for address and data;
The system also switches address and data, row and column address with No. 15 from 1110 switch 73, and outputs A6 and A7 for serial output selection. 75 is a serial output dart, and one of the four outputs from the shift register 72 is sent to A6. Select point with A7 and write 5 out. 76 is a 5-out dart and is controlled by SOB.

FIG. 8 and FIG. 8B are block diagrams 1 showing an example of a video RAM mechanism using RAM-2 shown in FIG.
is assumed. In the figure, 81 is a 16-bit CPU, consisting of m address buses and 1.6 data buses. 82 is a control signal line, which is connected to memory or Il.
Provided for input/output Ti1il IQI with o. 83 is m
This is the address bus for books.

84 is 16 data buses. 85 is a control logic (M/P-CT) that performs memory control and control of both 111;
(L) Creates a signal for the memory based on the control signal from the CPU 81, and (A) controls the response path.

861d memory is no good! (6D on line 11r)
, TR/QE', R/v, A7/D.

Sends out signals such as PAS, CAS, SOF, etc. 87 and 88 are hour/minute 17 for row/column and data.
1j address data bus, and 87 and 88 are the same as address buses but different as data buses. For bus 87 in Figure (5), Do to D for 7.8.
8 to 15, and in path 87 in Figure (13), D
O+2 +”' +14.82 is Dl + 3 +
”'+15. 89.89 is 2 RAM
-2. C-G is a clock generator,
This is the standard for video signals. DIV is the figure (4
) is the frequency division logic that divides the frequency by 16. In the example shown in Figure (5), an 87.88 address data bus is a common type, so the clock generator (CG) is devised, and an 8-bit 5
out, then the 8-bit 5 from the other RAM -2
This is so that out can be obtained. In the example shown in FIG. 3(B), instead of dividing the period from the clock generator (CG) and outputting 5 outs alternately, the wiring of the data bus to the RAM is also alternately performed.

Figure 9 shows each of the defects in Figures 8 (A) and (B), namely Figure (
This is a block diagram of a RAM (hereinafter referred to as RAM-3) that solves the problem of not being able to access only one RAM when using the configuration shown in Figure (B). ). In the figure, 91 is 256 bits,
This is a memory array of 256 bits. 92 is a 256-bit shift register for obtaining serial output; the 0th bit is a 256-bit shift register.

A total of four outputs are obtained from the 64th bit, 128th bit, and 192nd bit. 93 is the serial output control logic (So-CTL), and one RAM is the SC
Output Sout for 8 clocks of K input,
It also tells the other RAM-3 the timing to output 5out and the completion of output.

A control logic (CTL) 94 controls data/address, row/column address, read/write, and data between the memory array and the shift register. 95 is for address and data) (Add-Data
-GATE), the address is switched to address and data, row and column by the signal from the control logic 94, and the serial output selection address A6. After outputting A7. 96 is a serial output dart, and one of the four outputs from the shift register 92 is connected to A 6 ,
A: Select 18 at 7 and get 5 out. 97 is a dart using Sou and is controlled by a signal from the serial output control logic.

FIG. 10 shows an example in which RAM-3 shown in FIG. 9 is used as a video RAM with a 16-bit data path.

In the figure, 101 has m address buses and 16 data buses.
It is a CPU made up of books.

A control signal line 102 is used for input/output control of the memory and Ilo. 103 is m address buses. 1θ4 is 16 data buses. 105 is a control logic (hereinafter referred to as MC/P) that performs memory control and screen control.
The C-CTL logic (referred to as C-CTL logic) generates a control signal No. 46 for the memory according to a control signal from the CPU 1o1, and controls the address bus 103. 106 is the control signal line for memory fi, TR/Qg, R/v
.

~ Send out the names of RAS and CASO. 1o7
゜ and 10& are time-divided address/data buses for row/column and data; 1o7 and 108 have the same address but different data buses. 107 is Do~7°108 is D8~III. 109, 109 are two RAM-3s. C-
G is a clock generator, which serves as a reference for video signals.

Figure 11 shows a RAM (hereinafter referred to as RAM
M-4). Here, the configuration is the same as the RAM-3 configuration in FIG. 9 except that the configuration of the serial output control logic 93 is different, and the same parts are denoted by the same reference numerals and the explanation thereof will be omitted.

FIG. 12 shows an example in which RAM-4 shown in FIG. 11 is used as a video RAM using a 16-bit data bus. In the figure, 206 is connected to the control signal line 106 in FIG.
This includes an OE signal line. 209, 209 is RAM-4 shown in FIG. 21 is a logic that is wired-OR connected to the RAM L7) E out on the lower data side and controls Eln of the RAM on the upper data side. 212 is the upper side RA of data
This is the logic that controls the Ein of the RAM of the lower i+I data by wired OR connection of Eout of M.

Figure 13 is a time chart for explaining the operation of Figure 3 above, Figures 14 to 17 are time chart diagrams for explaining and explaining the operation of Figure 7 above, respectively.
The figure shows read cycle timing, FIG. 15 shows write cycle timing, No. 16 shows page mode read cycle timing, and FIG. 17 shows page mode write cycle timing. Figure 18 is the 8th figure above.
Time chart for explaining the operation in Figure (4), 1st
9 is a time chart for explaining the operation of FIG. 8(B) above, FIGS. 20 and 21 are time charts for explaining the operation of FIG. 9 above, and FIG. 22 is a time chart for explaining the operation of FIG. 11 above. 3 is a time chart for explaining the operation shown in the figure.

23, I(A) is an example of the bin arrangement of RAM-1 shown in Fig. 6, (D) is an example of the pin arrangement of RAM-2 shown in Fig. 7, and (C) is an example of the pin arrangement of RAM-2 shown in Fig. 9. The pin arrangement example of RAM-3 shown in FIG. 11 and the example of the bin arrangement of RAM-4 shown in FIG.

Here, the operation of the embodiment will be explained. First, Figures 1 to 4r
The operation of the video RAM using TMS4161 will be explained with reference to A1 and FIG. 13. 7 shown in Figure 1
M84161 random read/write operation is AO”
”” Set a random address to A 7 and Tn/Q
Set E to @I (high) and then set RAS to Low. When RAS goes to "Low '", TR/Q18 goes to H.
i gh”, random read/write of the memory array 11 is performed. Next, column addresses A, -A7
Set it to CAS wo@Low'. These operations access the memory specified by the rask and column address of the memory array 1). By reading, an output can be obtained at Q. When the light
It is written by setting data in D and then setting W to "Low". Furthermore, in page mode read/write, if a row address is set first, the 256 bits indicated by the row address can be read/written one after another using only the column address. Refreshing is also performed by simply specifying a row address, similar to the normal 64-bit RAM.

At this time, CAS and TR/QE are set to "Hi gb". Transfer between the shift register 12 and memory array 1 is almost the same as random read/write.
The difference is that the 256-bit memory array 11 and shift register 12 specified by the row address is opened. It becomes possible to transfer data between the two.

When W is "High", data is transferred from memory array 1 to shift register 12, and when W is "Low", data is transferred from shift register 12 to memory array 1. The serial output from is 4
With book, 0 bit, 64 bit, 128 bit, 192
It comes out from the bit eye. For this selection, CAS is Low”
When the address line is A.6. This is done by A7.

And - if you make a counter-selection, the selection result continues to be retained.

Here, the video signal generating means of the video RAM configured using the memory shown in FIG. 1 will be explained with reference to FIGS. 3 and 13. The frequency of the clock generated by the clock generator 32 is divided by the n frequency division logic 33, and the frequency is divided by the clock generator 32.
8, to obtain a serial output (5oot(i)). This data is set in the shift register 34 provided outside the memory 28 by a pulse (shift register low pulse) separately output from the n frequency division logic 33. A clock is directly input to the shift register 34, and the data set υ is shifted by this.
This becomes the final serial output (SO).

Next, the operation according to the embodiment of the present invention will be explained.

The operation timing of RAM-1 shown in FIG. 6 is similar to that of the dynamic RAM (TMS4161
).

The operation timing of RAM-2 shown in FIG. 7 will be explained using FIGS. 14 to 17. As shown in FIGS. 14 to 17, the read/write timing is basically the same as in the case of FIG. 1 described above. However, since the data and address are processed in a time-sharing manner, after setting the column address in RAM using CAS, ADo is used for reading.
~Set data to AD7 and set A/D to “Low” (when setting the address, ~Φ is “High”)
″).Also, when writing, after setting the column address,
By setting A/D to “Low”, the data will be
- Output to AD7. Also, a data transfer operation from the refresh operation memory array 7 to the shift register 72,
The operations of the shift register 72 and the like are the same as in the case of FIG. 1 described above.

In the configuration of FIG. 8(4), as shown in the time chart of FIG.
After obtaining 8-bit 5out from one RAM (RAM-2) 89 using the clock from C) and the signal from the divide-by-16 logic (DIV), the next 8-bit 5out is obtained from another RAM (R
AM-2) Obtains 8-bit 5out from 89. The configuration of FIG. 8(B), as shown in FIG. 19, provides each RAM (RAM-2) 89.
M (RAM-2) Outputs 5 out alternately to 89.89.

The operation of RAM-3 shown in FIG. 9 is random read/
Write and refresh operations are the same as in the case of RAM-2 shown in FIG.

Regarding serial output, the timing is shown in FIG. FIG. 10 shows an example of a video RAM circuit (1f) using the RAM-3 described above.

When Ein becomes Hj gh, Bout is obtained. Then, when 8 bits are output, 5out stops and a pulse is output to Kout. This Eout is transferred to the next RAM (RAM -s) J o y is Ein
Then, repeat the action you just described. Moreover, the timing regarding TEH is shown in FIG. RAS is “Low”
When TR/QE and TER are LOW, serial output starts to be output from that RAM (RAM-3) 109.
When 5out of 8 bits each is output using Ein and Eout, reset the RAM by TER) L, RAM with TER "Low", 1: D The series of serial outputs starts again.

The operation of RAM-4 shown in FIG. 11 is almost the same as that of RAM-3 shown in FIG. 9 described above. The difference is that in RAM-3, the start of a series of serial outputs is specified by TER, but in RAM-4, when specifying the start, 1 is wired ORed with gout.
The start of the serial output is specified by controlling Ein with the signal line.

If line (g) is set to “Low”, gout will be set to “H”.
Even if it becomes "high", Ein remains at "l, □w", and R4 to ■ (RAM-4) do not output at the next clock. When the above signal tax is “High”, E
When out becomes -High, Ein becomes -H1gh
”. As a result, this RAM will output from the next clock. Immediately after turning on the power, each RAM outputs serial output for 8 clocks, and then Eout becomes @Hi g
The serial output control logic 93AK power-on reset circuit of FIG.

As described above, the data input end of the memory array is connected to the i-bit (e.g. 8 bits)-4' corresponding to the CPU path-i.
By using a parallel structure, there is no need to arrange RAM chips to match the CPU bus width, and therefore it is possible to easily obtain a video RAM with the desired memory array, while reducing external circuitry. You can configure the configuration
It can be accumulated. Furthermore, in the r TMS 4161 J, if you try to increase the storage content of the memory chip beyond the current level, you will have to increase the number of address line bins accordingly, but in the above example, the number of bins for the address line will increase to 512 bits. There is no need to increase the number of bins.

[Effect of departure]

As described above, according to the video RAM of the present invention, in a dynamic memory device having a serial output terminal for video signals, the data input terminal of the memory array has a multi-bit parallel configuration adapted to the r-tabus width of the CPU. By doing this, it is possible to optimize the memory capacity of the video RAM, reduce the number of circuit elements for foreign communications, and make the equipment configuration more subdivided.

[Brief explanation of the drawing]

1 to 4 are block diagrams explaining the conventional video RAM configuration, FIG. 5 is a conceptual diagram illustrating the basic configuration of the present invention, and FIG. 6 is a block diagram illustrating the basic configuration of the present invention. FIG. 7 is a block diagram showing the configuration of the RAM (RAM-1) in the second embodiment of the present invention.
(RAM-, ?) A block diagram showing the Q configuration in FIG. 8) and FIG. 8(B) respectively show a video RAM using the RAM (RAM-2) in the second embodiment.
FIG. 9 is a block diagram showing a configuration example of a 4H structure, FIG. 9 is a block diagram showing a configuration of RAM (RAM-3) in the third embodiment of the present invention, and FIG. FIG. 11 is a block diagram showing a configuration example of a video RAM mechanism using a RAM (RAM-3) according to a fourth embodiment of the present invention. Figure 12 shows the RAM in the fourth embodiment.
13 to 22 are a block diagram showing an example of the configuration of a video RAM mechanism using (RAM-4), and FIGS. 13 to 22 are time charts for explaining the operation of the above embodiment, respectively.
Figure (4) shows the RAM (' R
(B) is a diagram showing an example of the bin arrangement of RAM (RAM-2) in the second embodiment, and (C) is a diagram showing an example of the bin arrangement of RAM (RAM-2) in the second embodiment. Figure (6) shows an example of the arrangement of RAM (RAM-3) in the fourth embodiment.
-4) is a diagram showing an example of the bin arrangement. 51.61, 71.91...Memory array, 52.6
2,72.92...shift register, 63.73,8
5,94,105...control logic, 64.74...
・Dart circuit, 65.75°96...Serial output dirt, 66.76.97...-5out f-), 8
J, 101・CPU, 82. 86.102,106...Control signal line, 83°1
03...Address bus, 84,104...Data bus, 87.88,107,108...Address/data bus, 89.89...RAM-2,9J. 93A...Serial output control logic, 109°10
9...RAM -3,209,209...RAM
-4゜Applicant's representative Patent attorney Takehiko Suzue Figure 5 Figure 6 Figure 7 Figure 14 read cycle timing Figure 15 write cycle timing Figure 23 (A) (C) CB) CD)

Claims (2)

[Claims] (1) In a dynamic memory device having a serial output terminal for video signals, the data input terminal of the memory array is configured in an n-bit parallel configuration, and the data input terminal of the memory array is connected to the memory array via an n-bit-wide path. Video RAM characterized by writing data at - position 0 (2) The video AM0 according to claim 1, characterized in that an internal address line for addressing the memory array is used as an internal data line of the memory array in a time-sharing manner.