JP5924104B2 - Image processing apparatus and image forming apparatus - Google Patents

Description

  The present invention relates to an image processing apparatus and an image forming apparatus, and more particularly to a technique for efficiently performing bus use right arbitration in response to requests from a plurality of data transfer circuits when a memory capable of burst transfer is used.

  In the image forming apparatus, it is necessary to process a large amount of image data in a short time as resolution and productivity are improved. For this reason, it is configured to handle data in a memory that can handle data at high speed.

  For example, a semiconductor memory such as DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) capable of burst transfer is used to increase the amount of memory that can be transferred at one time and to increase the speed.

  For DDR SDRAM, the amount of data that can be burst transferred (burst transfer length) is increased to 2 times, 4 times, and 8 times that of the basic SDRAM, such as DDR, DDR2, and DDR3. Progressing in the direction.

  Further, when a plurality of circuits make a data transfer request to the memory, it is necessary to provide a memory arbitration circuit and appropriately assign the right to use the bus.

  Note that the following patent documents and the like have been proposed for memory arbitration when performing high-speed data transfer in SDRAM.

JP 2011-180654 A

  Further, in a process such as 2 in 1 that forms two images on one sheet, a process of rotating the image by 90 degrees is required. For this reason, image rotation processing is also made faster and easier by handling the pixels in a square area in a grouped state such as N pixels × N pixels on the memory. In this case, increasing the square pixel size may increase the burst transfer length described above, and may enable high-speed processing.

  However, in the above case, increasing N itself constituting one block increases the amount of data that can be handled at one time, but requires a large amount of internal memory necessary for image rotation processing, which is not practical.

  Further, in the method described in Patent Document 1 described above, the amount of memory that can be transferred at one time is increased by using a semiconductor memory such as DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) capable of burst transfer. , Trying to speed up. It has been proposed that a continuous request signal is provided so that the arbitration circuit gives a continuous bus use right to one data transfer circuit. This is expected to enable high-speed continuous data transfer.

  However, in the meantime, another data transfer circuit cannot handle the data, resulting in a new problem that the performance of the entire apparatus is lowered as a whole.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus and an image forming apparatus that can efficiently arbitrate a bus use right in response to requests from a plurality of data transfer circuits when a memory capable of burst transfer is used. .

  The above-described problems are solved by the following image processing apparatus or image forming apparatus.

A plurality of data transfer circuits for processing image data by performing at least one of input and output of image data, a memory capable of continuous data transfer, a bus connected to the memory, and from the data transfer circuit An image processing apparatus having an arbitration circuit that arbitrates a bus use right when using the memory in response to a request, and a control unit , or an image forming apparatus having the image processing apparatus, wherein the control unit After adjusting the burst transfer length, which means the number of continuous data transfer, so that the memory transfer bandwidth satisfies the total data transfer bandwidth required for each of the data transfer circuits, each data transfer circuit so as to satisfy the bandwidth of required data transfer, allocate bandwidth for each data transfer circuit by adjusting the burst transfer length, said arbitration circuit Imparts the bus use right according to the burst transfer length that is adjusted to meet the bandwidth of each data transfer circuit is required data transfer, characterized in that.

  The arbitration circuit described above grants the bus use right according to the burst transfer length when the data transfer circuit performs sequential access to the memory.

  Further, the arbitration circuit described above repeats continuous data transfer for a plurality of channels at the same position a plurality of times for image data in units of N × N pixels when the data transfer circuit performs random access to the memory. In this way, data transfer of the band is performed.

Moreover, the said control unit described above, the burst transfer length in that vibration split to the respective data transfer circuit, fulfills the required bandwidth is the band of each of the data transfer circuit required data transfer, the burst allocated bandwidth determined by dividing swing the transfer length is such portion that exceeds the required bandwidth is reduced.

A plurality of data transfer circuits for processing image data by performing at least one of input and output of image data, a memory capable of continuous data transfer, a bus connected to the memory, and from the data transfer circuit In an image processing apparatus having an arbitration circuit that arbitrates a bus use right when using the memory in response to a request, and a control unit , or an image forming apparatus having the image processing apparatus, the control unit includes a memory Each data transfer circuit is required after adjusting the burst transfer length, which means the number of consecutive data transfers, so that the transfer bandwidth of the data satisfies the total data transfer bandwidth required for each data transfer circuit. to meet the bandwidth of the data transfer, allocate bandwidth for each data transfer circuit by adjusting the burst transfer length, arbitration circuit, the data transfer circuit which Depending on the requests from a plurality of data transfer circuits in the case of using the to impart the bus use right, which can burst transfer memory in response to a burst transfer length that is adjusted to meet the bandwidth of data transfer required The bus use right can be adjusted efficiently.

  In addition, the arbitration circuit described above provides the right to use the bus according to the burst transfer length when the data transfer circuit performs sequential access to the memory, while taking advantage of the characteristics of the memory capable of burst transfer. In accordance with requests from a plurality of data transfer circuits, the bus use right can be arbitrated efficiently.

  Further, when the data transfer circuit performs random access to the memory, the arbitration circuit described above repeats continuous data transfer for a plurality of channels at the same position for image data in N × N pixel units a plurality of times. By using data transfer, it is possible to efficiently arbitrate bus usage rights in response to requests from multiple data transfer circuits without reducing the efficiency even in the case of random access when using a memory capable of burst transfer. Yes.

Further, the above control unit, the burst transfer length in that vibration split for each data transfer circuit, fulfills the required bandwidth is the band of each of the data transfer circuit required data transfer, split swing burst transfer length By reducing the portion where the allocated bandwidth determined by the number exceeds the required bandwidth, the bandwidth allocated to other data transfer circuits is not reduced, that is, without waste, efficiently and efficiently from a plurality of data transfer circuits. The bus use right can be adjusted upon request.

  Further, according to the image processing apparatus and the image forming apparatus, since it is possible to efficiently arbitrate the right to use the bus, even if the processing circuit is operated at a lower clock than in the past, sufficient processing can be performed as a result. Low power can be achieved.

It is a block diagram which shows schematic structure of embodiment of this invention. It is a flowchart which shows operation | movement of embodiment of this invention. It is a flowchart which shows operation | movement of embodiment of this invention. It is a flowchart which shows operation | movement of embodiment of this invention. It is explanatory drawing which shows the mode of the data processing of embodiment of this invention. It is explanatory drawing which shows the mode of the data processing of embodiment of this invention. It is explanatory drawing which shows the mode of the data processing of embodiment of this invention.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments (embodiments) for carrying out an image processing apparatus and an image forming apparatus of the present invention will be described below in detail with reference to the drawings. Here, the embodiment will be described using an image forming apparatus including the image processing apparatus as a specific example.

〔Constitution〕
Here, the configuration of the image forming apparatus 100 of the embodiment will be described in detail with reference to FIG. Note that descriptions of general parts that are known as the image forming apparatus 100 and are not directly related to the characteristic operations and controls of the present embodiment are omitted.

  An image forming apparatus 100 illustrated in FIG. 1 performs at least one of an overall control unit 101 that controls each unit, an operation display unit 105 that allows an operator to perform various operation inputs and various displays, and input and output of image data. A plurality of data transfer circuits 110a to 110e that process image data in the memory, and a storage control unit 120 that arbitrates bus use rights and performs memory control when using the memory in response to a request from the data transfer circuit; , A memory 130 capable of continuous data transfer, and a bus B connecting between the storage control unit 120 and the memory 130.

  Here, the overall control unit 101 includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like (not shown). Here, the CPU uses a predetermined area of the RAM as a work area, executes various programs stored in the ROM, and comprehensively controls each unit of the image forming apparatus 100.

  The operation display unit 105 includes input devices such as a keyboard, a mouse, and a touch panel, and transmits various input instruction signals to the overall control unit 101. The operation display unit 105 includes display means such as an LCD (Liquid Crystal Display) and a CRT (Cathode Ray Tube), and displays various image data input from the overall control unit 101. The operation display unit may be a separate operation unit and display unit, but may be a touch panel that presses a displayed icon or key.

  The data transfer circuits 110a to 110e are, for example, a data transfer circuit 110a serving as a scanner that reads an original and generates input image data in RGBA format, and performs input image processing on the input image data in RGBA format to generate an image in YMCKA format. Data transfer circuit 110b as an input image processing unit for converting to data, YMCKA format image data and data transfer circuit 110c as a non-volatile storage unit for storing various data, YMCKA format image data for output (image formation) The data transfer circuit 110d as an output image processing unit that converts the image data into YMCK format image data, and the data transfer circuit 110e as a printer that receives the YMCK format image data and forms an image on paper can be configured.

  The scanner serving as the data transfer circuit 110a outputs image data in RGBA format after performing image processing such as shading correction, scaling, and tilt correction. The input image processing unit as the data transfer circuit 110b has a function of changing processing depending on whether the image is color or monochrome. If the input image data obtained by the scanner is a color image, color conversion is performed. Input image processing such as (RGB → YMCK) is performed. The output image processing unit as the data transfer circuit 110d performs output image processing such as printer gamma conversion, error diffusion processing, and smile variable magnification processing necessary for image formation on the stored image data. The printer as the data transfer circuit 110e is an electrophotographic or various image forming unit or printing apparatus, and corresponds to a print engine that forms and outputs an image on a predetermined recording sheet in a copying machine, a printer, a facsimile machine, or the like. It is a part to do.

  Further, specific examples of the data transfer circuits 110a to 110e are not limited to this.

  Here, R (red), G (green), B (blue), and A (tag data or attribute information) are meant. Further, Y (yellow), M (magenta), C (cyan), K (black), and A (tag data or attribute information) are meant.

  The storage control unit 120 stores data for accessing the memory 130 corresponding to the data transfer circuits 110a to 110e, and refers to the data stored in the buffers 120a to 120e by a round robin method or the like. A memory arbitration circuit 121 that grants a bus use right, a multiplexer 122 that grants data transfer between one of the data transfer circuits 110a to 110e and the memory 130 according to the bus use right granted by the memory arbitration circuit 121, and a memory 130 The memory controller 125 is configured to be controlled.

  Here, the memory arbitration circuit 121 means the number of continuous data transfers when each of the data transfer circuits 110a to 110e satisfies a necessary data transfer band (referred to as a necessary band). Control is performed to assign a burst transfer length to each data transfer circuit and to grant a right to use the bus according to the burst transfer length.

  Here, the memory arbitration circuit 121 and the memory controller 125 are shown as an integrated configuration as the storage control unit 120, but the memory arbitration circuit 121 and the memory controller 125 may exist separately and independently.

  The memory 130 uses a semiconductor memory such as DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) capable of continuous data transfer by burst transfer, and increases the amount of memory that can be transferred at one time. It is something to remember.

[Operation]
First, the overall control unit 101 calculates the amount of data handled by each of the data transfer circuits 110a to 110e (step S101 in FIG. 2). In the image forming apparatus 100, the data amount is determined according to the resolution of the image, the number of colors (channels), the number of gradations, and the paper size.

  For example, the data amount of one sheet of A4 size with a resolution of 600 dpi is 137 Mbytes in the case of four RGBA channels in a scanner and 8-bit gradation per pixel. The data amount of one A4 size at 600 dpi resolution is 85.7 Mbytes in the case of compressed image data of 5 bits of YMCK and 4 bits gradation per pixel. In the case of image data for image formation of four bits of YMC and 8-bit gradation per pixel, the data amount of one sheet of A4 size with a resolution of 1200 dpi is 548.2 Mbytes.

  That is, DMA # 1, which is the output of the data transfer circuit 110a, transfers data of 8 bits per pixel with 4 channels of resolution 600 dpi and RGBA, so the data amount is 137 Mbytes. DMA # 2, which is an input of the data transfer circuit 110b, transfers data of 8 bits per pixel with 4 channels of resolution 600 dpi and RGBA, so the data amount is 137 MB. Since DMA # 3, which is the output of the data transfer circuit 110b, transfers data of 4 bits per pixel with 5 channels of resolution 600 dpi and YMCKA, the data amount is 85.7 Mbytes. DMA # 4, which is an input of the data transfer circuit 110c, transfers data of 4 bits per pixel with 5 channels of resolution 600 dpi and YMCKA, so the data amount is 85.7 Mbytes. DMA # 5, which is the output of the data transfer circuit 110c, transfers data of 4 bits per pixel with 5 channels of resolution 600 dpi and YMCKA, so that the data amount is 85.7 Mbytes. DMA # 6, which is an input of the data transfer circuit 110d, transfers data of 4 bits per pixel with 5 channels of resolution 600 dpi and YMCKA, so that the data amount is 85.7 Mbytes. DMA # 7, which is the output of the data transfer circuit 110d, transfers data of 8 bits per pixel with 4 channels of resolution 1200 dpi and YMCK, so the data amount is 548.2 Mbytes. DMA # 8, which is an input of the data transfer circuit 110e, transfers data of 8 bits per pixel with 4 channels of resolution 1200 dpi and YMCK, so the data amount is 548.2 Mbytes.

  The overall control unit 101 then adds the bandwidth required for each data transfer circuit 110a to 110e to handle data in the unit processing time (required bandwidth) and the total required bandwidth of all the data transfer circuits 110a to 110e. A bandwidth (required total bandwidth) is calculated (step S102 in FIG. 2).

  Here, the unit processing time means that when the image forming apparatus 100 has the ability to process 120 sheets of paper per minute, it is only necessary to process one sheet of image data in 0.5 seconds. Equivalent to seconds. However, DMA # 1 that is a scan input and DMA # 8 that is a printer output need to be synchronized with the control signal, and there is a sheet-to-sheet interval (between sheets). Here, if the interval between sheets is about 0.1 seconds, it is necessary to process one piece of image data in 0.4 seconds, so 0.4 seconds is a unit processing time.

in this case,
DMA # 1 is 137 MB / 0.4 seconds = 342.5 MB / s,
DMA # 2 is 137 MB / 0.5 seconds = 274 MB / s,
DMA # 3 is 85.7 Mbytes / 0.5 seconds = 171.4 Mbytes / s,
DMA # 4 is 85.7 Mbytes / 0.5 seconds = 171.4 Mbytes / s,
DMA # 5 is 85.7 Mbytes / 0.5 seconds = 171.4 Mbytes / s,
DMA # 6 is 85.7 Mbytes / 0.5 seconds = 171.4 Mbytes / s,
DMA # 7 is 548.2 Mbytes / 0.5 seconds = 1096.4 Mbytes / s,
DMA # 8 is 548.2 Mbytes / 0.4 seconds = 1370.5 Mbytes / s,
become. The required total bandwidth is 3769 Mbytes / s.

  The overall control unit 101 calculates the burst transfer length so as to satisfy the above required bandwidth and the required total bandwidth (step S103 in FIG. 2). In this embodiment, the burst transfer length means the amount of data when performing one burst transfer.

  The image forming apparatus 100 may require image rotation, and packing and handling image data in units of N × N pixels forming a square makes the number of vertical and horizontal pixels equal before and after the image rotation processing. Even when the rotation process is performed, efficient data transfer is possible.

  However, even if the burst transfer length is increased when there is only one channel, the efficiency may be poor. Therefore, N × N pixels at the same position of 4 channels of RGBA or 5 channels of YMCKA are to be transferred, and the burst transfer length It is desirable to increase. The efficiency at the time of image rotation will be described in detail later with reference to FIGS.

  For example, if the interface with the memory 130 is 64 bits and compressed image data of 4 bits per pixel is packed and processed in units of 8 × 8 pixels, the burst transfer length is set to 16 in the case of 4 channels such as RGBA, YMCKA In the case of 5 channels, the burst transfer length is 20.

  In the case of the above specific example, DMA # 2, DMA # 4, and DMA # 6 are not sequential access but random access, so the burst transfer length cannot be larger than the above 16 or 20. Even if 64 burst transfer is used, it takes four times as long as 16 burst transfer, and the meaning of increasing the burst transfer length is lost. In addition, DMA # 7 and DMA # 8 access different addresses for each channel because the image formation timing differs for each color. Therefore, in order to increase the transfer efficiency, it is necessary to increase the burst transfer length by sequential access within the channel.

  Here, the overall control unit 101 calculates the transfer bandwidth of the memory 130 when the burst transfer length calculated as described above is used (step S104 in FIG. 2). Further, the overall control unit 101 determines whether the calculated transfer bandwidth satisfies the necessary total bandwidth calculated in step S102 (step S105 in FIG. 2).

  For example, when a semiconductor device conforming to the DDR3-1066 standard is used as the memory 130, when a random read / write address is accessed with the above burst transfer length, the memory transfer bandwidth is about 2899 Mbyte / s. Become. Since this transfer bandwidth (2899 Mbyte / s) cannot satisfy the necessary total bandwidth (3769 Mbyte / s) calculated in step S102 (NO in step S105 in FIG. 2), the overall control unit 101 performs burst. The transfer length is recalculated (step S103 in FIG. 2).

Here, when handling 4 channels of image data, the burst transfer length is 64, and when handling 5 channels of image data, the burst transfer length is 80, which is defined as a unit for arbitrating at one time. The transfer length is
In DMA # 1, burst transfer length = 64,
In DMA # 2, burst transfer length = 16 × 4
In DMA # 3, burst transfer length = 80,
In DMA # 4, burst transfer length = 20 × 4
In DMA # 5, burst transfer length = 80,
In DMA # 6, burst transfer length = 20 × 4
In DMA # 7, burst transfer length = 64 × 4
In DMA # 8, burst transfer length = 64 × 4
Can be determined.

  Here, the case of 16 × 4 means that the burst transfer length is set to 16 and is repeated four times.

When the burst transfer length is determined as described above, the bandwidth allocated to each DMA is 266 Mbyte / s for DMA # 1.
DMA # 2 is 266 Mbyte / s,
DMA # 3 is 332 Mbyte / s,
DMA # 4 is 332 Mbyte / s,
DMA # 5 is 332 Mbyte / s,
DMA # 6 is 332 Mbyte / s,
DMA # 7 is 1064 Mbyte / s,
DMA # 8 is 1064 Mbyte / s,
become.

  The transfer bandwidth in this case is 3988 Mbyte / s, which satisfies the necessary total bandwidth (3769 Mbyte / s) calculated in step S102 (YES in step S105 in FIG. 2).

  However, the band due to the above burst transfer length does not satisfy the required band obtained in step S102 in DMA # 1, DMA # 2, DMA # 7, and DMA # 8 (NO in steps S106 and S107 in FIG. 2). ).

  Note that DMA # 8 is data transfer for sending image data to the image transfer circuit 110e (printer). If there is a shortage in this portion, a serious malfunction such as inability to print at a normal position occurs.

  When the bandwidth of each of the above DMAs is examined in detail, the required bandwidth is 171 Mbytes / s in DMA # 3 to DMA # 6 that satisfies the required bandwidth, but is nearly twice as high as 332 Mbytes / second. Bandwidth is allocated and the waste is extremely high. If there is such a useless bandwidth, the bandwidth that can be allocated to other DMAs is narrowed. Therefore, it is necessary to increase the burst transfer length as a whole, and the capacity of the buffers 120a to 120e must be increased in conjunction with this, resulting in increased waste.

  Therefore, for DMA # 3 to DMA # 6 to which a bandwidth that greatly exceeds the required bandwidth is allocated, the burst transfer length is adjusted so as to be as low as possible within a range that satisfies the required bandwidth (see FIG. 2 in step S108). Further, in a portion that is significantly below the required bandwidth, the burst transfer length is increased according to the required degree (step S108 in FIG. 2). As a result, the bandwidth allocated to other insufficient DMAs is relatively increased, and the necessary bandwidth can be satisfied without waste as a whole. Further, the capacities of the buffers 120a to 120e can be set to appropriate values.

Here, the burst transfer length of each DMA is
In DMA # 1, burst transfer length = 80,
In DMA # 2, burst transfer length = 16 × 4
In DMA # 3, burst transfer length = 40,
In DMA # 4, burst transfer length = 20 × 2,
In DMA # 5, burst transfer length = 40,
In DMA # 6, burst transfer length = 20 × 2,
In DMA # 7, burst transfer length = 64 × 4
In DMA # 8, burst transfer length = 80 × 4
It is determined.

The bandwidth allocated to each DMA when defining the burst transfer length as above DMA # 1 is 3 52M bytes / s,
DMA # 2 is 282 Mbyte / s,
DMA # 3 is 176 Mbyte / s,
DMA # 4 is 176 Mbyte / s,
DMA # 5 is 176 Mbyte / s,
DMA # 6 is 176 Mbyte / s,
DMA # 7 is 1129 Mbyte / s,
DMA # 8 is 1411 Mbyte / s,
become.

  In this case, each transfer band exceeds the required band (YES in step S107 in FIG. 2).

Therefore, the overall control unit 101 repeats the above burst transfer length or burst transfer length.
The weight of DMA # 1 is 5,
DMA # 2 has a weight of 4,
DMA # 3 has a weight of 2,
DMA # 4 has a weight of 2,
DMA # 5 has a weight of 2,
DMA # 6 has a weight of 2,
The weight of DMA # 7 is 4,
The weight of DMA # 8 is 5,
(Step S109 in FIG. 2).

  As described above, by setting the burst transfer length so that the required bandwidth obtained from the data amount handled by each of the data transfer circuits 110a to 110e is satisfied and is not wasted, all data transfer is completed within the unit processing time. As a result, smooth processing becomes possible. Note that the specific numerical values used in the above description are merely examples, and the present invention is not limited thereto, and various changes can be made.

  According to this embodiment, since continuous and efficient reading and writing are possible, even if the processing circuit is operated at a lower clock than in the past, sufficient processing can be performed as a result, and low power can be achieved. it can. In addition, since it is possible to use a control circuit and a memory that are slower than conventional ones, it is possible to reduce the cost of the apparatus.

  A specific example (1) of the arbitration operation will be briefly described below. Here, the operation in the case where the end signal does not exist will be described with reference to the flowchart of FIG. The case where the end signal does not exist is performed in a state where there is a margin in the processing of each of the data transfer circuits 110a to 110e as the entire image forming apparatus 100.

  First, the overall control unit 101 notifies the storage control unit 120 of the burst transfer length determined as described above. In the storage control unit 120, the burst transfer length (or burst transfer length and repetition count) received from the overall control unit 101 is set as the maximum transfer count of each of the data transfer circuits 110a to 110e (step S201 in FIG. 3).

  Here, when the image forming apparatus 100 starts operation, the memory arbitration circuit 121 starts arbitration (step S202 in FIG. 3). That is, the right to use the bus is granted by the memory arbitration circuit 121 by the round robin method or the like to the data transfer circuit 110x that is permitted to transfer data among the data transfer circuits 110a to 110e (step S203 in FIG. 3). .

  In the data transfer circuit 110x to which the right to use the bus is granted, the memory arbitration circuit 121 controls the data transfer circuit 110x until the number of data transfers reaches a predetermined maximum transfer number (NO in step S205 in FIG. 3). Data transfer is performed between them (step S204 in FIG. 3).

  When the data transfer circuit 110x to which the right to use the bus is granted has reached the maximum number of data transfers (YES in step S205 in FIG. 3), the memory arbitration circuit 121 corresponds to the data transfer circuit 110x. The data capacity stored in the buffer 120x to be checked is confirmed (step S206 in FIG. 3).

  If data corresponding to the transfer unit is accumulated in the buffer 120x (YES in step S206 in FIG. 3), the memory arbitration circuit 121 causes the data transfer circuit 110x to perform data transfer (step S204 in FIG. 3). ).

  If data corresponding to the transfer unit is not stored in the buffer 120x (NO in step S206 in FIG. 3), the memory arbitration circuit 121 considers that the data transfer of the data transfer circuit 110x has been completed, The data transfer circuit 110y is given a bus use right to perform data transfer (step S204 in FIG. 3). Thereafter, in the same manner, the memory arbitration circuit 121 performs arbitration, and repeatedly controls data transfer by assigning a bus use right to one of the data transfer circuits 110a to 110e by a round robin method or the like.

  A specific example (2) of the arbitration operation will be briefly described below. Here, the operation in the case where the end signal exists will be described with reference to the flowchart of FIG.

  First, the overall control unit 101 notifies the storage control unit 120 of the burst transfer length determined as described above. The storage control unit 120 sets the burst transfer length (or burst transfer length and number of repetitions) received from the overall control unit 101 as the maximum number of transfers of each data transfer circuit 110a to 110e (step S301 in FIG. 4).

  Here, when the image forming apparatus 100 starts operating, if it is not the final data of the burst transfer length set for the data transfer circuits 110a to 110e (NO in step S302 in FIG. 4), the data is transferred into the corresponding buffer 120x. Waiting for data corresponding to the unit to be accumulated (NO in step S303 in FIG. 4, YES in S302 and S303), the memory arbitration circuit 121 starts arbitration (step S304 in FIG. 4).

  If it is the final data of the set burst transfer length (YES in step S302 in FIG. 4), the memory arbitration circuit 121 starts arbitration even if the buffer capacity is not satisfied (in FIG. 4). Step S304).

  Here, the right to use the bus is granted to the data transfer circuit 110x that is permitted to transfer data among the data transfer circuits 110a to 110e by the memory arbitration circuit 121 that performs arbitration of the round robin method or the like (in FIG. 4). Step S305).

  In the data transfer circuit 110x to which the bus use right is given, the memory arbitration circuit 121 controls the memory transfer 130 until the number of data transfers determined by the burst transfer length is reached (step S302 in FIG. 4). Data transfer is performed (step S306 in FIG. 4).

  In addition, after the data transfer circuit 110x to which the bus use right is given performs the data transfer corresponding to the burst transfer length determined by the burst transfer length, the memory arbitration circuit 121 performs the data transfer circuit by the round robin method or the like. The right to use the bus is granted to the other data transfer circuits 110y in 110a to 110e (steps S304, S305, and S306 in FIG. 4). Thereafter, in the same manner, the memory arbitration circuit 121 performs arbitration, and repeatedly controls data transfer by assigning a bus use right to one of the data transfer circuits 110a to 110e by a round robin method or the like.

  Here, the relationship between the image rotation and the burst transfer length will be described with reference to FIG.

  The area (a) in FIG. 5 shows a part of the image data before rotation, and is divided into eight blocks 1 to 8 and processed. Here, each block is an aggregate of 8 × 8 pixels (N × N pixels) as shown in FIG.

  In this case, it is assumed that the burst transfer length X is X = 8 and the memory 130 capable of 8 burst (X burst) transfer is used. Here, the burst transfer length X means the amount of data when performing one burst transfer.

  Here, as shown in FIGS. 5A and 5B, 8 pixels (N pixels) in the row (vertical) direction are continuously transmitted by 8 column bursts (X = 8, X burst) transfer in the column (horizontal) direction. Read out once, rotated 90 ° by rearranging the pixels as shown in FIG. 5C, and then again transferred 8 pixels in the row direction to 8 columns in the column direction as shown in FIGS. 5C and 5D. Thus, the data is written in the memory 130 once in succession. As described above, by setting N × N pixels as a transfer target, it is possible to perform favorable processing even during image rotation.

  A case where the burst transfer length is further increased to increase the speed will be described with reference to FIG.

  In the case of FIG. 6 as well, each block is an aggregate of 8 × 8 pixels (N × N pixels), similar to that shown in FIG. In this case, description will be made assuming that the memory 130 capable of transferring 16 bursts (X = 8, 2X burst) is used.

  Here, 8 pixels in the row (vertical) direction are continuously read out by 16 column burst (2 × burst) transfer in the column (horizontal) direction as shown in FIG. 6A, and the pixels are arranged as shown in FIG. 6B. Rotate 90 ° by changing. However, as shown in FIG. 6C, since the positions of the blocks 1 and 2 after the image rotation are different from those before the rotation, writing of 8 columns burst transfer in the row (vertical) direction in the column (horizontal) direction is performed. It is written twice in the memory 130 repeatedly.

  In this case, at the time of reading in FIG. 6A, it can be performed at a high speed by 16 burst transfer with sequential access, but since the row (vertical) address after the rotation processing is different, at the time of writing in FIG. It becomes impossible to write, and high-speed processing cannot be realized even though the burst transfer amount is increased.

  As described above, if there is only one channel (data in the same color), it may not be efficient even if the burst transfer length is increased. Therefore, N at the same position of 4 channels of RGBA or 5 channels of YMCKA. A description will be given of increasing the burst transfer length with × N pixels as the transfer target.

  Here, as shown in FIG. 7, the case of C (cyan), M (magenta), Y (yellow), K (black), A (tag data), that is, the case of 5 channels is taken as a specific example. Further, as in FIG. 5 and FIG. 6, the description will be made with the number of block pixels N = 8, image data of 8 × 8 pixel block units as a specific example, and burst transfer length X = 8 as a specific example. Here, a specific example is given in which each color of YMCK is arranged in the order of CMYK.

  Here, FIG. 7A schematically shows a state of the memory 130 in which image data before and after rotation is stored, and C1 is a block of 8 × 8 pixels for cyan C (FIG. 7). (See (c)), M1 is an 8 × 8 pixel block at the same pixel position as C1 for magenta M, and Y1 is an 8 × 8 pixel block at the same pixel position as C1 and M1 for yellow Y. Yes, K1 is a block of 8 × 8 pixels at the same pixel position as C1, M1, Y1 for black K, and A1 is an 8 × 8 block at the same pixel position as C1, M1, Y1, K1 for tag data A. This is a block of 8 pixels.

  Here, for the 8 × 8 pixel block of C1, M1, Y1, K1, and A1, which are at the same pixel position, the image data for five channels is stored in the memory 130 with different column addresses adjacent to each other at the same row address. Write to. Therefore, the same applies to the next 8 × 8 pixel block C2, M2, Y2, K2, A2, and the subsequent pixels.

  When the image is rotated by 90 ° or 270 °, 8 × 8 pixels for 5 channels from the head position of the memory 130 to which writing has been performed are read out by 8 pixels · 8 × 5 burst transfer according to an instruction from the storage control unit 141. The read image data is rearranged for each channel and rotated within each 8 × 8 pixel (FIGS. 7C, 7D, and 7E).

  Then, the storage control unit 141 writes the rearranged image data for 5 channels in N × N pixel units (block units) to the memory 130 at different adjacent column addresses with the same row address. At this time, the data is written in an area (image area after rotation) different from the area (image area before rotation) read out earlier. At this time, the image data for five channels of CMYKA are sequentially written in the memory 130 with different column addresses adjacent to each other with the same row address, so that the efficiency is not lowered.

  That is, image data written to different adjacent column addresses with the same row address for 5 channels in units of N × N pixels is continuously read from the memory 130, and N × N pixels for each channel read from the memory 130 Each unit of image data is rotated, and the rotated image data for 5 channels in N × N pixel units are written continuously to different adjacent column addresses with the same row address in the memory 130. Continuous reading and writing with a large burst transfer length becomes possible, and when the memory 130 capable of burst transfer is used, data transfer at the time of executing the image rotation process can be performed efficiently. In other words, even if the pixel position is random access, sequential access is possible in the direction of multiple channels of the same pixel, so efficient data transfer is possible even if the burst transfer length is increased. .

  In this example, the case of 5 channels of CMYKA is taken as a specific example, but also in the case of 4 channels of RGBA and YMCK, efficient data transfer is possible by increasing the burst transfer length.

[Other Embodiments (1)]
In the above embodiment, the image forming apparatus 100 having a scanner and a print engine has been described as a specific example, but the present invention is not limited to this. For example, an image processing apparatus that does not include a scanner or print engine and performs efficient image rotation processing by burst transfer is also an aspect of an embodiment of the present invention.

[Other embodiment (2)]
In the above embodiment, an image processing apparatus and an image forming apparatus that perform color image formation are assumed. However, the present invention is not limited to this. For example, even in a monochrome image processing apparatus or image forming apparatus, when an image memory capable of burst transfer is used for two channels of image data and tag data, continuous reading and writing are performed by burst transfer. realizable.

DESCRIPTION OF SYMBOLS 100 Image forming apparatus 101 Overall control part 105 Operation part 110a-110e Data transfer circuit 120 Storage control part 121 Memory arbitration circuit 125 Memory controller 130 Memory

Claims (5)

A plurality of data transfer circuits for processing image data by performing at least one of input and output of image data;
A memory capable of continuous data transfer;
A bus connected to the memory;
An arbitration circuit that arbitrates bus use rights when using the memory in response to a request from the data transfer circuit;
A control unit;
An image processing apparatus comprising:
The control unit adjusts the burst transfer length, which means the number of continuous data transfers, so that the transfer band of the memory satisfies the total data transfer band required for each of the data transfer circuits. Later, each of the data transfer circuits is allocated to each data transfer circuit by adjusting the burst transfer length so as to satisfy the required data transfer bandwidth,
The arbitration circuit grants the right to use the bus according to a burst transfer length adjusted so that each of the data transfer circuits satisfies a necessary data transfer bandwidth.
An image processing apparatus. The arbitration circuit grants the bus use right according to the burst transfer length when the data transfer circuit performs sequential access to the memory.
The image processing apparatus according to claim 1. When the data transfer circuit performs random access to the memory, the arbitration circuit repeats continuous data transfer for a plurality of channels at the same position for N × N pixel unit image data a plurality of times. Perform bandwidth data transfer,
The image processing apparatus according to claim 1. Wherein the control unit, the burst transfer length in that vibration split to the respective data transfer circuit, fulfills the required bandwidth each data transfer circuit is a band of the required data transfer, split of the burst transfer length portion allocated bandwidth determined by the swing exceeds the required bandwidth is set to be smaller,
The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus. The image processing apparatus according to any one of claims 1 to 4,
An image forming unit that forms an image according to the image data processed by the image processing device;
An image forming apparatus.

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