JP2013239048A - Image process device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maximize a warranty value of a transfer rate in image process devices employing a split transaction bus.SOLUTION: An image process device according to the present invention includes: a bus right arbitration register that includes a plurality of hierarchized registers; and a bus arbiter that arbitrates a bus right with reference to the register. In each field of the register, at least one of a value indicative of a device and a value indicative of a lower hierarchy is stored, and a pointer of the register is cyclically shifted every time the register is referred to. The bus arbiter firstly refers to the uppermost hierarchy register and when a pointer of a reference destination indicates a hierarchy, refers to a register of the hierarchy. When the pointer of the reference destination indicates a device and the bus right is requested from the device, the bus arbiter gives the bus right to the device.

Description

  The present invention relates to an image processing apparatus.

  An image processing ASIC provided in an image processing apparatus such as a digital multi-function peripheral (MFP) is equipped with a plurality of devices, and the memory access of these devices competes. Each device issues a memory bus right request to the bus right arbitration means in the ASIC when memory access becomes necessary, and in response to this, the bus right arbitration means determines a predetermined priority. A bus right is granted to each device according to the order.

  On the other hand, in an image processing apparatus such as an MFP that requires high-speed and high-quality image formation, it is necessary to transfer a large amount of data within a predetermined cycle between devices involved in image processing. If not, an abnormal image is generated. In this regard, in recent years, there has been provided an image processing apparatus that employs a PCI Express (registered trademark) high-speed serial bus as an interface between devices that need to ensure a sufficient transfer rate.

  Here, for devices directly connected to image quality, such as a scanner data / plotter data input / output DMAC, it is necessary to guarantee a high transfer rate. Therefore, in bus arbitration, priority is given to these devices. Although the ranking is set high, the upper limit value of the total memory access rate is determined, and therefore the guaranteed transfer rate (worst value) must be extremely low.

  This problem becomes particularly serious in a device such as PCI Express (registered trademark) that employs a split transaction type bus in which a request command and a response to the request command are separated. In other words, in the split transaction type bus, if the request command is continuously issued at a high issue rate, the queue becomes full and a new request cannot be issued. If a sufficient margin is taken to absorb this variation, the transfer rate value that can be guaranteed becomes increasingly lower.

  In this regard, Japanese Patent Laid-Open No. 2007-249816 (Patent Document 1) constantly monitors the serial communication path of PCI Express (registered trademark) and dynamically arbitrates according to the amount of packet data actually transferred. A data communication circuit that can perform appropriate bus arbitration while maintaining the consistency of the actual traffic priority even if a transaction layer transmission buffer is present by changing the table Disclose.

  The present invention has been made in view of the above problems in the prior art, and the present invention employs a split transaction type bus in which a request command and a response to the request command are separated as in PCI Express (registered trademark). An object of the present invention is to maximize a guaranteed transfer rate in an image processing apparatus.

  As a result of intensive studies on a method for maximizing a guaranteed transfer rate in an image processing apparatus employing a split transaction type bus, the present inventor has conceived the following configuration and has reached the present invention.

  That is, according to the present invention, it includes a bus arbitration register including a plurality of hierarchized registers, and a bus arbiter that arbitrates the bus right with reference to the register, and each field of the register includes a device. At least one of the value indicated and the value indicating the hierarchy one level lower than the register hierarchy, the pointer of the register is cyclically shifted each time the register is referred to, and the bus arbiter is the first to If the value of the field indicated by the pointer of the reference destination is a value indicating the hierarchy, the register of the hierarchy indicated by the value is referred to by referring to the register of the reference destination When the value of the field indicated by the pointer is a value indicating the device and a bus right is requested from the device, the bus is sent to the device. The grant, an image processing apparatus is provided.

1 is a conceptual diagram of an image processing apparatus according to an embodiment. FIG. 3 is an internal block diagram of a controller ASIC installed in the image processing apparatus according to the present embodiment. The conceptual diagram which shows the structure of the register | resistor for bus right arbitration in this embodiment. The conceptual diagram for demonstrating the bus arbitration register | resistor in this embodiment. The conceptual diagram for demonstrating the bus arbitration register | resistor in this embodiment. The conceptual diagram for demonstrating the bus arbitration register | resistor in this embodiment. The figure which shows the mediation result by the bus arbiter in this embodiment. The conceptual diagram which shows the register for arbitration rate setting in this embodiment.

  Hereinafter, although this invention is demonstrated with embodiment, this invention is not limited to embodiment mentioned later. In the drawings referred to below, the same reference numerals are used for common elements, and the description thereof is omitted as appropriate.

  FIG. 1 is a conceptual diagram of an image processing apparatus 1000 according to an embodiment of the present invention. An image processing apparatus 1000 referred to as an MFP or the like includes a scanner unit 200 for reading a document, a plotter unit 300 for printing out image data, and an engine control for controlling the scanner unit 200 and the plotter unit 300. The ASIC 400 includes a controller ASIC 100, a CPU 500 for controlling the entire image processing apparatus 1000, and a memory 600 for storing various programs and data.

  The engine control ASIC 400 and the controller ASIC 100 are connected by a PCI Express standard high-speed serial bus 700 (hereinafter referred to as PCI Express 700), and the controller ASIC 100 and the CPU 500 are connected by a PCI Express standard high-speed serial bus 800. (Hereinafter referred to as PCI Express 800). On the other hand, the memory 600 is controlled by a memory controller (not shown) built in the CPU 500 and is interfaced with the SSTL standard.

  Here, first, the flow of data during copying in the image processing apparatus 1000 will be described. The image read by the scanner unit 200 is subjected to image processing in the engine control ASIC 400 and then passed to the controller ASIC 100. The controller ASIC 100 issues a request to store the processed image data in the memory 600 to the CPU 500, and the CPU 500 stores the corresponding image data in the memory 600 in response to the request.

  The image data stored in the memory 600 is read from the memory 600 in response to a request from the controller ASIC 100 and is passed to the plotter unit 300 via the engine control ASIC 400. The plotter unit 300 prints out the received image data.

  Next, a data flow when printer data is created in parallel with copying will be described. First, a printer output request (printer language data) is input to the controller ASIC 100 from the outside via a network or the like. The controller ASIC 100 issues a request to the CPU 500 to store the input printer language data in the memory 600, and the CPU 500 stores the corresponding printer language data in the memory 600 in response to the request. Thereafter, the CPU 500 interprets the printer language data and creates image data corresponding to the contents on the memory 600. At this time, the image data is created as compressed data using a compressor mounted on the controller ASIC 100 in order to suppress consumption of memory capacity.

  When the plotter unit 300 is released from the print output process for copying, the image data (compressed data) stored in the memory 600 is read from the memory 600 in response to a request from the controller ASIC 100. The read image data (compressed data) is subjected to decompression processing by the decompressor of the engine control ASIC 400 and then delivered to the plotter unit 300. The plotter unit 300 prints out the received image data.

  FIG. 2 is an internal block diagram of the controller ASIC 100 mounted on the image processing apparatus 1000 according to the present embodiment. The controller ASIC 100 is prepared for each color of process colors (CMYK), a PCI Express route controller 102 that controls the PCI Express 700 on the engine control ASIC 400 side, a PCI Express endpoint controller 104 that controls the PCI Express 800 on the CPU 500 side, and so on. To control the four video output control units 110a, 110b, 110c, and 110d, the four image processing units 120a, 120b, 120c, and 120d, the compression unit 130, the line buffer 140 for scanner data, and the line buffer 140 Video input controller 150, bus arbiter 160, and overall controller 170 for controlling the entire controller ASIC 100.

  Each of the video output control units 110a to 110d includes a video output controller, a stamp DMAC, and a video output DMAC. In FIG. 2, the video output controller, the stamp DMAC, and the video output DMAC are denoted as Vout, Stp DMAC, and Vout DMAC, respectively.

  The video output controller (Vout) controls the entire video output control unit 110 and executes processing for sending plotter data to the engine control ASIC 400. The video output DMAC is a direct memory access controller (DMAC) for preparing plotter data to be printed out. The stamp DMAC (Stp DMAC) prepares stamp print data to be superimposed on the plotter data to be printed out. DMAC.

  Each of the image processing units 120a to 120d includes an image processing controller and two general-purpose DMACs. In FIG. 2, the image processing controller and the general-purpose DMAC are denoted as IMP and GDMAC, respectively. To explain based on the image processing unit 120a, the image processing controller (IMP_0) reads out data by the general purpose DMAC (GDMAC10) and executes image processing, and the execution result is stored in the memory 600 by another general purpose DMAC (GDMAC11). Write.

  The compression unit 130 includes a compressor and two general-purpose DMACs. In FIG. 2, the compressor and the general-purpose DMAC are denoted as ENC_0, GDMAC_00, and GDMAC_01, respectively. The compressor (ENC_0) reads the raw data with the general-purpose DMAC (GDMAC_00) and writes the compression result into the memory 600 with the general-purpose DMAC (GDMAC_01).

  The line buffer 140 can store a plurality of lines of scanner data, and the video input controller 150 controls the line buffer 140. In FIG. 2, the line buffer 140 and the video input controller 150 are denoted as Line Buff and VIcnt, respectively.

  The bus arbiter 160 is a bus arbitration unit, and executes arbitration of memory access requests issued to the CPU 500 from each of the video output control units 110a to 110d, the image processing units 120a to 120d, and the compression unit 130. Here, the overall controller 170 includes a control register 172, and the CPU 500 is configured to be able to set a predetermined value in the control register 172. The overall controller 170 controls the bus arbiter 160 based on the set value relating to the arbitration condition set in the control register 172.

  Next, the contents of the bus arbitration executed by the bus arbiter 160 of the controller ASIC 100 will be described based on a specific example.

  In this embodiment, the bus arbiter 160 refers to the bus arbitration register and executes the bus arbitration. FIG. 3 is a conceptual diagram showing the configuration of a new bus arbitration register employed by the present embodiment. The bus arbitration register illustrated in FIG. 3 includes five registers. Each field of the register stores at least one of a value indicating a device requesting the bus right from the bus arbiter 160 and a value indicating a hierarchy one level lower than the hierarchy of the register, and the remaining fields store no operation instructions. (Hereinafter referred to as NOP) is stored.

  In the present embodiment, four of the five registers are used as basic setting registers and are hierarchized in four stages. Of the five registers, two registers are hierarchized in two stages and function as substitute destination determination registers. A value indicating a device is set in a register in a hierarchy corresponding to the priority of the device. In FIG. 3, “VIcnt” indicates the video input controller 150, “Vout_0 to 3” indicates four video output DMACs, “Stp_0 to 3” indicates four stamp DMACs, and “G00˜ "G41" indicates 10 general-purpose DMACs (hereinafter the same in other figures).

  In the first layer of the basic setting register, “VIcnt” indicating the request source device and “2nd” indicating the reference of the second layer are set in order from the top, and no operation instruction (in the remaining 11 fields) NOP) is set.

  In the second layer of the basic setting register, “Vout_0”, “Vout_1”, “Vout_2”, and “Vout_3” indicating the request source device are set in order from the top, followed by “3” indicating the third layer. “3rd” is set four times in succession, and NOP is set in the remaining five fields.

  “Stp_0”, “Stp_1”, “Stp_2”, and “Stp_3” indicating the requesting device are set in the third layer of the basic setting register in order from the top, followed by reference to the fourth layer. “4th” shown is set twice in succession, and NOP is set in the remaining seven fields.

  In the fourth layer register, “Vout_0”, “Vout_1”, “Vout_2”, “Vout_3”, “Stp_0”, “Stp_1”, “Stp_2”, “Stp_3”, “Stp_3”, “Stp_3” VIcnt "is set, and NOP is set in the remaining four fields.

  In the basic setting register, a value indicating a device with the highest priority is set in the highest hierarchy, and a value indicating a device with a lower priority is set as the hierarchy goes down. In the case of the example shown in FIG. 3, the video input controller 150 “VIcnt” that needs to guarantee the worst value of the transfer rate in order to prevent abnormal images is set in the first layer, Next to the input controller 150 “VIcnt”, the video output DMAC “Vout_0 to 3” which must guarantee the transfer rate is set.

  Note that the above-described fourth layer register also functions as the first layer of the replacement destination determination register at the same time, and the second layer register of the replacement destination determination register has a request source in order from the top. Devices “G00”, “G01”, “G10”, “G11”, “G20”, “G21”, “G30”, “G31”, “G40”, “G41” are set, and the remaining three fields NOP is set in

  In the initial state, the pointers of the registers constituting the bus arbitration register are set at the head position (left end) as shown in FIG. The bus arbiter 160 determines the value indicated by the register pointer, and grants the bus right to the device indicated by the value. The register pointer is cyclically shifted each time the register is referenced by the bus arbiter 160. That is, the register pointer shifts to the right every time the register is referred to by the bus arbiter 160. When the pointer reaches the right end of the register or when the next shift destination is NOP, the position of the pointer is changed. It is configured to shift to the top position (left end) of the register. Hereinafter, the bus arbitration process executed by the bus arbiter 160 using the bus arbitration register shown in FIG. 3 will be described in detail.

  The bus arbiter 160 refers to the highest hierarchy (that is, the first hierarchy) first and determines the value indicated by the pointer when determining where to grant the bus right. In the initial state shown in FIG. 3, the pointer of the first layer points to “VIcnt”. In this case, the bus arbiter 160 determines whether or not a bus right request is issued from “VIcnt”. If a bus right request is issued from “VIcnt”, a predetermined allocation period set in advance is determined. The bus right is granted to “VIcnt” for (t).

  Thereafter, in synchronization with the end of the predetermined allocation period (t), the pointer of the first layer is shifted to “2nd” as shown in FIG. The bus arbiter 160 again determines the value indicated by the first layer pointer. In the state shown in FIG. 4A, since the pointer of the first hierarchy points to “2nd”, the bus arbiter 160 refers to the second hierarchy down the hierarchy and determines the value indicated by the pointer. . At this time, the pointer in the second hierarchy points to “Vout_0”. In this case, the bus arbiter 160 determines whether or not a bus right request has been issued from “Vout_0”. If a bus right request has been issued from “Vout_0”, the bus arbiter 160 has a predetermined allocation period (t). Grant the bus right to “Vout_0”.

  Thereafter, in synchronization with the end of the allocation period (t), as shown in FIG. 4B, the pointer of the first layer shifts to “VIcnt” and at the same time, the pointer of the second layer shifts by one to the right. (That is, shift from “Vout — 0” to “Vout — 1”). The bus arbiter 160 again determines the value indicated by the first layer pointer. In the state shown in FIG. 4B, since the pointer in the first layer points to “VIcnt”, the bus arbiter 160 determines whether a bus right request is issued from “VIcnt”. When a bus right request is issued from “VIcnt”, the bus right is granted to “VIcnt” for a predetermined allocation period (t).

  Thereafter, in synchronization with the end of the allocation period (t), as shown in FIG. 4C, the first layer pointer is shifted to “2nd”. The bus arbiter 160 again refers to the first hierarchy and determines the value indicated by the pointer. In the state shown in FIG. 4C, since the pointer of the first hierarchy points to “2nd”, the bus arbiter 160 refers to the second hierarchy down the hierarchy and determines the value indicated by the pointer. . At this time, the pointer in the second hierarchy points to “Vout — 1”. In this case, the bus arbiter 160 determines whether or not a bus right request is issued from “Vout_1”. If a bus right request is issued from “Vout_1”, the bus arbiter 160 extends over a predetermined allocation period (t). Grant the bus right to “Vout_1”.

  Thereafter, the pointers in the first and second hierarchies are shifted in a manner as shown in FIGS. 4D, 4E, 5F, and 5G. Each time, the bus arbiter 160 determines whether a bus right request is issued from each of “VIcnt”, “Vout_2”, “VIcnt”, “Vout_3”, and the bus right request is issued from each device. If it is, the bus right is granted in the order of “VIcnt” → “Vout_2” → “VIcnt” → “Vout_3”.

  Here, the allocation period (t) is a parameter for determining the transfer rate. It is assumed that a transfer of 128 bytes is performed in one arbitration, and a transfer rate of 200 MB / s is guaranteed with the setting for one frame in the first hierarchy. For this purpose, the allocation period (t) ≧ 128 / (200 * 1024 * 1024) = 610 ns may be set.

  Subsequently, as shown in FIG. 5 (h), the pointer of the first layer is shifted to “VIcnt”, and at the same time, the pointer of the second layer is shifted by one to the right (that is, from “Vout_3” to “3rd”). shift). Then, the bus arbiter 160 refers to the first hierarchy again and determines the value indicated by the pointer. In the state shown in FIG. 5H, the first layer pointer points to “VIcnt”. Therefore, it is determined whether or not a bus right request is issued from “VIcnt”. When a bus right request is issued, the bus right is granted to “Vout — 1” over a predetermined allocation period (t).

  Subsequently, as shown in FIG. 5I, the pointer in the first layer is shifted to “2nd”. The bus arbiter 160 again refers to the first hierarchy and determines the value indicated by the pointer. In the state shown in FIG. 5I, the pointer of the first hierarchy points to “2nd”, so the bus arbiter 160 refers to the second hierarchy down the hierarchy and determines the value indicated by the pointer. . At this time, the pointer in the second hierarchy points to “3rd”. The bus arbiter 160 further descends the hierarchy, refers to the third hierarchy, and determines the value indicated by the pointer. At this time, since the third layer pointer points to “Stp_0”, it is determined whether the bus right request is issued from “Stp_0”, and the bus right request is issued from “Stp_0”. If so, a bus right is granted to “Stp_0” over a predetermined allocation period (t).

  Thereafter, similarly, the registers in the first to third layers repeat the sequential shift, and after going through the state shown in FIG. 6 (j), the state shown in FIG. 6 (k) is reached. At this time, the bus arbiter 160 refers to the first hierarchy again and determines the value indicated by the pointer. In the state shown in FIG. 6 (k), since the pointer of the first hierarchy points to “2nd”, the bus arbiter 160 refers to the second hierarchy down the hierarchy and determines the value indicated by the pointer. . At this time, since the pointer of the second hierarchy points to “3rd”, the bus arbiter 160 further descends the hierarchy, refers to the third hierarchy, and determines the value indicated by the pointer. At this time, since the pointer of the third hierarchy points to “4th”, the bus arbiter 160 further goes down the hierarchy, refers to the fourth hierarchy, and determines the value indicated by the pointer. At this time, since the pointer in the fourth layer points to “Vout_0”, the bus arbiter 160 determines whether or not a bus right request is issued from “Vout_0”, and the bus right request from “Vout_0”. Is issued, a bus right is granted to “Vout — 0” over a predetermined allocation period (t). Thereafter, the same arbitration process is repeated.

  FIG. 7 illustrates an arbitration result by the bus arbiter 160. In FIG. 7, the devices to which the bus arbiter 160 has given the bus right are shown in time series. As described with reference to FIG. 3 to FIG. 6, after 17 arbitrations from the initial state, “VIcnt” → “Vout_0” → “VIcnt” → “Vout_1” → “VIcnt” → “Vout_2” → “VIcnt → Vout_3 → VIcnt → Stp_0 → VIcnt → Stp_1 → VIcnt → Stp_2 → VIcnt → Stp_3 → VIcnt → Vout_0 (Fig. 6 (k The bus right is granted in the order of the status shown in ()). Thereafter, the bus right arbitration is executed in the same procedure, and as a result, the bus right is given to each device in the order shown in FIG.

  So far, the case where the request for the bus right is issued from the device indicated by the pointer of each layer has been described, but in reality, the request for the bus right is not necessarily issued from the device indicated by the pointer. Is not limited. In this regard, when the bus arbiter 160 in this embodiment determines that the bus right request is not issued from the device indicated by the pointer, the bus arbiter 160 refers to the substitution destination determination register and determines the value indicated by the pointer.

  For example, in the initial state shown in FIG. 3, the first layer pointer points to “VIcnt”, so the bus arbiter 160 determines whether a bus right request is issued from “VIcnt”. As a result, when it is determined that the bus right request is not issued from “VIcnt”, the bus arbiter 160 refers to the first layer of the substitution destination determination register and determines the value indicated by the pointer. In this case, since the first layer pointer of the substitution destination determination register points to “Vout_0”, the bus arbiter 160 determines whether or not a bus right request is issued from “Vout_0”, and “Vout_0” When the request for the bus right is issued from “,” the bus right is granted to “Vout — 0” over a predetermined allocation period (t). When the bus right is given to “Vout_0”, the pointer of the first layer of the substitution destination determination register is shifted from “Vout_0” to “Vout_1”.

  On the other hand, if it is determined that a bus right request has not been issued from “Vout — 0”, the bus arbiter 160 refers to the second hierarchy of the substitution destination determination register and determines the value indicated by the pointer. In this case, since the pointer in the second layer of the substitution destination determination register points to “G00”, the bus arbiter 160 determines whether or not a request for the bus right is issued from “G00”. When the request for the bus right is issued from “”, the bus right is granted to “G00” for a predetermined allocation period (t). When the bus right is given to “G00”, the pointer of the second layer of the substitution destination determination register is shifted from “G00” to “G01”.

  As described above, the bus arbitration executed by the bus arbiter 160 in the present embodiment has been described by taking as an example a mode in which read access and write access are arbitrated using one bus arbitration register. Then, a register for read access and a register for write access may be prepared separately, and the memory access may be arbitrated based on the OR result of two arbitration results using each register. .

  Finally, the arbitration rate setting register will be described. As described in FIG. 2, the overall controller 170 mounted on the controller ASIC 100 includes the control register 172, and the control register 172 includes an arbitration rate setting register. The value of the arbitration rate setting register is set by the CPU 500, and the overall controller 170 sets a bus arbitration register used by the bus arbiter 160 based on the value set in the arbitration rate setting register.

  FIG. 8A is a diagram conceptually illustrating an arbitration rate setting register. The arbitration rate setting register shown in FIG. 8A includes, for each device, a “hierarchy” of a basic setting register in which a value indicating the device is stored, and a “value” indicating the device in the hierarchy (register). A first register for setting the “number of times of storage” and a second register for setting the “number of times of storage” of a value indicating a hierarchy one level lower than the hierarchy for each level Consists of including.

  In the first register illustrated in FIG. 8A, “VIcnt” is stored once in the first layer, and each of “Vout_0”, “Vout_1”, “Vout_2”, and “Vout_3” is stored in the second layer. It is set to store twice, and each of “Stp_0”, “Stp_1”, “Stp_2”, and “Stp_3” is stored once in the third hierarchy. On the other hand, for the other devices (G00 to G41), the hierarchy is set to “0”, which means that the value indicating the device (G00 to G41) is not stored in the first to third hierarchies. doing.

  Further, the second register illustrated in FIG. 8A stores a value indicating a lower hierarchy with respect to the first hierarchy once, and stores a value indicating the lower hierarchy with respect to the second hierarchy four times. Stored and set to store a value indicating a lower hierarchy twice with respect to the third hierarchy.

  The overall controller 170 sets a bus arbitration register used by the bus arbiter 160 based on the value of the arbitration rate setting register (first and second registers) shown in FIG. When the value of the arbitration rate setting register is set as shown in FIG. 8A, the overall controller 170 generates a bus arbitration register having the hierarchical structure shown in FIG. 8B.

  As described above, according to the present embodiment, since the dispersion in the negative direction of the arbitration result is automatically eliminated, the guaranteed rate of the request source that must guarantee the worst value of the transfer rate is maximized. can do. In addition, according to the present embodiment, when there is a DMAC that does not need to participate in the bus arbitration due to reasons such as suspension, the allocation period to the DMAC is automatically allocated to another DMAC. Variation in the positive direction (ensuring a transfer rate higher than the scheduled transfer rate) can be generated. Furthermore, according to the present embodiment, it is possible to easily set the arbitration rate using a dedicated register.

  As described above, the present invention has been described with the embodiment. However, the present invention is not limited to the above-described embodiment, and as long as the operations and effects of the present invention are exhibited within the scope of embodiments that can be considered by those skilled in the art. It is included in the scope of the present invention.

100 ... Controller ASIC
DESCRIPTION OF SYMBOLS 102 ... Route controller 104 ... Endpoint controller 110 ... Video output control unit 120 ... Image processing unit 130 ... Compression unit 140 ... Line buffer 150 ... Video input controller 160 ... Bus arbiter 170 ... Overall controller 172 ... Control register 200 ... Scanner unit 300 ... Plotter unit 400 ... ASIC for engine control
500 ... CPU
600 ... Memory 700, 800 ... High-speed serial bus 1000 ... Image processing device

JP 2007-249816 A

Claims (7)

A bus arbitration register including a plurality of hierarchized registers;
A bus arbiter that refers to the register and arbitrates the bus right,
Each field of the register stores at least one of a value indicating a device and a value indicating a hierarchy one level lower than the hierarchy of the register,
The register pointer is cyclically shifted each time the register is referenced,
The bus arbiter is
First refer to the register at the highest level,
When the value of the field indicated by the pointer of the register of the reference destination is a value indicating the hierarchy, the register of the hierarchy indicated by the value is referred to.
When the value of the field indicated by the pointer of the register to be referred to is a value indicating the device, and when the bus right is requested from the device, the bus right is granted to the device.
Image processing device.   The image processing apparatus according to claim 1, wherein the bus right is a spirit right of a spirit transaction type bus.   The image processing apparatus according to claim 2, wherein the spirit transaction type bus is a PCI Express standard serial bus. The bus arbitration register includes an alternative destination determination register,
The bus arbiter is
When the value of the field indicated by the pointer of the register at the reference destination is a value indicating the device and there is no bus right request from the device, a bus is sent to the device indicated by the pointer of the substitution destination determination register. The image processing apparatus according to claim 1, wherein the right is granted.   The image processing apparatus according to claim 1, wherein the bus arbitration register includes a read access register and a write access register separately. For each of the devices, an arbitration rate setting register comprising a first register for setting a hierarchy of the registers in which a value indicating the device is stored and the number of times of storage in the register is set;
The image processing apparatus according to claim 1, wherein the bus arbitration register is generated based on contents set in the first register. The arbitration rate setting register further includes a second register for setting, for each of the hierarchies, the number of times a value indicating a hierarchy one level lower than the hierarchy is stored in the hierarchy register.
The image processing apparatus according to claim 6, wherein the bus arbitration register is generated based on contents set in the first register and the second register.