JP2006145665A - Image forming controller device and printer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image forming controller device and a printer device capable of efficiently performing memory access in accordance with the number of colors composing image data to be processed; DMACs (203, 205 and 603) respectively switch a master ID issued in accordance with the format of the image data set in image format registers (303, 307 and 702); and a memory controller 106 determines a memory access command issued to a RAM part 112 according to the master ID received together with a memory access requirement. <P>SOLUTION: The DMACs (203, 205 and 603) respectively switch the master ID issued in accordance with the format of the image data set in the image format registers (303, 307 and 702). The memory controller 106 determines the memory access command issued to the RAM part 112 according to the master ID received together with the memory access requirement. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming controller device that can be connected to an image forming engine to constitute an image forming device, and a printer device that includes the image forming controller device and the image forming engine. The present invention relates to an image forming controller device and a printer device capable of performing the above.

  With the rapid development of information communication technology, information devices such as personal computers are widely used for both office use and home use. In addition, with the widespread use of such devices, the demand for printer devices as output devices is also increasing. In particular, in recent years, an ink jet printer apparatus that discharges fine ink droplets of a plurality of colors to form an image on a recording medium has advanced, and a printer apparatus that can output a high-definition color image such as a color photograph. In addition, printer apparatuses capable of outputting to a large recording medium having an A0 width or a B0 width have been developed.

  Such a printer device includes an image forming controller device that performs image processing and an image forming engine (printer engine, printing mechanism) that performs printing processing. The image forming controller device receives image data for printing from a host device such as a connected personal computer, performs image processing for converting the received data into a data format that can be printed by the image forming engine, The converted data is sent to the image forming engine for printing. At this time, the image data received from the host device and the output data after the image processing are temporarily stored in a memory element in the image forming controller device.

  These data stored in the memory elements have increased in data capacity compared to the past due to higher definition of printed images and larger output paper sizes, and higher speeds due to higher functionality of the image forming engine. Memory access is becoming necessary. In view of these requirements, a synchronous DRAM (SDRAM) that inputs and outputs data in synchronization with a clock signal is widely used as a memory element mounted on an image forming controller device.

  In the synchronous DRAM, as shown in FIG. 10, a large number of storage elements are arranged in a two-dimensional lattice, and a storage element to be accessed is specified by a set of a row address and a column address input from the outside. FIG. 10 shows a state where the storage elements shown by shading are specified.

  Data input / output to / from the synchronous DRAM is performed by issuing the following command. In the synchronous DRAM, (A) an ACTIVE command that designates and activates a column address, (B) a READ command that designates row address designation and data output, and (C) a row address designation and data storage instruction WRITE command to perform, (D) PRE command to perform deactivation (precharge), (E) READA command to automatically perform precharge after data output and data output, and (F) row address There is a command such as a WRITEA command that automatically precharges after specification and data storage and data storage. In addition, the synchronous DRAM includes a REFRESH command for instructing refresh.

  Reading data from the synchronous DRAM can be realized by (1) designating a column address using the ACTIVE command and (2) designating a row address using the READ command and outputting the data. Data writing to the synchronous DRAM can be realized by (1) ACTIVE command (column address designation) and (2) WRITE command (row address designation and data input). At this time, when the storage elements corresponding to the same column address are continuously accessed as in the storage elements indicated by hatching in FIG. 10, the ACTIVE command of (1) is used in the second or subsequent reading or writing. Can be omitted, and the next READ command or WRITE command can be issued following the previous READ command or WRITE command. Therefore, the synchronous DRAM is characterized in that high-speed memory access is possible when continuously accessing storage elements on the same column address.

  On the other hand, when accessing a storage element at a column address different from the previous memory access, the PRE command is issued and deactivated, then the ACTIVE command is issued to activate the column address, and READ or WRITE is performed. Will be executed. That is, following (1) and (2) above, (3) deactivation is instructed by the PRE command, (4) a different column address is designated by the ACTIVE command, and (5) by the READ command or WRITE command. Read or write data.

  Therefore, if the READ command and the WRITE command are used when consecutively accessing different column addresses, it is necessary to issue the command sequence shown in FIG. In the case of such a memory access, when the READA command and the WRITEA command for automatically precharging are used, the same access can be realized by issuing the command sequence shown in FIG. That is, since the issue of the PRE command can be omitted, the access speed can be improved as compared with the case where the READ command and the WRITE command are used.

As image data handled by the image forming controller device, for example, data for four colors of cyan (C), magenta (M), yellow (Y), and black (K) are stored on the synchronous DRAM as shown in FIG. . At this time, when data is read from the memory for image processing, when data is read for transferring data to the image forming engine, or when output data subjected to image processing is written to the memory, FIG. Since the access is made in the order of the symbols (1), (2), (3),. It is generally known that (See Patent Document 1)
Japanese Patent Laid-Open No. 10-39569

  However, in the image forming controller that performs memory access using the above-mentioned READA command and WRITEA command, an inefficient memory may be used depending on the format of image data to be handled when reading image data from the memory element or writing image data to the memory element. There was a problem of access.

  For example, when processing monochrome image data such as monochrome printing, the image data is stored on the memory element as shown in FIG. In this case, since reading and writing of image data is continuous access to storage elements on the same column address, memory access by the READA command and the WRITEA command continues the READ command and the WRITE command without executing the PRE command. Therefore, the time required for memory access is increased as compared with the case where it is automatically performed.

  Therefore, the present invention has been made in view of the above-described problems of the conventional example. The number of colors of image data processed by the image forming controller device is detected. When the image data is composed of a single color, the synchronization is a memory element. Format of image data to be processed by performing memory access to the DRAM by the READ command and the WRITE command, and when the image data is composed of multiple colors, by performing memory access to the synchronous DRAM by the READA command and the WRITEA command Accordingly, an object of the present invention is to provide an image forming controller device capable of executing efficient memory access with a simple configuration.

  In order to achieve the above object, in the image forming controller device according to claim 1, in the image forming controller device that performs image processing on the input image data to generate and output the image forming data, the image forming controller device is connected to the connected memory element. A memory controller that can issue at least two memory access commands of one memory access command and a second memory access command; and one or more DMA controllers that request the memory controller to issue a memory access command; Image data color number detection means for determining whether the image data is composed of a single color or multiple colors, and when the DMA controller requests the memory controller to issue a memory access command, the image data The data color number detection means When it is determined that the memory controller issues the first memory access command to the memory element, and when it is determined that the image data is multicolor image data, the memory controller Memory access control means for controlling to issue a second memory access command is provided.

  In order to achieve the above object, according to a second aspect of the present invention, in the image forming controller device according to the first aspect, one or a plurality of DMA controllers designated in advance among the plurality of DMA controllers. The memory access control unit controls the memory access request, and the memory controller responds to the first memory access command or the second memory in response to a memory access request of a DMA controller other than the designated DMA controller. Only one of the access commands is issued.

  In order to achieve the above object, in the image forming controller device according to claim 3, in the image forming controller device according to claim 1 or 2, the memory access command uses the data stored in the memory element. It is a memory read command to be read.

  In order to achieve the above object, in the image forming controller device according to claim 4, in the image forming controller device according to claim 1 or 2, the memory access command is a memory write for writing data to the memory element. It is a command.

  In order to achieve the above object, according to a fifth aspect of the present invention, in the image forming controller device according to any one of the first to fourth aspects, the combination of a row address and a column address is used. The memory controller has a function of specifying a storage element to be accessed and controlling a synchronous DRAM that inputs and outputs a command in synchronization with an input clock signal.

  In order to achieve the above object, in the image forming controller device according to claim 6, in the image forming controller device according to claim 5, the first memory read command instructs reading without auto-precharge of the synchronous DRAM. The second memory read command is a READA command for instructing a read operation with auto precharge of the synchronous DRAM.

  In order to achieve the above object, in the image forming controller device according to claim 7, in the image forming controller device according to claim 5, the first memory write command indicates writing without auto-precharge of the synchronous DRAM. The second memory write command is a WRITEA command for instructing a write with auto precharge of the synchronous DRAM.

  In order to achieve the above object, in the image forming controller device according to claim 8, in the image forming controller device according to any one of claims 1 to 7, the DMA controller is connected to a memory controller. A unique master ID is issued to each of the DMA controllers together with a memory access command issue request.

  In order to achieve the above object, in the image forming controller device according to claim 9, in the image forming controller device according to claim 8, the image data is constituted by a single color in one or a plurality of the DMA controllers. The master ID issued in this case is different from the master ID issued when the image data is composed of multiple colors.

  In order to achieve the above object, in the image forming controller device according to claim 10, in the image forming controller device according to claim 9, the image data color number detection means is configured such that the DMA controller issues a memory access command. It is characterized in that it is determined whether the image data is composed of a single color or multiple colors based on the master ID issued together with the request.

  In order to achieve the above object, in the image forming controller device according to claim 11, image data representing a configuration of image data in the image forming controller device according to any one of claims 1 to 10. A register for storing format information is provided.

  In order to achieve the above object, in the image forming controller device according to claim 12, in the image forming controller device according to claim 11, the color number detecting means is based on image data format information stored in the register. It is determined whether the image data is composed of a single color or multiple colors.

  In order to achieve the above object, in a printer apparatus according to claim 13, a printer apparatus having an image formation controller device and an image formation engine that performs printing based on image formation data output from the image formation controller device. A memory controller capable of issuing at least two memory access commands, ie, a first memory access command and a second memory access command, to the connected memory element; and a memory for the memory controller. One or a plurality of DMA controllers that request issuance of access commands, image data color number detection means for determining whether image data is composed of a single color or multicolors, and the DMA controller is the memory controller Memory access When the image data color number detecting means determines that the image data is monochrome image data, the memory controller issues a first memory access command to the memory element, And a memory access control means for controlling the memory controller to issue the second memory access command to the memory element when the image data is determined to be the image data.

  As described above in detail, according to the present invention, when the image data to be processed is composed of a single color, the synchronous DRAM is accessed by the READ command and the WRITE command, and the image data is composed of multiple colors. By accessing the synchronous DRAM with the READA command and the WRITEA command, it is possible to perform an efficient memory access according to the format of the image data.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments when the present invention is applied to an image forming controller device of a printer device will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an image forming controller apparatus according to the present embodiment. The image forming controller device provides a function of receiving printing data from a host device such as a personal computer, converting the received data into data having a configuration printable by a printer engine, and outputting the data.

  Reference numeral 100 in the drawing denotes an image forming controller device, which includes a CPU 101, an image processing unit 102, a printer engine interface unit 103, a communication interface unit 104, an external bus circuit unit 105, and a memory controller 106. The bus lines 108a to 108f are connected to the system bus bridge 107, respectively. In this embodiment, these blocks are realized as an image forming controller ASIC 109 sealed in one package as a system LSI.

  In addition to the image forming controller ASIC 109, the image forming controller device 100 includes an expansion slot 110 and a RAM unit 112 for connecting a function expansion unit.

  In addition, the image forming controller device 100 includes a ROM unit, an operation unit, a display unit, and the like (not shown).

  The CPU 101 is responsible for overall control of the image forming controller device 100, and sequentially reads and executes control procedures (programs) stored in a ROM unit or RAM unit 112 (not shown), thereby communicating for communication with the host device. Control of the interface unit 104, interpretation of the communication protocol, control of the image processing unit 102 for converting image data received from the host device into data having a configuration printable by the printer engine, and image formation generated by the image processing unit 102 Control of the printer engine interface unit 103 for transferring data to the printer engine is performed.

  The image processing unit 102 has a function of converting print data received from the host device into output image data that can be printed by the printer engine.

  The printer engine interface unit 103 has a function of transmitting and receiving data between the image forming controller device 100 and the printer engine.

  The detailed configurations of the image processing unit 102 and the printer engine interface unit 103 will be described later with reference to the drawings.

  The communication interface unit 104 has a function of transmitting / receiving data to / from a host device such as a personal computer or a workstation, and a function of storing print data received from the host device in the RAM unit 112 via the memory controller 106. It has. The communication method of the communication interface unit 104 may be any method such as high-speed serial communication such as USB or IEEE 1394, parallel communication such as IEEE 1284, or network communication such as 100BASE-TX. You may have a method. Further, the present invention is not limited to a wired communication system, and a wireless communication system is also included.

  The expansion bus circuit unit 105 has a function of controlling the function expansion unit installed in the expansion slot 110, and controls to transmit data to the function expansion unit via the expansion bus 111 and to receive data output from the function expansion unit. I do. As the function expansion unit mounted in the expansion slot, a communication unit that provides a communication function with a host device such as USB, IEEE 1394, IEEE 1284, or network communication, a hard disk drive unit that provides a large capacity storage function, or the like can be mounted. .

  Each block of the image processing unit 102, the printer engine interface unit 103, the communication interface unit 104, and the external bus circuit unit 105 has a DMAC (Direct Memory Access Controller) and issues a memory access request. It has. The DMAC of each block has a function of issuing a master ID unique to each block together with a memory access request when issuing a memory access request, and the memory controller 106 and the system bus bridge 107 use the master ID to issue a memory access request. Can be identified.

  The memory controller 106 has a function of controlling the RAM unit 112 connected via the memory bus 113. The memory controller 106 generates necessary control signals from each block having the CPU 101 and the DMAC via the system bus bridge 107 in response to a write request to the RAM unit 112 or a read request from the RAM unit 112, and the RAM unit 112. Data is written to and read from the RAM unit 112, and data is relayed between the CPU 101 and each block.

  When the RAM unit 112 is configured by a synchronous DRAM such as a DDR (Double Data Rate) type SDRAM or an SDR (Single Data Rate) type SDRAM, the memory controller 106 receives two types of commands, READ command and READA command, as data read. A function to issue is provided, and a command to be issued can be selectively switched according to the number of colors of the processed image. Similarly, the memory controller 106 can select and issue two types of commands, a WRITE command and a WRITEA command, as data write commands.

  The system bus bridge 107 has a function of connecting blocks constituting the image forming controller ASIC 109, and also has a function of arbitrating a bus right when an access request is issued simultaneously from a plurality of blocks. Each block having the CPU 101 and the DMAC may issue an access request to the RAM unit 112 via the memory controller 106 at the same time, and the system bus bridge 107 can appropriately perform arbitration according to a priority specified in advance. .

  The RAM unit 112 is composed of a synchronous DRAM or the like, stores control procedures executed by the CPU 101, temporarily stores output data converted by the image processing circuit unit 102, and prints received from the host device by the communication interface unit 104. This is a memory block that provides functions such as temporary buffering of data for use, temporary storage of data exchanged with a function expansion unit connected via the external bus 111, and work memory of the CPU 101.

  Note that the data bus width of the bus lines 108a to 108f of the image forming controller device according to the present embodiment is 256 bits, and the data bus width of the memory bus 113 is 64 bits.

  Next, an image processing unit of the image forming controller apparatus according to the present embodiment will be described with reference to the drawings.

  FIG. 2 is a block diagram illustrating a configuration of an image processing unit of the image forming controller device. The image processing unit 102 is roughly composed of a register unit 201, a control circuit 202, a read DMAC 203, an image processing circuit 204, and a write DMAC 205.

  As shown in FIG. 3, the register unit 201 designates the image processing start register 301 for instructing the start of image processing, the command / parameter register 302 for designating the contents and parameters of the image processing to be executed, and the format of the image data to be image processed. Input image format register 303, input line length register 304 for designating the length (number of pixels) of image data to be processed, input memory address register 305 for designating the start address of a memory area in which image data is stored, and RAM section The input offset register 306 for specifying the memory address offset for each processing color of the image data stored in the image data, the output image format register 307 for specifying the format of the output data after the image processing, and the output line for specifying the length of the output image data Long register 308 An output offset register 310 which specifies the offset of the memory address for storing the output image data to the head address of a memory area for storing output image data output memory address register 309 is designated, and for each color.

  Each pixel is represented by 8 bits each of red (R), green (G), and blue (B), and input image data having a line length of 32768 pixels is stored in the RAM unit 112 as shown in FIG. If the input image format register 303 is set, the contents indicating three colors and 8 bits are set, the input line length register 304 is set to 32768 (0x8000 in hexadecimal notation), and the input memory address register 305 is set to the head address. 0x8010_0000, and 0x0001_0000 which is an offset of the memory address for each color is set in the input offset register 306.

  Also, output image data (1-bit data) binarized into four colors of cyan (C), magenta (M), yellow (Y), and black (K) is stored in the RAM unit 112 as shown in FIG. The output image format register 307 contains contents representing 1 bit of 4 colors, the output line length register 308 contains 32768 pixels, the output memory address register 309 contains cyan head address 0x8110_0000, and the output offset register 310 Is set to 0x0001 — 0000, which is an offset for each color.

  The control circuit 202 has a function of controlling the entire image processing circuit unit 102.

  The read DMAC 203 has a function of issuing a read request to the system bus bridge 107 via the internal bus line 206 in order to read data to be processed from the RAM unit 112.

  The image processing circuit 204 performs color space conversion processing, gamma conversion processing, quantization processing using an error diffusion method, and the like on the image data read by the read DMAC 203 in accordance with the contents of the command / parameter register 302, and the printer engine. The binarized data that can be printed is generated.

  The write DMAC 205 has a function of issuing a write request to the system bus bridge 107 in order to store the binarized data generated by the image processing circuit 204 in the RAM unit 112.

  Next, operations of the read DMAC 203 and the write DMAC 205 will be described with reference to the drawings.

  When the input image data is stored in the RMA unit 112 as shown in FIG. 4 and each register of the register unit 201 is set as described above, the CPU 101 instructs the image processing start register 301 to start image processing. After writing, the control circuit 202 instructs the read DMAC 203 to issue a read request for image data.

  Receiving the read instruction, the read DMAC 203 reads 32-byte data from the address 0x8010_0000 specified by the input memory address register 305, that is, R data from the first pixel to the 32nd pixel. Next, the read DMAC 203 reads the 32-byte G data from the address 0x8011_0000 obtained by adding the address offset 0x0001_0000 stored in the input offset address register 306. Similarly, the read DMAC 203 reads B data of 32 bytes from 0x8012_0000.

  When the reading of the data of each color is completed, the control circuit 202 issues a control signal to the image processing circuit 204, and the image processing circuit 204 performs processing such as color space conversion according to the contents of the command / parameter register 302 and the like. , Generate output data. Thereafter, the control circuit 202 performs control so that the reading of input data and image processing are sequentially repeated for the number of pixels set in the input line length register 304.

  On the other hand, when the image processing circuit 204 generates 256 bits of data for each color, that is, data for 256 pixels, the control circuit 202 causes the write DMAC 205 to write the generated binary image data to the RAM unit 112. Take control. The write DMAC 205 issues a request to write the data from the first pixel to the 256th pixel of C, that is, the 32-byte data at the address 0x8110_0000 specified by the output memory address register 309 according to the instruction of the control circuit 202. Similarly, the write DMAC 205 adds 32 bytes of M data to the address 0x8111_0000, 32 bytes of Y data to the address 0x8112_0000, and 32 bytes of K data to the address 0x8113_0000. Are sequentially written to the system bus bridge 107 so as to be written. Thereafter, the binarized image data generated in the same manner is written into the RAM unit 112.

  When the read DMAC 203 and the write DMAC 205 issue a memory access request, the control circuit 202 performs control to issue a master ID together. At this time, the control circuit 202 controls to switch the master ID issued by the read DMAC 203 according to the contents of the input image format register 303.

  Similarly, control is performed so that the write DMAC 205 issues a different master ID depending on the contents of the output image format register 307.

  Next, the printer engine interface unit of the image forming controller apparatus according to the present embodiment will be described with reference to the drawings.

  FIG. 6 is a block diagram showing the configuration of the printer engine interface unit. The printer engine interface unit 103 includes a register unit 601, a control circuit 602, a DMAC 603, and an engine transfer circuit 604.

  As shown in FIG. 7, the register unit 601 includes an engine transfer start register 701 that instructs the printer engine to start transferring image data, a transfer image format register 702 that specifies the format of image data to be transferred to the printer engine, and an image to be transferred. A transfer line length register 703 for designating the length of data, a memory address register 704 for designating the start address of a memory area in which image data is stored, and an address offset for each color of image data stored in the RAM unit 112 The offset register 705 is designated.

  The control circuit 602 is a circuit block that controls the entire printer engine interface unit 103.

  The DMAC 603 has a function of issuing a read request to the system bus bridge 107 via the internal bus line 605 in order to read data to be transferred to the printer engine from the RAM unit 112.

  The engine transfer circuit 604 transfers the data read by the DMAC 603 to the printer engine via the engine interface.

  When the DMAC 603 issues a memory access request, the control circuit 602 performs control so that a master ID is issued simultaneously. The control circuit 602 controls the master ID to be issued at this time so as to switch according to the contents of the transfer image format register.

  Next, the operation of the memory controller of the image forming controller apparatus according to the embodiment of the present invention will be described with reference to the drawings.

  FIG. 8 shows master IDs that are simultaneously output when the CPU 101 and the DMAC of each block constituting the image forming controller device 100 issue an access request to the RAM unit 112 via the memory controller 106.

  The DMAC of the CPU 101, the communication interface unit 104, and the external bus circuit unit 105 uses a fixed master ID regardless of the processing content. On the other hand, as described above, the read DMAC 203 and the write DMAC 205 of the image processing unit 102 selectively switch the master ID according to the format of the image data to be processed and issue it together with the access request. That is, different master IDs are used for single color processing such as monochrome printing and for multicolor processing of color printing.

  Similarly, the printer engine interface unit 103 issues an access request to the memory controller 106 using different master IDs when transferring single-color image data and when transferring multi-color image data.

  As shown in FIG. 9, the memory controller 106 selects and issues a memory access command to be issued to the RAM unit 112 according to the master ID received together with the memory access request from the CPU 101 and the DMAC of each block. That is, in response to a memory access request from the CPU 101, the communication interface unit 104, and the external bus circuit unit 105, or a memory access request from the image processing unit 102 or the printer engine interface unit 103 when handling monochrome image data, the RAM A READ command and a WRITE command are issued to the synchronous DRAM of the unit 112. On the other hand, when handling multi-color image data, in response to a memory request from the image processing unit 102 or the printer engine interface unit 103, a READA command and a WRITEA command are issued to access the memory of the RAM unit 112.

  As described above, when the memory controller 106 issues a memory access command to the RAM unit 112 so that the image processing circuit unit 102 and the printer engine interface unit 103 handle single-color image data, the memory is executed by the READ command and the WRITE command. When accessing and handling multi-color image data, memory access can be performed efficiently with any image format by performing memory access with the READA command and the WRITEA command.

  In the above-described embodiment, the case where the DMAC of each block issues a different master ID depending on the image format, and the memory controller determines the memory access command to be issued to the memory element based on the master ID received together with the memory access request. However, the present invention is not limited to this. The memory controller and the register for setting the image format of each block are respectively connected, and the image format register of the block corresponding to the master ID received together with the memory access request is stored. It goes without saying that the present invention is configured even if the image forming controller device determines a memory access command issued to the memory element by the memory controller according to the contents.

  In this case, the DMAC of each block can constitute the present invention without switching the master ID issued according to the image data format.

  In addition, the memory controller itself has a register for storing the contents representing the format of the image data. When the memory access request is received, the memory controller determines the memory access command issued to the memory element according to the contents of the register. It goes without saying that the present invention is configured even with a controller device.

  Further, in the above-described embodiment, the case where the CPU and each block are configured as a system LSI sealed in one package has been described, but the present invention is not limited to this, and some blocks It goes without saying that the present invention can be configured even with an image forming controller device in which all the blocks are configured by individual ICs or the like.

  In the above-described embodiment, the case where the respective blocks are connected by the system bus bridge has been described. However, the present invention is not limited to this, and the respective blocks share the bus line. It goes without saying that the present invention is configured even in an image forming controller device that arbitrates bus rights by a bus right request signal and a response signal issued by each block.

1 is a block diagram illustrating a configuration of an image forming controller device according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of an image processing unit of the image forming controller device according to the embodiment of the present invention. It is a figure which shows the structure of the register part of the image processing part shown in FIG. FIG. 3 is a diagram illustrating a state in which image data in which each pixel is expressed by three colors and eight bits is stored in a memory element in the image forming controller device according to the embodiment of the present invention. FIG. 4 is a diagram illustrating a state in which image data in which each pixel is represented by four colors and one bit is stored in a memory element in the image forming controller device according to the embodiment of the present invention. 3 is a block diagram illustrating a configuration of a printer engine interface unit of the image forming controller device according to the embodiment of the present invention. FIG. It is a figure which shows the structure of the register part of the printer engine interface part shown in FIG. 5 is a diagram illustrating a master ID issued by each block in the image forming controller device according to the embodiment of the present invention. FIG. FIG. 5 is a diagram illustrating a relationship between a memory access command issued by a memory controller of the image forming controller device according to the embodiment of the present invention and a master ID. It is a figure explaining the structure of a synchronous DRAM. It is a figure explaining the memory access procedure (a) by a READ command and a WRITE command, and the memory access procedure (b) by a READA command and a WRITEA command. It is a figure explaining a mode that the image data comprised by CMYK four colors is stored in synchronous DRAM. It is a figure explaining a mode that the image data comprised by K1 color is stored in synchronous DRAM.

Explanation of symbols

100 Image formation controller device 101 CPU
DESCRIPTION OF SYMBOLS 102 Image processing part 103 Printer engine interface part 104 Communication interface part 105 External bus circuit part 106 Memory controller 107 System bus bridge 108a-108f Bus line 109 Image formation controller ASIC
110 Expansion slot 111 External bus 112 RAM section 113 Memory bus 201 Register section 202 Control circuit 203 Read DMAC
204 Image processing circuit 205 Write DMAC
206 Internal Bus Line 301 Image Processing Start Register 302 Command Parameter Register 303 Input Image Format Register 304 Input Line Length Register 305 Input Memory Address Register 306 Input Offset Register 307 Output Image Format Register 308 Output Line Length Register 309 Output Memory Address Register 310 Output Offset register 601 Register section 602 Control circuit 603 DMAC
604 Engine transfer circuit 605 Internal bus line 701 Engine transfer start register 702 Transfer image format register 703 Transfer line length register 704 Memory address register 705 Offset register

Claims (13)

In an image formation controller device that performs image processing on input image data to generate and output image formation data,
A memory controller capable of issuing at least two memory access commands, a first memory access command and a second memory access command, to a connected memory element;
One or more DMA controllers requesting the memory controller to issue a memory access command;
Image data color number detection means for determining whether the image data is composed of a single color or multiple colors;
When the DMA controller requests the memory controller to issue a memory access command, if the image data color number detection means determines that the image data is single-color image data, the memory controller Memory access control for issuing the first memory access command and controlling the memory controller to issue the second memory access command to a memory element when it is determined that the image data is multicolor image data And an image forming controller device.   The memory access control means controls the memory access request of one or a plurality of DMA controllers designated in advance among the plurality of DMA controllers, and the memory access request of a DMA controller other than the designated DMA controller. 2. The image forming controller according to claim 1, wherein the memory controller issues only one of the first memory access command and the second memory access command.   3. The image forming controller device according to claim 1, wherein the memory access command is a memory read command for reading data stored in the memory element.   3. The image forming controller according to claim 1, wherein the memory access command is a memory write command for writing data to the memory element.   The memory controller has a function of controlling a synchronous DRAM that specifies a storage element to be accessed by a set of a row address and a column address and inputs a command and inputs / outputs data in synchronization with an input clock signal. The image forming controller device according to claim 1, wherein the image forming controller device is an image forming controller.   The first memory read command is a READ command for instructing a read without synchronous pre-charge of the synchronous DRAM, and the second memory read command is a READA command for instructing a read with automatic pre-charge of the synchronous DRAM. The image forming controller device according to claim 5.   The first memory write command is a WRITE command for instructing a synchronous DRAM non-auto-precharge write, and the second memory write command is a WRITEA command for instructing a synchronous DRAM auto-precharge write. The image forming controller device according to claim 5.   The image according to any one of claims 1 to 7, wherein the DMA controller issues a master ID unique to each DMA controller together with a request for issuing a memory access command to the memory controller. Forming controller device.   In one or a plurality of the DMA controllers, the master ID issued when image data is composed of a single color is different from the master ID issued when image data is composed of multiple colors. The image forming controller device according to claim 8.   The image data color number detection means determines whether the image data is composed of a single color or a multicolor based on a master ID issued by the DMA controller together with a memory access command issuance request. Item 10. The image forming controller device according to Item 9.   The image forming controller apparatus according to claim 1, further comprising a register that stores image data format information representing a configuration of image data.   12. The image forming controller according to claim 11, wherein the number-of-colors detection unit determines whether the image data is composed of a single color or multiple colors based on the image data format information stored in the register. apparatus. In a printer apparatus having an image formation controller device and an image formation engine that performs printing based on image formation data output from the image formation controller device.
A memory controller capable of issuing at least two memory access commands of a first memory access command and a second memory access command to a connected memory element; and a memory access to the memory controller. One or a plurality of DMA controllers that request command issuance, image data color number detection means for determining whether the image data is composed of single color or multicolor, and the DMA controller to the memory controller When the memory access command is issued, the memory controller issues a first memory access command to the memory element when the image data color number detection means determines that the image data is monochrome image data. Are determined to be multicolor image data. Printer apparatus characterized by comprising a memory access control means for the memory controller is controlled so as to issue the second memory access command to the memory device if.

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