JP2752082B2 - Controller for digital signal processing circuit - Google Patents

Description

The present invention relates to a control device for controlling a digital signal processing circuit for digitally processing a video signal by a central processing system. The digital signal processing circuit changes (supplies) various control data supplied to a digital signal processing circuit in synchronization with a vertical synchronizing signal so that digital signal processing is smoothly performed.

(Prior Art) Conventionally, a digital video signal processing circuit is controlled by a central processing system using a microcomputer. FIG. 4 shows a block diagram of the configuration. In FIG. 4, 11 is a microcomputer, 12 is a decoder, and 16 is a digital video signal processing circuit. The microcomputer 11 is connected to the decoder 12 via a bus 17. The decoder 12 has a transfer D
The flip-flops 13, 14, 15,... Constitute a data path to the digital video signal processing circuit 16, 18 is a common data line connecting the decoder 12 and the D flip-flop 13, and 20A, 20B, 20C are Are data lines that connect the D flip-flops 13, 14, 15,... And the digital video signal processing circuit 16. Reference numerals 19A, 19B, and 19C denote signal lines for guiding a transfer destination selection signal from the decoder 12. In the following, a description will be given of a configuration for transferring three types of data.

In the operation of such a configuration, first, the microcomputer 11 converts control data (for example, comparison reference values, coefficient data, etc.) necessary for the digital video signal processing circuit 16 and an address to which the control data is transferred into a packet format. Are supplied to the decoder 12 in order. The decoder 12 transfers the input control data to any one of the D flip-flops 13, 14, and 15, generates a selection signal by decoding the address signal, and outputs this signal to the D flip-flops 13, 14,.
15 is applied as an output operation control signal. Since the control data is transferred first, the D flip-flops 13, 14, 15 perform an output operation at the timing when the selection signal is input. Accordingly, the digital video signal processing circuit 16 is provided with various control data necessary for predetermined circuits such as deflection processing, color signal processing, A / D and D / A conversion processing, and performs digital processing of video signals. Become.

A digital video signal processing circuit performs a normal process of digitally processing a video signal and converting it into an analog signal and outputting the converted signal for display, and a case of performing a special process such as screen still, enlargement, reduction, and strobe. There is. When the latter special processing is performed, the screen is switched from the normal processing screen to the special processing screen. Therefore, it is desirable that the control data change or the supply timing coincide. If each control data is changed or newly supplied at the timing of non-coincidence, the image quality deteriorates at the moment of screen switching. Therefore, the change or supply of the control data must be completed within the vertical synchronizing signal period or very short if it is out of the period.

Considering the circuit shown in FIG. 4 from such a viewpoint, the time from the start of the special processing until the digital video signal processing circuit 16 is completely in the special processing state, that is, the microcomputer 11 has a plurality of control data and address data The time required to register the signals and sequentially supply them to the decoder 12 via the bus 17 sufficiently exceeds the vertical synchronization signal period, so that the digital video signal processing circuit 16 operates normally even during the special image display period. Does not perform any special processing, resulting in image distortion.

(Problem to be Solved by the Invention) In a system in which a digital video signal processing circuit is controlled by a microcomputer, when special display is performed, a data transfer period for supplying various control data required for special display processing to the digital video signal processing circuit. In addition, since the time required for the pre-processing sufficiently exceeds the vertical synchronizing signal period, an image display period occurs before control data for special display is available in the digital video signal processing circuit, and there is a problem that a screen is disturbed. . When returning from the special display to the normal display image, displaying the special display screen stored in the memory until the control data for the normal display is completed does not cause the inconvenience of screen disturbance.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a control device for a digital signal processing circuit which eliminates the above-mentioned problems and prevents screen disturbance when switching to a special display.

[Constitution of the Invention] (Means for Solving the Problems) The present invention is directed to a digital signal for supporting digital signal processing by transferring various control data required for digital processing of a video signal to a predetermined destination of a digital signal processing circuit. In the control device of the signal processing circuit, data for generating the control data, the data including address data for specifying the predetermined supply destination is generated, and the generated data is converted to the digital signal processing circuit. A microcomputer which converts the serial data into data within one vertical synchronizing cycle in synchronization with the vertical synchronizing signal from the microcomputer and outputs the control data by decoding the serialized data from the microcomputer And a first transfer buffer for holding control data from the decoder;
A second transfer buffer for holding the control data from the first transfer buffer at the timing of the vertical synchronization signal and transferring the control data to each supply destination of the digital signal processing circuit.

(Operation) According to such a configuration, the first transfer buffer includes:
The control data supplied via the microcomputer and the decoder is held before the vertical synchronization signal is applied to the second transfer buffer. Therefore, the second transfer buffer is
Control data can be transferred at the same time at the timing of the vertical synchronization signal, and reference value data and coefficient data required for digital signal processing are changed at the same time to prevent screen disturbance.

Hereinafter, the present invention will be described with reference to examples.

FIG. 1 is a block diagram showing one embodiment of a digital signal processing circuit according to the present invention. In the figure, 21 is a microcomputer, 22 is a decoder, 26 is a digital video signal processing circuit, 23, 24 and 25 are transfer D flip-flops, and the microcomputer 21 and the decoder 22 are connected by a bus 30; And D flip-flops 23, 24, 25 are connected by a data line 31 and signal lines 32A, 32B, 32C.

In this embodiment, the data output from the D flip-flops 23, 24, and 25 are not directly supplied to the digital video signal processing circuit 26, and the D flip-flops 23, 24, and 25 and the digital video signal processing circuit 26 D flip-flops 27, 28 and 29 are provided between them. The vertical synchronizing signal generated by the digital video signal processing circuit 26 is led to these D flip-flops 27, 28, 29 as an output operation control signal. However, this vertical synchronization signal is also supplied to the microcomputer 21.

The operation of such a configuration will be described with reference to FIG.
FIG. 2 is a flowchart showing the operation of the microcomputer 21.

When changing control data or supplying new data, a preparation operation is performed in step S11. This operation is a process of setting control data and address data in a predetermined register of the microcomputer 21. When the preparation work is completed, the microcomputer 21
Perform S12 and S13. Steps S12 and S13 are processing for monitoring the incoming of the vertical synchronizing signal and capturing it by detection. Thereby, the microcomputer 21 knows the position of the vertical synchronizing signal.

When the microcomputer 21 knows the timing of the vertical synchronization signal, the microcomputer 21 sequentially executes steps S14, S15, and S16, and serializes the control data and the address data set in the register at the timing of the vertical synchronization signal to the decoder 22, respectively. Forward. The operation of the microcomputer 21 is now completed.

Note that decoding start timing information is required when each data created by the microcomputer 21 is decoded, but the configuration of the signal path of such a timing signal is omitted because it is not an invention relating to the signal format.

Thus, the control data is stored in the D flip-flops 23, 24, and 25, respectively. Here, the control data to be transferred to the D flip-flop 23 together with the address data of the address A is a,
The control data transferred to the D flip-flop 25 together with the address C is denoted by b, and the control data transferred to the D flip-flop 25 is denoted by c. FIG. 3 is a time chart showing the transfer operation of the data A, a, B, b and C, c.

In FIG. 3, (a) shows a vertical synchronizing signal, in which a vertical synchronizing signal period and one vertical scanning period are shown.
(B) shows the operation of the microcomputer 21;
(C), (d) and (e) are D flip-flops, respectively.
23, 24, and 25, and (f), (g), and (h) show the operations of the D flip-flops 27, 28, and 29, respectively.

A period 41 shown in FIG. 3B is a processing period of step S11 described in FIG. 2, and a period 42 is a period of steps S12 and S13. As described above, it can be seen that the microcomputer 21 monitors the preparation work and the vertical synchronization signal at a certain timing, and transfers the data A, a, B, b and C, c in the order of the vertical synchronization signal.

A and a are data to which the D flip-flop 23 is transferred, but the control data a is held in the D flip-flop 23 as shown in (c). The holding timing is determined by applying a selection signal obtained by decoding the address A to the D flip-flop 23. After holding the data in this manner, the D flip-flop 23 can supply the data to the next-stage D flip-flop 27. Similarly, the D flip-flop 24 holds the control data b by the selection signal based on the address B, and the D flip-flop 25 holds the control data c by the selection signal based on the address C.

Thus, the D flip-flops 27, 28, and 29 do not take in the output of the D flip-flops 23, 24, and 25 even if they hold data, that is, do not perform the output operation. The output operation is performed at the timing of the vertical synchronization signal. Therefore, the D flip-flops 27 and 2 are synchronized with the timing of the vertical synchronization signal next to the vertical synchronization signal whose transfer has been started by the microcomputer 21.
8, 29 hold control data from the D flip-flops 23, 24, 25, respectively. This situation is (f), (g), (h)
It becomes as shown in. The respective control data a, b, c are simultaneously taken into respective D flip-flops 27, 28, 29. When the D flip-flops 27, 28, and 29 hold the data, they perform an output operation to the digital video signal processing circuit 26. Therefore, the digital video signal processing circuit 26 determines that each control data is changed or supplied simultaneously. Become. Moreover, since the timing of simultaneous change (supply) is synchronized with the vertical synchronization signal,
Data is changed (supplied) within the vertical synchronization signal period,
The screen can be switched from the normal screen to the special processing screen without causing screen disturbance.

In the above embodiment, the microcomputer 21
All data transfer must be completed within one vertical scanning period, but when the number of data is large and time is required, D flip-flops 27, 28,
29 may be driven.

[Effects of the Invention] As described above, according to the present invention, control data can be changed (supplied) in a very short time even within or outside the vertical synchronizing signal period, and screen switching without image disturbance occurs. Enable.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a control device for a digital video signal processing circuit according to the present invention, FIGS. 2 and 3 are flowcharts and time charts for explaining the operation of the present invention, and FIG. FIG. 2 is a configuration diagram showing a circuit of FIG. 21: microcomputer, 22: decoder, 23, 24, 25,
... a first D flip-flop, 26 ... a digital video signal processing circuit, 27, 28, 29 ... a second D flip-flop.

Claims (1)

(57) [Claims] 1. A control device for a digital signal processing circuit for supporting digital signal processing by transferring various control data required for digital processing of a video signal to a predetermined destination of the digital signal processing circuit, wherein the control data is generated. Data including address data for designating the predetermined supply destination, and synchronizing the generated data with a vertical synchronization signal from the digital signal processing circuit for one vertical synchronization cycle. A microcomputer for converting serialized data into serial data and outputting the same; a decoder for decoding serialized data from the microcomputer to create and output the control data; and a first for storing control data from the decoder. And the control data from the first transfer buffer and the timing of the vertical synchronization signal. And a second transfer buffer for holding the data and transferring it to each destination of the digital signal processing circuit.