JP3217551B2 - Still image storage and transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system in which a plurality of still picture data held in a frame memory section are combined into a single video signal and sent out to provide a service, or still picture data sent from the outside. Is stored in the frame memory unit.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional still image storage / transmission device. In FIG. 1, reference numeral 1 denotes general control for analyzing still image information sent from a host computer (not shown), controlling buffering of the still image information, and controlling each unit for transmitting a still image. Unit 2, a communication control unit for communicating with a host computer, 3 a RAM for storing a program for operating the general control unit 1 and a RAM used as a work area, 4 a read timing signal synchronized with an output video signal, etc. A read timing generator for generating various synchronization signals; a header information register for holding header information necessary for displaying a still image; a read frame address register for holding an address of a still image to be transmitted; 7 is a write frame address register for holding the address of a still image to be stored, and 8 is Parallel / serial converter for sending header information (hereinafter,
P / S converter, 9 is a bit extension unit for transmitting the header information, 10 is a frame memory unit for holding a still image, and 11 is a digital / analog converter (hereinafter D / A). An analog / digital converter (hereinafter, referred to as an A / D converter) 12 for converting a video signal input by an analog signal into a digital signal, and 13 for writing a still image to the frame memory unit 10. Is a timing generation unit that generates the timing signal of FIG. 14a, 14b, 14c, and 14d are switching circuits that can be switched based on a write / read switching signal output from the overall control unit 1.

Next, the operation will be described. In the above-described still image storage / transmission device, the overall control unit 1 analyzes the still image information sent from the host computer using the communication control unit 2 and buffers it in the RAM 3. If the command sent from the host computer instructs storage of a still image, the frame number of the still image is set in the write frame address register 7, and the still image data is obtained from the A / D converter 12. Then, the still image data is written to the frame memory unit 10 according to the write timing signal generated by the timing generation unit 13.

When a command sent from the host computer instructs display of a still image, the still image information is rearranged on the RAM 3 in the order to be displayed. Further, the integrated control unit 1 sets the frame numbers of the still image information in the specified order in the read frame address register 6 based on the read timing signal output from the read timing generation unit 4, and sets the header necessary for display. Information and the like are set in the header information register 5. This header information is information that is multiplexed as identification information in the vertical blanking period of the composite synchronization signal via the P / S converter 8 and the bit extension unit 9 and is sent to the D / A converter 11. The still image data corresponding to the header information is referred to the value of the read frame address register 6 set by the general control unit 1 and the D / A conversion unit based on the read timing signal output from the read timing generation unit 4. It is sent to 11.
As described above, the information regarding reading is processed by the general control unit 1 for each frame based on the data held in the RAM 3 and output to each unit.

[0005]

Since the conventional still image storage and transmission apparatus is configured as described above, when a plurality of still images are cyclically transmitted in the same order, the general control unit 1 controls the same. Therefore, there is a problem that the burden on the overall control unit 1 is always large.

Further, when the contents of a still image are updated, there is a problem that a time delay of up to one cycle occurs until the updated still image is actually transmitted.

Another problem is that it is difficult to transmit a still image by interrupting the cyclic transmission and interrupting a different still image.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the invention of claim 1 is directed to a general control unit for transmitting a plurality of still images cyclically in the same order. It is an object of the present invention to obtain a still image storage and transmission device with reduced load.

According to a second aspect of the present invention, when the content of a still image is updated or a new still image is added and transmitted, the cyclic transmission is temporarily stopped and the updated or added still image is added. It is an object of the present invention to obtain a still image storing / sending device capable of sending with priority.

[0010]

According to a first aspect of the present invention, there is provided a still image storage / transmission apparatus which sequentially registers still image number information of each still image in a sequential service RAM unit, and cyclically stores the still image number information in the sequential service RAM. The frame synchronization signal of the output video signal generated by the read timing generation unit when the corresponding still image is output is counted by the cyclic frame counter unit, and a frame address corresponding to the registration address of the still image number information is generated. Then, a frame address corresponding to the registration address is repeatedly generated up to the final registration address of the still image number information, the still image number information is read from the sequential service RAM unit based on the frame address, and the still image data is stored. Frame memory address and identification information actually multiplexed during the vertical blank period Are read out from the still image registration RAM unit at the timing of the output video signal based on the still image number information, and the still image data stored in the frame memory is adjusted one frame at a time to the timing of the video signal. The above-mentioned identification information for identifying each still image is multiplexed into a single video signal and transmitted.

In the still image storing and transmitting apparatus according to a second aspect of the present invention, the cyclic frame counter section is controlled by the general control section, and stores the frame address corresponding to the registered address of the still image number information registered in the sequential service RAM section. The counting of the synchronization signal generated by the read timing generator for generating is stopped, and the priority still image number information output register sets the still image number information designated by the general control unit, and the cyclic frame counter unit Based on the still image number information read from the sequential service RAM unit or the still image number information output from the priority still image number information output register, the frame memory address of the frame memory storing the still image data and each still image Actually reproduced from the information to identify the vertical blank The above-described method for reading out the identification information and the like multiplexed therebetween from the still image registration RAM unit, adjusting the still image data stored in the frame memory one frame at a time to the timing of the video signal, and identifying each still image during the vertical blanking period The identification information is multiplexed, synthesized into one system of video signal, and transmitted.

[0012]

According to the first aspect of the present invention, there is provided a still image storage / transmission device based on a frame address in which still image number information of each still image written in the sequential service RAM unit is repeatedly output up to the final address of the still image number information. The video data to be output is referred to and read out, and further, based on the still image number information, the frame memory address where the corresponding still image is stored, the identification information actually multiplexed in the vertical blank period of the video signal, etc. The identification information is read out from the still image registration RAM unit in synchronization with the signal timing, and the identification information is multiplexed and output during the vertical blank period of the still image video signal stored in the frame memory address. Since the control when images are repeatedly transmitted in the same order is not directly performed by the general control unit,
The burden on the overall control unit is reduced.

In the still picture storing and transmitting apparatus according to the second aspect of the present invention, the still picture number information designated by the general control section is set in the priority still picture number information output register, and the read performed by the cyclic frame counter section is performed. The count of the frame synchronization signal generated by the timing generation unit is temporarily stopped by the overall control unit, and the still image number information set in the priority still image number information output register is selected,
Still image registration RAM based on the selected still image number information
The identification information frame memory address is output from the unit, the still image data stored in the frame memory of the frame memory address is read, and the still image data corresponding to the still image is output during the vertical blank period of the output video signal of the still image. Since the identification information is multiplexed and output, processing such as interrupting and transmitting an updated or added still image can be performed in a short time.

[0014]

【Example】

Embodiment 1 FIG. An embodiment of the first aspect of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a still image storage / transmission device according to the present embodiment. In FIG. 1, the same or corresponding parts as in FIG. In the figure, reference numeral 21 denotes a cyclic frame counter unit which counts a frame synchronization signal generated by the read timing generation unit 4 and outputs a frame address, and 22 denotes a sequentially output still image number information of each still image as a registration address. The sequential service RAM unit 23 to which the data is written is a data latch unit for holding the still image number information. Reference numeral 25 denotes a max address register, which holds the value of the last registered address of the still image number information written in the sequential service RAM unit 22. 24 compares the last registered address held in the max address register 25 with the frame address output from the cyclic frame counter unit 21;
This is an address comparator that outputs a reset pulse to the cyclic frame counter unit 21 when they match. Reference numeral 26 denotes a still image registration RAM unit in which a frame memory address of the frame memory unit 10 in which still image data is stored, identification information of a still image actually multiplexed in a vertical blank period of a still image video signal, and the like are sequentially stored. , 2
7a and 27b are switched by a write / read switching signal output from the general control unit 1, and 14d and 27b are switched.
Reference numerals c and 27d denote switching circuits that are switched by a timing switching signal output from the read timing generator 4.

Next, the operation will be described. In the still image reading control circuit of the still image storage / transmission device, when writing necessary still image data to the frame memory unit 10, the general control unit 1 writes a write frame in accordance with a command given from the host computer via the communication control unit 2. Using the address register 7, the A / D converter 12, and the timing generator 13, the still image data sent from the outside to the frame memory 10 is stored. In this case, the switching circuits 14a and 14c are switched to the write side by the write / read switching signal output from the general control unit 1.

When still image data is displayed, the switching circuits 14a, 14b, 14c, 27a, 27b are switched to the read side by a write / read switching signal output from the general control unit 1. The general control unit 1 sequentially writes still image number information of each still image sequentially output to the sequential service RAM unit 22 in accordance with a command given from the host computer via the communication control unit 2, and further writes each still image. Using the still picture number information as an offset address, the frame memory address of the frame memory unit 10 in which the still picture data corresponding to the still picture number information is stored, or the still picture actually multiplexed in the vertical blank period of the still picture video signal Is written in the still image registration RAM unit 26.

In order to perform a cyclic operation,
The last registered address of the sequential service RAM unit 22 is set in the max address register 25, and the read timing generation unit 4 is enabled. As a result, the cyclic frame counter 21 starts counting the frame synchronization signal output from the read timing generator 4 from “0”. The count value is always stored in the remax address register 25 by the address comparator 24.
Is compared with the last registered address value. Then, when the value becomes the same as the last registered address value of the max address register 25, a reset pulse is output to the cyclic frame counter unit 21, and the cyclic frame counter unit 21 is reset and the read timing generation unit 4 The output frame synchronization signal is counted again from "0". This count value is output to the sequential service RAM unit 22 as a frame address.

The sequential service RAM unit 22
Still picture number information is generated in order according to the frame address output from the cyclic frame counter section 21. The still image number information output from the sequential service RAM unit 22 is passed to the still image registration RAM unit 26 after being latched by the data latch unit 23. Still image registration R
The AM unit 26 uses the still image number information as an offset address, and stores the still image data corresponding to the still image number information in the frame memory address of the frame memory unit 10 where the still image data is stored or in the vertical blank period of the still image video signal. The multiplexed identification information is output to the header information register 5 and the lead frame address register 6 according to the timing of the output video signal. The frame memory address indicated by the read frame address register 6 is input to the frame memory unit 10 and the corresponding still image data is read out.
It is output via the D / A converter 11. The identification information corresponding to the still image data is stored in the header information register 5, P / S
The video signal is multiplexed and output during the vertical blanking period of the video signal of the still image output via the D / A conversion unit 11 via the conversion unit 8 and the bit extension unit 9.

As described above, according to this embodiment, the cyclic frame counter unit 21, the sequential service RAM unit 22, the address comparator 24, the max address register 25, the still image registration RAM unit 26, etc. Since the reading is performed by clicking, the burden on the overall control unit 1 is reduced.

Embodiment 2 FIG. Hereinafter, an embodiment of the second aspect of the present invention will be described with reference to the drawings. 2, the same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, reference numeral 30 denotes a priority still picture number information output register in which the designated still picture number information is set under the control of the general control unit 1. Reference numeral 27e denotes a switching circuit that is switched by a priority still image selection signal output from the overall control unit 1.

Next, the operation will be described. In this still image storage / transmission device, when writing necessary still image data, the overall control unit 1 sends the write frame address register 7 and the A / D conversion unit 12 in accordance with a command given from the host computer via the communication control unit 2. The still image data sent from the outside to the frame memory unit 10 is stored using the timing generation unit 13. When displaying still image data, the overall control unit 1 follows a command given from the host computer via the communication control unit 2 and
Still image number information of each still image sequentially output to the sequential service RAM unit 22 is written in order, and still image data corresponding to the still image number information is written using the still image number information of each still image as an offset address. Is written in the still image registration RAM unit 26 with the frame memory address of the frame memory unit 10 in which the is stored and the identification information of each still image actually multiplexed during the vertical blanking period of the still image video signal.

In order to perform a cyclic operation,
The value of the last registered address of the sequential service RAM unit 22 is set in the max address register 25, and the read timing generation unit 4 is enabled. As a result, the cyclic frame counter 21 starts counting the frame synchronization signal output from the read timing generator 4 from “0”. The count value is always stored in the max address register 25 by the address comparator 24.
Is compared with the last registered address value held in the. When the count value becomes the same value as the last registered address value of the max address register 25, a reset pulse is output to the cyclic frame counter unit 21 and the cyclic frame counter unit 21 is reset, The frame synchronization signal of the output video signal is counted again from "0" and output as a frame address.

The sequential service RAM unit 22
Still picture number information is generated in order according to the frame address output from the cyclic frame counter 21. The still image number information is latched by the data latch unit 23 and then passed to the still image registration RAM unit 26. The still image registration RAM unit 26 uses the still image number information as an offset address and multiplexes the frame memory address of the frame memory unit 10 in which the corresponding still image data is stored or the vertical blank period of the still image video signal actually. The identification information is output to the header information register 5 and the read frame address register 6 according to the timing of the output video signal. The frame memory address is input to the frame memory unit 10 via the read frame address register 6, and the still image data is read from the frame memory unit 10 and output via the D / A conversion unit 11. At this time, the identification information is stored in the header information registers 5, P /
The output video signal is multiplexed and output during the vertical blank period of the output video signal via the S conversion unit 8, the bit expansion unit 9, and the D / A conversion unit 11.

If the content of the still image is changed while the still image is being serviced cyclically, the integrated control unit 1 stores the changed still image in the priority still image number information output register 30. Still image number information is set, the cyclic frame counter 21 is temporarily stopped, and a priority still image selection signal is output to output a priority still image number information register 30.
Selects the still image number information to be output and outputs it to the still image registration RAM unit 26. Then, after transmitting the changed still image corresponding to the still image number information for several frames, the general control unit 1 controls each unit again so as to perform normal cyclic transmission.

As described above, according to the present embodiment, even when a still image is being cyclically provided, the still image is set based on the still image number information set in the priority still image number information output register 30. The contents can be changed within a short period of time, and the changed still image can be transmitted for several frames, after which normal cyclic transmission can be resumed.

[0026]

According to the first aspect of the present invention, the cyclic frame counter unit, the sequential service RAM
, A still image registration RAM unit, etc., so that the still image can be cyclically read without imposing a burden on the overall control unit, so that the burden on the overall control unit is reduced. .

According to the second aspect of the present invention, the counting for generating the frame address in the cyclic frame counter section is stopped, and based on the still picture number information set in the priority still picture number information output register, Since the updated or added still image stored in the frame memory is configured to be sent, the updated or added still image is interrupted and sent when the still image is sent cyclically. And the like can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a still image storage / transmission device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a still image storing / sending device according to an embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a conventional still image storage / transmission device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Overall control part 4 Read timing generation part 10 Frame memory part 21 Cyclic frame counter part 22 Sequential service RAM part 26 Still image registration RAM part 30 Priority still image number information output register

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/21 H04N 5/91-5/956

Claims (2)

(57) [Claims] A frame memory unit capable of storing a plurality of frames of still image data, wherein the still image data stored in the frame memory unit is stored in one frame based on a frame memory address.
The data is read out from the frame memory unit frame by frame in accordance with the timing of the video signal, identification information for identifying each still image is multiplexed during the vertical blanking period, and the still image data is synthesized into one system of video signal and transmitted. A sequential service RAM unit in which still image number information of each still image is registered in order,
A read timing generator that generates and outputs a frame synchronization signal of an output video signal when the still image data is output, counts the frame synchronization signal output from the read timing generator, and stores the frame synchronization signal in the sequential service RAM unit. A cyclic frame for repeatedly generating a frame address corresponding to the registered address of the registered still picture number information up to the last registered address of the registered address, and reading out the still picture number information from the sequential service RAM unit based on the frame address. A counter unit and information for identifying each still image generated based on the still image number information and the frame memory address of the frame memory unit in which the still image data is stored are written. RAM
Based on the still image number information read from the unit, the frame memory address where the still image data is stored, identification information actually multiplexed in the vertical blank period reproduced from the information for identifying each still image, etc. RAM for reading still images, and the sequential service RAM
During the period when the unit is not read based on the frame address, and during the period when the still image registration RAM unit is not read based on the still image number information , writing to them is performed.
And a general control unit for performing reading or reading . 2. A frame memory unit capable of storing a plurality of frames of still image data, wherein the still image data stored in the frame memory unit is stored on the basis of a frame memory address.
The data is read out from the frame memory frame by frame at the timing of the video signal, identification information for identifying each still image is multiplexed during the vertical blanking period, and the still image data is synthesized into one system of video signal and transmitted. In the still image storage / transmission device, a sequential service RAM unit in which still image number information of each still image is registered in order, and a lead for generating and outputting a frame synchronization signal of an output video signal when the still image data is output A timing generation unit and a frame synchronization signal output from the read timing generation unit are counted, and a frame address corresponding to the registration address of the still image number information registered in the sequential service RAM unit is set as the final registration address of the registration address. Up to the above-mentioned sequence based on this frame address. A cyclic frame counter for reading out the still picture number information from the static service RAM section or stopping the counting of the frame synchronization signal; and outputting priority still picture number information to which the designated still picture number information is set. A register and information for identifying each still picture generated based on the still picture number information and the frame memory address of the frame memory unit in which the still picture data is stored are written. The frame memory address storing the still image data and each still image are identified based on the still image number information read from the unit or the still image number information read from the priority still image number information output register. Information that is actually multiplexed during the vertical blank period A still image registration RAM portion to be read, the sequential service RA
The M section and the still image registration RAM section write or read
A period which is not out looking performs writing to them, and is set to the counting performed in cyclic frame counter unit is stopped, also the priority still picture number information output register to control the priority still image number information output register Still image number information is specified, and the still image number information supplied to the still image registration RAM unit is
A still image number information read from the sequential service RAM unit or a general control unit for switching to still image number information read from the priority still image number information output register. Storage and delivery device.