JPH0750799A - Still picture storing/sending device - Google Patents

Abstract

PURPOSE:To reduce burden on a general control part when a still picture is sent sequentially by multiplexing identification information to identify the still picture in a vertical blanking period, and sending by synthesizing them in a video signal of one system. CONSTITUTION:A sequential service RAM part 22 generates still picture number information sequentially according to a frame address outputted from a cyclic frame counter part 21. The still picture number information outputted from the sequential service RAM part 22, after being latched with a data latch part 23, is delivered to a still picture registration RAM part 26. The still picture registration RAM part 26 outputs the frame memory address of a frame memory part 10 in which still picture data in accordance with the still picture number information is stored and the identification information multiplexed in the vertical blanking period of a still picture video signal actually to a header information register 5 and a read frame address register 6 fitting in the timing of an output video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention synthesizes a plurality of still picture data held in a frame memory unit into a video signal of one system and sends it out to provide a service, or still picture data sent from the outside. The present invention relates to a still image storage / transmission device for storing the image data in the frame memory unit.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the structure of a conventional still image storing and transmitting apparatus. In FIG. 1, reference numeral 1 is an overall control for analyzing still image information sent from a host computer (not shown), controlling the buffering of the still image information, and controlling each part for sending the still image. 2, a communication control unit for communicating with a host computer, 3 a RAM for storing a program for operating the general control unit 1 and used as a work area, 4 a read timing signal synchronized with an output video signal, etc. , A read timing generator for generating various sync signals, a header information register for holding header information necessary for displaying a still image, a read frame address register for holding an address of a still image to be sent, 7 is a light frame address register for holding the address of a still image to be stored, and 8 is the above Parallel / serial converter for sending header information (hereinafter,
P / S conversion unit), 9 is a bit expansion unit for transmitting the header information, 10 is a frame memory unit for holding a still image, and 11 is a digital / analog conversion unit (hereinafter, D / A). A conversion unit), 12 is an analog / digital conversion unit (hereinafter, referred to as an A / D conversion unit) that converts a video signal input by an analog signal into a digital signal, and 13 is a unit for writing a still image in the frame memory unit 10. Is a timing generation unit for generating the timing signal. 14a, 14b, 14c and 14d are switching circuits that can be switched based on a write / read switching signal output from the overall control unit 1.

Next, the operation will be described. In the above-mentioned still image storing / transmitting apparatus, the overall control unit 1 analyzes the still image information sent from the host computer using the communication control unit 2 and buffers it in the RAM 3. When the command sent from the host computer instructs to store a still image, the frame number of the still image is set in the write frame address register 7 and still image data is obtained from the A / D converter 12. Then, the still image data is written to the frame memory unit 10 according to the write timing signal generated by the timing generation unit 13.

When a command sent from the host computer instructs the display of still images, the still image information is rearranged in the RAM 3 in the order of display. Further, the integrated control unit 1 sets the frame numbers of the still image information in the read frame address register 6 in the designated order based on the read timing signal output from the read timing generation unit 4, and also the header required for display. Information and the like are set in the header information register 5. This header information is information that is multiplexed as identification information during the vertical blanking period of the composite sync signal via the P / S conversion unit 8 and the bit expansion unit 9 and sent to the D / A conversion unit 11. The still image data corresponding to the header information refers to the value of the read frame address register 6 set by the overall control unit 1, and based on the read timing signal output from the read timing generation unit 4, the D / A conversion unit Sent to 11.
As described above, the information regarding the reading is output to each unit by the integrated control unit 1 processing for each frame based on the data stored in the RAM 3.

[0005]

Since the conventional still image storing / transmitting device is constructed as described above, when a plurality of still images are cyclically transmitted in the same order, the control of the general control section 1 is performed. Since this is performed, there is a problem that the overall control unit 1 always has a heavy load.

Furthermore, when the content of the still image is updated, there is a problem that a maximum time delay of one cycle occurs before the updated still image is actually transmitted.

There is also a problem in that it is difficult to temporarily stop the cyclic transmission to interrupt a different still image and transmit the still image.

The present invention has been made to solve the above problems, and the invention of claim 1 is directed to a general control unit for cyclically sending a plurality of still images in the same order. It is an object of the present invention to obtain a still image storing / transmitting device with reduced load.

According to a second aspect of the invention, when the content of a still image is updated or a new still image is added and transmitted, the cyclic transmission is temporarily stopped and the updated or added still image is temporarily stopped. It is an object of the present invention to obtain a still image storage / transmission device capable of prioritizing and transmitting.

[0010]

A still picture storing and transmitting apparatus according to a first aspect of the present invention sequentially registers still picture number information of each still picture in a sequential service RAM section and cyclically assigns the still picture number to the still picture number. When the corresponding still image is output, the frame synchronization signal of the output video signal generated by the read timing generation unit is counted by the cyclic frame counter unit and the frame address corresponding to the registered address of the still image number information is generated. Then, the frame address corresponding to the registered address is repeatedly generated up to the final registered address of the still image number information, the still image number information is read from the sequential service RAM section based on the frame address, and the still image data is stored. Frame memory address and the identification information actually multiplexed in the vertical blank period. And the like are read from the still image registration RAM section according to the timing of the output video signal based on the above still image number information, the still image data stored in the frame memory is adjusted frame by frame with the timing of the video signal, and a vertical blank period is also set. The above-mentioned identification information for identifying each still picture is multiplexed and combined into one system of video signal to be transmitted.

In the still picture storing and transmitting apparatus according to the second aspect of the present invention, the cyclic frame counter section is controlled by the general control section, and the frame address corresponding to the registration address of the still picture number information registered in the sequential service RAM section is set. The counting of the synchronization signal generated by the read timing generation unit for generation is stopped, the still image number information output register sets the still image number information designated by the general control unit, and the cyclic frame counter unit On the basis of the still image number information read from the sequential service RAM section or the still image number information output from the priority still image number information output register, the frame memory address of the frame memory storing the still image data and each still image Actual vertical blank reproduced from information to identify The identification information or the like multiplexed in between is read from the still image registration RAM unit, the still image data stored in the frame memory is adjusted frame by frame to the timing of the video signal, and each still image is identified in the vertical blank period. The identification information is multiplexed, combined into one system video signal and transmitted.

[0012]

In the still image storing / transmitting apparatus according to the present invention, the still image number information of each still image written in the sequential service RAM unit is based on the frame address at which the still image number information is repeatedly output up to the final address of the still image number information. The frame memory address in which the corresponding still image is stored based on the still image number information and the identification information actually multiplexed in the vertical blank period of the video signal are output. Since the above identification information is multiplexed and output during the vertical blank period of the video signal of the still image stored in the frame memory address and read out from the still image registration RAM section at the timing of the signal, a plurality of still images are output. The control for repeatedly sending images in the same order is not performed directly by the integrated control unit, so
The burden on the integrated control unit will be reduced.

In the still picture storing / transmitting apparatus according to the second aspect of the present invention, still picture number information designated by the integrated control section is set in the priority still picture number information output register, and the reading is performed by the cyclic frame counter section. The integrated control unit temporarily stops the count of the frame synchronization signal generated by the timing generation unit, and the still image number information set in the priority still image number information output register is selected.
Still image registration RAM based on the selected still image number information
The identification information frame memory address is output from the section, the still image data stored in the frame memory of the frame memory address is read, and the still image corresponding to the still image is output during the vertical blank period of the output video signal of the still image. Since the identification information is multiplexed and output, processing such as interrupting and sending the updated or added still image can be performed in a short time.

[0014]

【Example】

Example 1. An embodiment of the invention of claim 1 will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the still image storage / transmission apparatus of this embodiment. In FIG. 1, the same or corresponding parts as in FIG. In the figure, 21 is a cyclic frame counter that counts the frame synchronization signal generated by the read timing generator 4 and outputs a frame address, and 22 is the sequentially output still image number information of each still image as a registered address. The written sequential service RAM section 23 is a data latch section for holding still picture number information. A maximum address register 25 holds the value of the final registration address of the still picture number information written in the sequential service RAM unit 22. 24 compares the final registered address held in the max address register 25 with the frame address output from the cyclic frame counter unit 21,
It is an address comparator that outputs a reset pulse to the cyclic frame counter unit 21 when they match. Reference numeral 26 denotes a still image registration RAM unit in which the frame memory address of the frame memory unit 10 in which still image data is stored and identification information of still images actually multiplexed in the vertical blank period of the still image video signal are sequentially stored. Two
7a and 27b are switched by a write / read switching signal output from the integrated control unit 1, and 14d and 27b.
Reference characters c and 27d denote switching circuits that switch according to the timing switching signal output from the read timing generation unit 4.

Next, the operation will be described. In the still image read control circuit in this still image storage / transmission device, when the necessary still image data is written in the frame memory unit 10, the general control unit 1 follows a command given from the host computer via the communication control unit 2 to write a light frame. The address register 7, the A / D conversion unit 12, and the timing generation unit 13 are used to store still image data sent from the outside to the frame memory unit 10. In this case, the switching circuit 14a and the switching circuit 14c are switched to the write side by the write / read switching signal output from the overall control unit 1.

When displaying still image data, the switching circuits 14a, 14b, 14c, 27a and 27b are switched to the read side by the write / read switching signal output from the integrated control unit 1. Then, the overall control unit 1 sequentially writes still image number information of each still image sequentially output to the sequential service RAM unit 22 in accordance with a command given from the host computer via the communication control unit 2, and further The still image number information is used as an offset address, and the still image data that corresponds to the still image number information is stored in the frame memory address of the frame memory unit 10 or the still image that is actually multiplexed in the vertical blank period of the still image video signal. The information regarding the identification information and the like is written in the still image registration RAM unit 26.

In order to perform cyclic operation,
The final registration address of the sequential service RAM unit 22 is set in the max address register 25, and the read timing generation unit 4 is enabled. As a result, the cyclic frame counter unit 21 starts counting the frame synchronization signal output from the read timing generation unit 4 from “0”. The count value is always stored in the maximum address register 25 by the address comparator 24.
Is compared with the final registered address value of. Then, when the value becomes the same as the final registered address value of the max address register 25, a reset pulse is output to the cyclic frame counter unit 21, the cyclic frame counter unit 21 is reset, and the read timing generation unit 4 outputs the reset pulse. The output frame synchronization signal is counted again from "0". This count value is used as a frame address in the sequential service RAM unit 22.
Is output to.

The sequential service RAM section 22 is
Still image number information is sequentially generated according to the frame address output from the cyclic frame counter unit 21. The still image number information output from the sequential service RAM unit 22 is latched by the data latch unit 23 and then passed to the still image registration RAM unit 26. Still image registration R
The AM unit 26 uses the still image number information as an offset address, and at the frame memory address of the frame memory unit 10 in which the still image data corresponding to the still image number information is stored or in the vertical blank period of the still image video signal. The multiplexed identification information is output to the header information register 5 and the read frame address register 6 at the timing of the output video signal. The frame memory address indicated by the read frame address register 6 is input to the frame memory unit 10 and the corresponding still image data is read out,
It is output via the D / A converter 11. The identification information corresponding to this still image data is the header information register 5, P / S
The video signal of the still image output through the conversion unit 8 and the bit expansion unit 9 and further output through the D / A conversion unit 11 is multiplexed and output in the vertical blank period.

As described above, according to this embodiment, the cyclic frame counter section 21, the sequential service RAM section 22, the address comparator 24, the max address register 25, the still image registration RAM section 26, etc. Since the click reading is performed, the burden on the central control unit 1 is reduced.

Example 2. An embodiment of the invention of claim 2 will be described below with reference to the drawings. In FIG. 2, parts that are the same as or equivalent to those in FIG. In the figure, reference numeral 30 is a priority still image number information output register which is controlled by the overall control unit 1 and in which designated still image number information is set. A switching circuit 27e is switched by a priority still image selection signal output from the overall control unit 1.

Next, the operation will be described. In this still image storage / transmission device, when writing necessary still image data, the overall control unit 1 follows the write frame address register 7 and the A / D conversion unit 12 in accordance with a command given from the host computer via the communication control unit 2. The still image data sent from the outside to the frame memory unit 10 is stored by using the timing generation unit 13. When displaying still image data, the overall control unit 1 follows a command given from the host computer via the communication control unit 2,
Still image number information of each still image sequentially output to the sequential service RAM unit 22 is written in order, and still image data corresponding to the still image number information is used with the still image number information of each still image as an offset address. The information about the frame memory address of the frame memory unit 10 in which is stored and the identification information of each still image that is actually multiplexed in the vertical blank period of the still image video signal is written in the still image registration RAM unit 26.

In order to perform cyclic operation,
The value of the final registration address of the sequential service RAM unit 22 is set in the max address register 25 and the read timing generation unit 4 is enabled. As a result, the cyclic frame counter unit 21 starts counting the frame synchronization signal output from the read timing generation unit 4 from "0". The count value is always stored in the maximum address register 25 by the address comparator 24.
Is compared with the final registered address value held in. Then, when the count value becomes the same value as the final registered address value of the max address register 25, a reset pulse is output to the cyclic frame counter unit 21, and the cyclic frame counter unit 21 is reset. The frame sync signal of the output video signal is again counted from "0" and output as a frame address.

The sequential service RAM unit 22 is
Still image number information is sequentially generated according to the frame address output from the cyclic frame counter unit 21. This still picture number information is latched by the data latch section 23 and then passed to the still picture registration RAM section 26. The still image registration RAM unit 26 uses the still image number information as an offset address and is multiplexed in the frame memory address of the frame memory unit 10 in which the corresponding still image data is stored or in the vertical blank period of the still image video signal. The identification information is output to the header information register 5 and the lead frame address register 6 at the timing of the output video signal. The frame memory address is input to the frame memory unit 10 via the read frame address register 6, the still image data is read from the frame memory unit 10, and output via the D / A conversion unit 11. At this time, the identification information is the header information register 5, P /
The signal is passed through the S conversion unit 8, the bit expansion unit 9, and the D / A conversion unit 11 and is multiplexed and output in the vertical blank period of the output video signal.

If the content of the still image is changed while the still image is being serviced cyclically, the central control unit 1 stores the changed still image in the priority still image number information output register 30. The still image number information is set, the cyclic frame counter unit 21 is temporarily stopped, the priority still image selection signal is output, and the priority still image number information output register 30 is output.
The still image number information output by is selected and output to the still image registration RAM unit 26. Then, after transmitting the changed still image corresponding to the still image number information for several frames, the overall control unit 1 controls each unit again so as to perform normal cyclic transmission.

As described above, according to the present embodiment, even when the still image is being serviced cyclically, the still image number is set based on the still image number information set in the priority still image number information output register 30. The contents can be changed within a short time, the changed still image can be transmitted for several frames, and then the normal cyclic transmission can be resumed.

[0026]

According to the first aspect of the invention, the cyclic frame counter section and the sequential service RAM are provided.
And a still image registration RAM unit are provided so that the still image can be cyclically read without burdening the overall control unit, so that the load on the overall control unit can be reduced. .

According to the second aspect of the invention, the count for generating the frame address in the cyclic frame counter section is stopped, and based on the still picture number information set in the priority still picture number information output register, Since it is configured so that the updated or added still images stored in the frame memory can be sent, the updated or added still images are interrupted and sent when cyclically sending the still images. It is possible to perform such processing in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a still image storage / transmission device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a still image storage / transmission device according to an embodiment of the invention of claim 2;

FIG. 3 is a block diagram showing a configuration of a conventional still image storage / transmission device.

[Explanation of symbols]

 1 integrated control unit 4 read timing generation unit 10 frame memory unit 21 cyclic frame counter unit 22 sequential service RAM unit 26 still image registration RAM unit 30 priority still image number information output register

Claims (2)

[Claims] 1. A frame memory unit capable of storing still image data of a plurality of frames, wherein the still image data stored in the frame memory unit is set to 1 based on a frame memory address.
Each frame is read from the frame memory unit at the timing of the video signal, and the identification information for identifying each still image is multiplexed in the vertical blank period, and the still image data is combined into one system of video signal and transmitted. In the still image storing / transmitting device, a sequential service RAM unit in which the still image number information of each still image is registered in order,
A read timing generation unit that generates and outputs a frame synchronization signal of an output video signal when the still image data is output, and a frame synchronization signal output from the read timing generation unit are counted and stored in the sequential service RAM unit. A cyclic frame in which a frame address corresponding to the registered address of the registered still image number information is repeatedly generated up to the final registered address of the registered address, and the still image number information is read from the sequential service RAM section based on this frame address. Information for identifying each still image generated based on the frame memory address of the counter unit and the frame memory unit in which the still image data is stored and the still image number information is written, and the sequential service is also provided. RAM
Based on the still picture number information read from the unit, the frame memory address where the still picture data is stored and the identification information which is reproduced from the information for identifying the respective still pictures and which is actually multiplexed in the vertical blank period. Still image registration RAM unit from which the data is read, and the above-mentioned sequential service RAM
Still image storing and sending, characterized in that it is provided with a centralized control unit for accessing them during the period when the units are not accessed by the frame address and during the period when the still image registration RAM unit is not accessed by the still image number information. apparatus. 2. A frame memory unit capable of storing still image data of a plurality of frames, wherein the still image data stored in the frame memory unit is set to 1 based on a frame memory address.
Each frame is read from the frame memory in synchronization with the timing of the video signal, identification information for identifying each still image is multiplexed in the vertical blank period, and the still image data is combined into one system of video signal and transmitted. In a still image storage / transmission device, a sequential service RAM unit in which the still image number information of each still image is sequentially registered, and a read for generating and outputting a frame synchronization signal of an output video signal when the above still image data is output. The timing generation unit and the frame synchronization signal output from the read timing generation unit are counted, and the frame address corresponding to the registration address of the still image number information registered in the sequential service RAM unit is the final registration address of the registration address. It is repeatedly generated up to the above and based on this frame address Cyclic frame counter that can read the still picture number information from the internal service RAM section or stop the counting of the frame synchronization signal, and priority still picture number information output in which designated still picture number information is set A register and information for identifying each still image generated based on the frame memory address of the frame memory unit in which the still image data is stored and the still image number information are written, and the sequential service RAM Based on the still image number information read from the unit or the still image number information read from the priority still image number information output register, the frame memory address storing the still image data and each still image are identified. Information that is reproduced from the information for A still image registration RAM portion to be read, the sequential service RA
While the M section and the still picture registration RAM section are not accessed, they are accessed, the counting performed in the cyclic frame counter section is stopped, and the priority still picture number information output register is controlled to give priority to that. The still image number information set in the image number information output register is specified, and the still image registration R is performed.
Central control unit for switching the still picture number information supplied to the AM section to the still picture number information read from the sequential service RAM section or the still picture number information read from the priority still picture number information output register A still image storage / transmission device, comprising: