JP3264942B2 - Image display control method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display control method and apparatus, and more particularly to an image display control method and apparatus for displaying a plurality of image data input in time series.

[0002]

2. Description of the Related Art Conventionally, an image display apparatus for monitoring a plurality of series of image information transmitted via a transmission line for monitoring a process in a factory or the like, for a presence meeting in an office building, or the like. Has been developed. These display image signals represented by multiplexed image sequences A to D output in time series from a plurality of image information sources such as the television cameras 501 to 503 and the VTR 504, as shown in FIG. An image display control device for processing such an image signal is shown in FIG.
Was constructed as shown in FIG.

In FIG. 9, reference numeral 21 denotes a transmission path through which four different image sequences A, B, C, and D are transmitted in time series. Reference numeral 22 denotes an interface unit that controls the interface with the transmission path 21. The interface unit 22 extracts an identification number for recognizing an image sequence added to the head of each sequence of image data. It has a function of separating clock signals, horizontal and vertical synchronization signals necessary for writing image data into the image memory 25. The horizontal writing counter 23 and the vertical writing counter 24 are counters for generating an address of the image memory 25 for writing image data. The horizontal write counter 23 is preset to a value output from the interface unit 22 by a horizontal synchronization signal, counts a clock signal, and outputs a horizontal address of the image memory 25. Similarly, the vertical writing counter 24 is preset to a value output from the interface unit 22 at the start of writing one image data of each image sequence, counts a horizontal synchronization signal output from the interface unit 22, The vertical address of the image memory 25 is output.

[0004] From the extracted image sequence identification numbers, the interface unit 22 transfers preset values of the horizontal write counter 23 and the vertical write counter 24 corresponding to the image display position of each sequence to the horizontal write counter 23 and the vertical write counter 24, respectively. Output. In this conventional example, the preset value of the horizontal writing counter 23 is “0” for the image information of the A and C series, and 1 / １ ／ of the number of horizontal pixels of the display device 26 for the B and D series. It is 2. The preset value of the vertical write counter 24 is
The value is “0” for the A and B sequence image information, and is １ ／ of the number of vertical pixels of the display device 26 for the C and D sequence image information. Thereby, as shown in FIG. 9, four series of images are displayed on the display screen of the display device 26.

Reference numeral 25 denotes an image memory, which is a so-called dual port memory in which writing and reading can be performed independently. Reference numerals 28 and 29 denote a vertical read counter and a horizontal read counter, respectively, which count a timing signal output from the read control unit 29 to generate a read address of the image memory 25. Reference numeral 26 denotes a display device such as a CRT, which displays image data read from the image memory 25 in synchronization with a timing signal from the read control unit 29.

[0006] With the above configuration, the image sequence input from the transmission line 21 is identified by the interface unit 22, and after the clock signal and the horizontal synchronization signal are extracted, the image data is input to the image memory 25. Is stored. At this time, after identifying the image sequence, the interface unit 22 presets desired values to the horizontal write counter 23 and the vertical write counter 24. As a result, the image signal input to the image memory 25 is written into the address of the image memory 25 addressed by the address value output from the horizontal write counter 23 and the vertical write counter 24 in synchronization with the clock signal. When one pixel data is thus written, the horizontal write counter 23 is incremented by the clock signal. When the writing of one horizontal scanning line is completed in this way, the horizontal writing counter 23 is preset again to a predetermined value. On the other hand, the vertical write counter 24 is incremented by a horizontal synchronizing signal indicating the end of writing of the horizontal scanning line. After one frame of moving image is written in one frame in this manner, the frame of the next series of moving images is similarly input and written into the image memory 25.

When displaying the image data, the image data written in the image memory 25 is read by the vertical read counter 2
8 and the address values output from the horizontal read counter 27 are sequentially read out in synchronization with the display timing of the display device 26 and displayed on the display device 26.

[0008]

However, in the above-described conventional example, when the image display area on the display device 26 is moved and the display areas of the different series of images overlap, the different series on the image memory 25 are displayed. Images alternately overwrite image data, so in the overlap area,
There is a problem that none of the overlapping images is displayed normally.

That is, as shown in FIG.
Considering the case where the image is displayed with the display position lowered, as shown in FIG. 11, the overlap area 701 includes the image sequence A at times t ₁ , t ₂ , t ₅ , t ₆ ,. Are displayed, and at time t ₃ , t ₄ , t ₇ ,..., The image sequence C is displayed. Therefore, in the display of the overlap area 701, the image sequences A and C are alternately displayed, and a normal display cannot be obtained.

[0010] As shown in FIG. 13, five series of images A, B, C, D and E are sequentially transmitted on a transmission line 21, and as shown in FIG. A,
When B, C, and D are assigned to the top, bottom, left, and right of the display device 26, and the image sequence E is assigned to the center and displayed, FIG.
As shown in the figure, in the central overlapping regions 91 to 94, the moving image sequence E and the images of the overlapping image sequences are alternately displayed, and the image of the moving image sequence E is displayed normally. You can't do that. As described above, in the above-described conventional example, there is a possibility that an image of an arbitrary series transmitted on the transmission path cannot be displayed at an arbitrary position.

The present invention has been made in view of the above-mentioned conventional example, and provides an image display control method and apparatus which can easily display a plurality of image data input in a time series at an arbitrary position on a display screen. The purpose is to do.

[0012]

In order to achieve the above object, an image display control device according to the present invention has the following arrangement. That is, identification means for identifying the image source of each image data input in time series from a plurality of image sources, and each image data is stored for each image source according to the identification by the identification means. The image storage means, having an address corresponding to the coordinates to be displayed on the display screen, displayed at each coordinate of the display screen, the storage position of each pixel of the corresponding image data stored in the image storage means Address storage means for storing at an address corresponding to each of the coordinates, and the storage position stored at an address of the address storage means corresponding to each of the coordinates of the display screen in synchronization with display on the display screen. Display control means for sequentially reading, reading corresponding pixels from the storage positions of the image storage means, and displaying them on the display screen, wherein image data from the plurality of image sources are provided. And displaying the respective data on the display screen. In order to achieve the above object, an image display control method according to the present invention includes the following steps. In other words, the source of each image data input in time series from a plurality of image sources should be identified, and the identified image data should be stored in the image memory for each image source and displayed on the display screen. At each address of the display memory having an address corresponding to the coordinates, the storage position of each pixel of the image data stored in the image memory, which is displayed at each corresponding coordinate of the display screen, is stored, and the display screen is displayed. In synchronization with the display of the display screen, sequentially reads the storage position stored at the address of the display memory corresponding to each coordinate displayed on the display screen, reads the corresponding pixel from the storage position of the image memory, Each of image data from a plurality of image sources is displayed on the display screen.

[0013]

In the above arrangement, the storage positions stored in the addresses of the address storage means corresponding to the respective coordinates of the display screen are sequentially read out in synchronization with the display on the display screen, and the time series are read from a plurality of image sources. By reading out the corresponding pixel from the storage position of the image storage unit that stores the image data input to each image source for each image source and displaying it on the display screen, each of the image data from the plurality of image sources is Display on the display screen.

[0014]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
Examples will be described in detail. <Description of Image Display Apparatus (FIG. 1)> FIG. 1 shows a schematic configuration of an image display apparatus according to an embodiment of the present invention.
FIG. In the figure, 101 is a plurality of images
A transmission line on which the sequences A, B, C and D are transmitted.
You. Reference numeral 102 denotes an interface unit of the transmission path 101.
Image sequence identification added to the beginning of each image data
The number is extracted, transmitted to the CPU 106, and the image
Clock signal required for writing image data to memory 104
It has the function of extracting numbers. 103 is a counter
The preset value input from the CPU 106.
The clock signal and count the clock signal.
The storage address value of the image data to be written to the image memory 104 is
Output. An image storage unit 104 is an image storage unit.
Memory, so-called dual that can write and read independently
Report configuration. Also, this image memory104
Is the total number of pixels per frame of the image sequence A, B, C, D
Has sufficient capacity to store the data. 105 is display
And displays the image information written in the image memory 104.
Show. Reference numeral 106 denotes a CPU, which is an interface unit 1
02 based on the image sequence identification number output from
Refer to table 110 and preset to counter 103
Output the value. Also, the CPU 106 stores in the image memory 104
Each pixel of the written image is displayed on the display unit 105.
Address of the display memory 107 corresponding to the coordinates to be changed.
These pixels are stored in the image memory 104.
Calculate and write the address value. 107 is an address
A display memory serving as storage means;
5 is a display image of each pixel of the image to be displayed for each display pixel.
The storage address value in the memory 104 is
Is written. Reference numeral 108 denotes a read control unit,
Various synchronization signals are sent to the display unit 105, and
From the display memory 107 sequentially in synchronization with the synchronization signal.
I have. Reference numeral 109 denotes an image sequence to be displayed on the display unit 105.
Man-machine for inputting designations and their display positions
An interface unit (MMI); 110 is an ad
Table, and is stored in the image memory 104 of each image series.
1 which is the offset address at the time of writing
03 preset values are stored.

The input image sequence A, B, C, D will be described below.
AX is the number of each horizontal pixel._S , BX_S , CX
_S , DX_S AY, the number of vertical pixels_S , BY_S , CY_S , D
Y_S , Each arbitrary pixel AP, B of each series of images
Let the coordinates of P, CP, and DP be (ax_S , Ay_S ),
(Bx_S , By_S ), (Cx_S , Cy_S ), (Dx_S ,
dy_S ). Further, the number of horizontal pixels of the display unit 105 is X
_d , The number of vertical pixels is Y_d And pixels AP, BP, CP, D
The coordinates of the display unit 105 for displaying each of the P
_d , Ay_d ), (Bx_d , By_d ), (Cx_d , Cy
_d ), (Dx_d , Dy _d ) And referring to FIG.
The operation of the embodiment will be described.

When an image sequence to be displayed on the display unit 105, their display position and the number of vertical and horizontal pixels of each image sequence are input from the MMI 109, the CPU 106 determines an address value in the image memory 104 for storing each image sequence. And an offset address value is registered in the address table 110 in association with the image sequence identification number. For example, for image sequence A, A _of = 0, and for B,
_{B of = AX S · AY S} , C of = AX S · AY against C
_{S + BX S · BY S,} D of = AX S · AY S with respect to D
Allocate as _{+ BX S · BY S + CX} S · CY S.

The image signal 10 input from the transmission path 101
0 is input to the CPU 106 after the image sequence identification signal is extracted by the interface unit 102. Upon receiving the image sequence identification signal, the CPU 106 searches the address table 110, outputs an offset address value corresponding to the image identification signal to the counter 103, and presets the counter 103. Further, in the interface unit 102, the image data is converted into image data in pixel units, and a clock signal synchronized with the image data is created and input to the counter 103 and the image memory 104.

The image data input to the image memory 104 is written into an address of the image memory 104 output from the counter 103 by a clock signal. afterwards,
The counter 103 is incremented by a clock signal. In this way, one frame of each image sequence is written in a predetermined address of the image memory 104. Thereafter, the same series of image data is stored in the image memory 104.
Overwritten within the given address.

On the other hand, the CPU 106 stores the image memory 10 in the display unit 105 at the address of the display memory 107 corresponding to the coordinates at which each pixel of the image of each image is to be displayed.
Then, the address value of each pixel of the image of each image series to be displayed stored in 4 is written. For example, as shown in FIGS. 2 and 3, the address in the image memory 104 that stores the information of the pixel PA is ｛A _of + AX _S (ay _S
−1) + ax _S −1}, and {B _of + BX _S (by _S −1) + a for the pixels PB, PC, and PD, respectively.
x _S -1}, {C _of + CX _S (cy _S -1) + cx _S −
1}, {D _of + DX _S (dy _S −1) + dx _S −1}.

Further, on the display unit 105 where the pixel PA is to be displayed.
Coordinates (ax_d , Ay_d ) Display memory 107 corresponding to
Is, as shown in FIG. 4 and FIG._d 
・ (Ay_d -1) + ax_d -1} and the pixel P
$ X for B, PC, PD_d ・ (By_d 
-1) + bx_d -1｝, ｛X_d ・ (Cy_d -1) + cx
_d -1｝, ｛X_d ・ (Dy_d -1) + dx_d -1｝
You.

That is, the CPU 106 controls the display memory 107
Address @ X_d・ (Ay_d -1) + ax_d -1｝
Address of corresponding pixel PA in image memory 104
｛A _of+ AX_S (Ay_S -1) + ax_S Write -1｝
No. Similarly, the address $ X of the display memory 107_d ・ (B
y_d -1) + bx_d -1} is the address of the pixel PB {B_of
+ BX_S (By_S -1) + a_S -1} to the address {X
_d ・ (Cy_d -1) + cx_d -1｝ pixel PC address
｛C_of+ CX_S (Cy_S -1) + cx_S-1｝
Furthermore, address @ X_d (Dy_d -1) + dx_d -1｝
Address @D of pixel PD_of+ Dx_S ・ (Dy_S -1) +
dx_S Write -1 @. As described above, the CPU 106
Instructed to display image data on display unit 105
For all addresses of the display memory 107 corresponding to the display area,
Then, writing is performed as described above.

If the display positions of the image series to be displayed on the display unit 105 overlap,
In accordance with the instruction input from the MMI 109, only the storage address of each pixel of the image sequence to be displayed in the overlapping image sequence in the image memory 104 is written in the corresponding address of the display memory 107.

As a result, various synchronization signals are output from the read control unit 108 to the display unit 105, and the contents of the display memory 107 are sequentially read word by word in synchronization with these synchronization signals. Since the output from the display memory 107 is used as a read address of the image memory 104, if only the address value of the pixel to be displayed is stored in the display memory 107 as described above, the image memory 10
From 4, only the actually displayed pixel data is read out and displayed on the display unit 105.

Thus, even in the overlap area, the pixels of the image sequence corresponding to the address value written in the display memory 107 are always displayed stably.

The image signals of each series are sequentially overwritten in the addresses of the image memory 104 designated by the CPU 106 in frame units. However, the display unit 10
As long as the display position in 5 and the selection of the display image sequence in the overlap area are not changed, the display memory 1
07 does not need to be rewritten, and a stable image display can be obtained. <Another Embodiment> FIG. 6 is a block diagram showing a configuration of an address generating means according to another embodiment of the present invention. Here, FIG.
As shown in (1), a plurality of image sequences A, B, and C are compressed during one frame period (1/30 second), inserted into the same number of slots, and used for a transmission path that is transmitted. Things. The signal on the transmission path 111 is added with a frame synchronization signal for obtaining a frame period and a slot synchronization signal for dividing a slot.

In FIG. 6, the interface unit 112
Converts a transmission signal input from the transmission path into a pixel-based image signal and simultaneously generates a clock signal synchronized with the pixel signal. Further, a frame synchronization signal and a slot synchronization signal are extracted to create a frame signal and a slot signal.

The counter 113 is provided with the image memory 10 described above.
4, and outputs a different address for each image sequence. On the other hand, the counter 114 is connected to a lower address of the image memory 104, and the maximum number that can be counted by the counter 114 is set to be equal to or larger than the maximum value of the number of pixels of each image sequence.

The transmission path 111 is connected to the interface section 112.
When a frame synchronization signal is input from the interface unit 112, the interface unit 112 outputs a frame signal to the counter 113,
The counter 113 is preset to a predetermined value. continue,
When the slot synchronization signal is input, the interface unit 112 outputs a slot signal to the counter 113 and the counter 114. The counter 113 counts the slot signal, while the counter 114 is preset to a predetermined value by the slot signal.

Next, when an image signal of the image sequence A is input, the interface unit 112 outputs image data in pixel units to the image memory 104. This image data is supplied to the counter 113 and the counter 1 in synchronization with the clock signal.
The data is written in the address of the image memory 104 addressed by the address value output from. When the writing of the image data is completed, the counter 114 is incremented by the clock signal. In this way,
An image of one frame of the image sequence A is written in a predetermined address of the image memory 104.

After the writing of the image sequence A is completed, the interface unit 112 creates and outputs a slot signal from the slot synchronization signal, and increments the counter 113. Thereby, the write upper address of the image sequence B is set. On the other hand, at this time, the counter 114 is reset. Thereafter, as in the case of the image sequence A, writing of the image sequence B is performed, and subsequently, the image sequence C is written. After the writing of the image data of each of the series A, B, and C in one frame period is completed, the counter 113 is preset by the frame synchronization signal, and the writing in the next frame period is started.

The image data written in the image memory 104 in this manner is read out under the control of the reading control unit 108 and displayed on the display unit 105 as in the first embodiment.

In this embodiment, since the CPU is not involved in the generation of the write address of the image data of each image series, high-speed processing is possible.

As described above, according to the present embodiment, when a plurality of series of images input through a transmission path are identified, and when these plurality of series of images are stored, writing of an image to be written is performed. By generating the address area without duplication for each image sequence, any number of sequence images out of a plurality of sequence images transmitted on the transmission path can be displayed at any position on the display screen.

[0034]

As described above, according to the present invention, there is an effect that a plurality of series of image data input in a time series can be easily displayed at an arbitrary position on a display screen.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an image display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing display coordinates of each image sequence and display coordinates of each pixel in the embodiment.

FIG. 3 is a diagram illustrating a data configuration of an image memory that stores each pixel data of each image sequence in the present embodiment.

FIG. 4 is a diagram showing display coordinates of each image sequence on a display screen and display coordinates of each pixel in the embodiment.

FIG. 5 is a diagram showing a data configuration in a display memory of pixel data displayed on a display screen in the embodiment.

FIG. 6 is a block diagram illustrating a configuration of an image display device according to another embodiment of the present invention.

FIG. 7 is a diagram showing an image transmission format according to another embodiment of the present invention.

FIG. 8 is a diagram showing a usage form of a general multiplexed image signal.

FIG. 9 is a block diagram illustrating a configuration of a conventional image display device.

FIG. 10

FIG. 12 is a diagram showing an overlapping state of images, which is a problem of the conventional example.

FIG. 11

FIG. 13 is a timing chart showing a relationship between an image overlap state and a transmission image sequence, which is a problem of the conventional example.

[Explanation of symbols]

 101, 111 Transmission line 102, 112 Interface unit 103, 113, 114 Counter 104 Image memory 105 Display unit 106 CPU 107 Display memory 108 Readout control unit 109 Man-machine interface (MMI) 110 Address table

Continuation of the front page (56) References JP-A-2-231627 (JP, A) JP-A-63-287889 (JP, A) JP-A-64-27087 (JP, A) JP-A-2-1900 (JP, A) , A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/14 G06T 1/60 H04N 5/66 H04N 5/907

Claims (2)

(57) [Claims] 1. A identification means for identifying the image source of the respective image data inputted in time series from a plurality of image supply source in response to identification by the identification means, the image source per each image data Having an address corresponding to the coordinates to be displayed on the display screen,
The image storage means displayed at each coordinate of the display screen
Location of each pixel of the corresponding image data stored in
Address storage means for storing an address corresponding to each of the coordinates, and each position of the display screen in synchronization with the display on the display screen.
Sequentially reading the memory location which is stored in the address of the address memory means corresponding to the target, the image storage unit
It reads the corresponding pixel from the storage position and a display control means for displaying on the display screen, before the respective image data from the plurality of image sources
An image display control device for displaying an image on a display screen . 2. A method for identifying a source of each image data input in time series from a plurality of image sources, storing the identified image data in an image memory for each image source, and displaying the image data on a display screen. Has an address corresponding to the coordinates to be displayed
Each address of the display memory has a corresponding
The image data stored in the image memory and displayed on the coordinates.
The storage position of each pixel of the data is stored, and the display of the display screen is synchronized with the display on the display screen.
Stored in the address of the display memory corresponding to each coordinate
Sequentially read out the stored storage locations, and
The corresponding pixel is read from the storage position and the plurality of pixels are read out .
Displaying each of the image data from the image sources on the display screen.