JPS6333711B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scan conversion device used when displaying the same image data between image display devices having different video signal standards.

Display devices used as image display terminals in electronic computer systems use video signal standards different from consumer television broadcasting standards in order to enable large-capacity display and high-resolution display. For example, graphic display devices have video signal standards that differ from consumer television broadcast standards in that the video frequency is higher, the number of horizontal lines is increased, and the vertical frequency is lower. Therefore, when a display device manufactured in accordance with television broadcasting standards, such as a video projector, color monitor, or video tape recorder, is used as a high-resolution display terminal device, a scan conversion device is required.

A conventional scan converter is shown in FIG. This device is a scan conversion device that allows image information displayed on a high-resolution display device to be displayed on a consumer TV device. Note that, to simplify the explanation, a case where black and white image information is displayed is shown. 1 is a consumer TV device, 2 is a high resolution CRT
It is a display. Said CRT display 2
Image information to be displayed is stored in the first storage circuit 21. This image information is sequentially read out from the first storage circuit 21 at a timing compatible with the video signal standard of the CRT display 2 and output to the CRT display 2. 22 is a memory control circuit that controls writing of image information into the first storage circuit 21 and reading of image information from the first storage circuit 21. Reference numeral 23 denotes a timing signal generation circuit which supplies an image information readout timing signal to the memory control circuit 22 and also outputs an image information readout timing signal to the CRT.
This circuit outputs horizontal and vertical synchronization signals to the display 2. 3 is a scan converter. The scan converter 3 is a second storage circuit 3
1, a second memory control circuit 32, a second timing signal generation circuit 33, and an encoder 34. The second memory circuit 31 is a memory circuit into which image information read from the first memory circuit 21 is written. The second memory control circuit 32 writes image information to the second storage circuit 31;
and a circuit that controls reading of image information from the second storage circuit 31. The second write control circuit 32 also controls reading out image information written into the second storage circuit 31 from the first storage circuit 21. The second timing signal generation circuit 33 outputs the read timing signal of the second storage circuit 31 to the memory control circuit 32.
Output to.

Further, this timing signal generation circuit 33 is arranged vertically.
And outputs a horizontal synchronization signal to the encoder 34. This encoder 34 is connected to the second storage circuit 31
This circuit creates a video signal from the image information read out from the TV and vertical and horizontal synchronization signals, and outputs it to the TV device 1.

Now, conventional scan converter 3 having the above configuration
performs scan conversion by the operation described below.
First, the memory control circuit 32 sends address information and a read signal (READ signal) to the first storage circuit 21 in order to read image information displayed on the TV device 1 from the first storage circuit 21 . This readout is performed independently of the readout by the first memory control circuit 22 (readout of image information to the CRT display 2). For this reason, the first
When data is transferred from the second storage circuit 21 to the second storage circuit 31, the transmission of image information to the CRT display 2 is suspended. On the other hand, the second memory control circuit 32 simultaneously sends a write signal (WRITE signal) to the second memory circuit 31. The image information read from the first memory circuit 21 is written into the second memory circuit 31 by this signal. In this way, when the image information for one screen displayed on the TV device 1 is stored in the second storage circuit 31, this image information is stored on the TV of the TV device 1.
The data are sequentially read out from the second storage circuit 31 at timings that comply with broadcast standards. Address information and a read signal (READ signal) at the time of reading are given by the second memory control circuit 32. Further, the read timing signal is given to the second memory control circuit 32 by the second timing signal generation circuit 33.

The outline of the conventionally used scan converter has been explained above. In this scan converter, image information for one screen is written to the memory circuit within the scan converter, and then that image information is output to the display device. Therefore, it is impossible to display real time. Therefore, even if the image information to be displayed changes, the new image information is not displayed on the display device.

The present invention solves this problem and provides a scan conversion device for displaying image data displayed on a high-resolution display in real time on a display device having a video signal standard different from that of the display.

The scan conversion device of the present invention includes a first storage circuit that stores image information displayed on a first image display section, and a first storage circuit that stores image information displayed on a first image display section; and a first timing signal generation circuit that outputs a timing signal for reading image information from the image display device, and the image information output from the first storage circuit to the first image display section. , a device for obtaining a timing signal output from the first timing signal generation circuit and displaying this image information on a second image display section having a video signal standard different from that of the first image display section; It is. The scan conversion device of the present invention includes a second storage circuit in which image information outputted from the first storage circuit to the first image display section is written, and a readout device outputted from the first timing signal generation circuit. Obtaining the timing signal, the second
a write control circuit that controls writing to the storage circuit; a readout control circuit that controls reading of the second storage circuit; and a second timing signal generation circuit for outputting to the circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below by giving an example of a scan conversion device according to the present invention.

FIG. 2 is a block diagram when a video projector 12 having a video signal standard of the television broadcasting standard is connected via the scan converter of the present invention.
4 is a high-resolution graphic display device (hereinafter referred to as an image display device).

2 is a first image display section. This first image display section 2 uses a high resolution CRT display. 5 is a microprocessor that controls the entire image display device 4; 6 is a control program memory that stores a control program executed by the microprocessor 5; and 7 is a working memory. A communication adapter 8 is an adapter for connecting the image display device 4 and a host computer (not shown). 21 is a first memory circuit;
Image information displayed on the CRT display 2 is stored. This first storage circuit 21 is composed of a three-sided refresh memory that stores color information of red (R), green (G), and blue (B) necessary for seven-color display. Refresh memory for each color is
For example, each dot on the display screen of the CRT display 2, which is composed of 1024 dots vertically and 1024 dots horizontally, has a storage location of 1 bit. In other words,
One dot pattern information on the screen of the CRT display 2 is stored in a total of 3 bits of R, G, and B. 24 is a parallel-to-serial converter. Parallel data read out from the first storage circuit 21 is converted into serial data by the parallel to serial converter 24 and output to the CRT display 2. The method of reading image information as parallel data is effective in that a storage element with relatively slow access time can be used in the first storage circuit 21. 23 is a first timing signal generation circuit. This first timing signal generation circuit 23 generates a horizontal synchronization signal (H.SYNC) and a vertical synchronization signal (V.SYNC) given to the CRT display 2.
SYNC) is a circuit that reads image information from the first storage circuit 21 in synchronization with raster scan and outputs a timing signal for parallel-to-serial conversion. The first timing signal generation circuit 23 stores, for example, 8-bit data in parallel in the first storage circuit 2.
When reading from 1, one pulse of the read signal is output to the memory control circuit 22 every time eight pulses of the timing signal are output to the parallel-to-serial converter 24. 22 is a memory control circuit. This memory control circuit 22 is a circuit that controls reading of image information from the first storage circuit 21 in synchronization with the readout signal output from the first timing signal generation circuit 23. 9 is a video bus. The video bus 9 includes R, G, and B image information read out from the first storage circuit 21, horizontal and vertical synchronization signals output from the first timing signal generation circuit 23, and A read timing signal is included. 10 is a scan conversion device of the present invention. The scan conversion device 10 receives R, G, and B image information and the read timing signal from the video bus 9. In addition to this scan conversion device, a hard copy device (not shown) and the like are connected to the video bus 9. 12 is a second CRT display having a different video signal standard from that of the CRT display 2;
This is an image display section. In this embodiment, a consumer video projector having a video signal standard of the television broadcasting standard is used.

FIG. 3 is an internal block diagram of the scan converter 10 of this embodiment. 101 is a second storage circuit. This second storage circuit 101 is a circuit into which image information sent to the video bus 9 is written. This second memory circuit 101 is also a refresh memory and has the same configuration as the first memory circuit 21, but
The storage capacity is smaller than that of the first storage circuit 21. This is because the display capacity of the video projector 21 is small and it is impossible to display all image information. Therefore, the image information taken into the second storage circuit 101 is a selected part of the image information displayed on the CRT display 2. 102 is a write control circuit. This write control circuit 102 is connected to the video bus 9
A read timing signal is obtained from the memory circuit 101, and a write address and a write signal (WRITE signal) are output to the second memory circuit 101. 103 is an X-direction start address register, 104 is a Y-direction start address register, 105 is an X-direction display length register, and 106 is a Y-direction display length register. These registers 103, 104, 10
The area of the image information to be taken into the storage circuit 101 is specified by the position information included in 5 and 106. 107 is a second timing signal generation circuit. This second timing signal generation circuit 1
07, horizontal and vertical synchronization signals (H.SYNC, V.SYNC) of the video projector 12, and a timing signal for reading image information from the second storage circuit 101 at a timing synchronized with this raster scan. Output. Furthermore, this timing signal generation circuit 107 also outputs a timing signal for the parallel to serial converter 109. 108 is a read control circuit. This read control circuit 108
This circuit outputs a read address and a read signal (READ signal) to the second memory circuit 101 in synchronization with the read timing signal output from the timing signal generation circuit 107. Also,
This readout control circuit 108 includes a video bus 9 to prevent contention between writing and reading out image information.
Reference numeral 109 to which a read timing signal (outputted from the first timing signal generation circuit 23) is inputted is a parallel-to-serial converter. This parallel-to-serial converter 109 is a circuit that converts parallel image data read from the second storage circuit 101 into serial data. 110 is an NTSC encoder. this
The NTSC encoder 110 is a circuit that synthesizes an NTSC standard video signal from image information of three colors R, G, and B, and horizontal and vertical synchronization signals, and outputs the synthesized video signal to the video projector 12. 111 is a display position changing circuit. This display position changing circuit 111
This circuit rewrites the contents of the direction start address register 103 and the Y direction start address register 104.

Next, the operation of the scan conversion device 10 of this embodiment will be explained. First, FIG. 4 shows the area of image information taken into the present scan converter 10. 20 is CRT
The screen 120 of the display 2 shows the area to be captured. The display screen of CRT display 2 is
For example, 1024 dots horizontally and 1024 dots vertically, total 1048576
Consists of dots. As mentioned above, this one dot corresponds to one bit of each of the R, G, and B refresh memories of the first storage device 21. x _s and y _s are coordinates indicating the starting position of the selected area. x _l and y _l are values that specify the size of the selected area. These x _s , y _s , x _l , and y _l values are input by the display position change circuit 111 to the X direction start address register 103, the Y direction start address register 104, and the X direction display length register 10, respectively.
5. Stored in the Y-direction display length register 106.
On the other hand, the write control circuit 102 includes a counter, and the first timing signal generation circuit 23
The count is increased (or decreased) by applying a readout signal outputted from the video bus 9 from the video bus 9. The read signal from the first timing signal generation circuit 23 also includes an initial signal (indicating the start of displaying one frame).
Counting up in the write control circuit 102 starts from the time when this initial signal is generated. On the other hand, from the values of x _s and y _s held in the registers 103 and 104, a value S is obtained that indicates from which pulse number the read signal is generated to start reading. Also, this value S and registers 105 and 10
The value E at the end of reading can be obtained from the values of x _l and x _l held in 6. The write control circuit 10
2 is provided with a comparator, and the area 120 to be read is determined by comparing the count number of the read signal with the values of S and E. While image information corresponding to this area 120 is being sent to the video bus 9, a write address and a write signal (WRITE signal) are output from the write control circuit 102 to the second storage device 101, and as a result, Image information is stored in the second storage device 101. Note that the write address and write signal are output in synchronization with the read timing signal output from the first timing signal generation circuit 23. Next, the second memory circuit 1
The image information stored in 01 is sequentially read out by the readout control circuit 108. As mentioned above, the read control circuit outputs the read address and the read signal (READ signal) to the second storage circuit 101, and the read address circulates within a certain range. As a result, image information is cyclically read out from the second storage circuit 101.

Since the image information is read out from the second storage circuit 101 in the form of parallel data, this data is converted into serial data by the parallel to serial converter 109. The converted image data is combined with horizontal and vertical synchronizing signals by the NTSC encoder 110 and output to the video projector 12 as an NTSC standard video signal. The image information displayed on the video projector 12 is transferred to an X-direction start address register 103 and a Y-direction start address register 104 by a display position change circuit 111.
By rewriting the contents of , it is possible to select from any area of the screen displayed on the CRT display 2. Writing of image information from the video bus 9 to the second storage circuit 101 as described above is always performed. At this time, in order to avoid conflict between the operation of writing image information into the second memory circuit 101 and the operation of reading image information from the second memory circuit 101, these operations are performed at the timing shown in FIG. ing. First, image information in the image display device 4 is read out at a timing synchronized with the raster scan of the CRT display 2. In this embodiment, the image information is read out as parallel data, so the image information is read out once every 8 dots, for example. The timing of this readout is determined by the first timing signal generation circuit 2.
It is controlled by a read timing signal output from 3. The memory control circuit 22 that has received this read timing signal outputs a read address and a read signal (READ signal) to the first memory circuit 21, and accesses this memory circuit 21. Next, the write control circuit 102 of the scan conversion device 10 sends the write address and write signal to the second storage circuit 101 in synchronization with the read timing signal (outputted from the first timing signal generation circuit 23). Output. At this point, the image information read out from the first storage circuit 21 has been output to the internal bus (not shown) of the scan conversion device 10 via the video bus 9, so this image information has been read out from the first storage circuit 21. It is written to a predetermined address in the memory circuit 101. After this write operation is completed, a read operation is subsequently performed. The read operation is performed during a period when the read timing signal is not output from the first timing signal generation circuit 23. For this reason, the read control circuit 103
The output of this read timing signal is monitored. During this period, the second timing signal generation circuit 1
When the read timing signal is output from 07, the read control circuit 108 outputs a read address and a read signal (READ signal) to the second memory circuit 101. In response to this signal, image information is read from a predetermined address in the second storage circuit 101. This read image information is stored in a data register in the parallel-to-serial converter 109 and converted into serial data at a timing synchronized with the raster scan of the video projector 12. in this case,
The second memory circuit 101 is required to have a memory element with a relatively short access time, but according to the inventor's tests, the image information displayed on a high resolution display of 1024 dots x 1024 dots can be stored in accordance with the television transmission standard. When outputting to a display device, it is sufficient to use a memory element with an access time of 200 ns.

As another embodiment of the present invention, the second memory circuit 1
There is also a scan conversion device in which the storage capacity of 01 is the same as the storage capacity of the first storage circuit 21, and all the image information output from the first storage circuit 21 is read into the second storage circuit 101. In the case of this scan conversion device, the image information output to the second display device is selected by the readout control circuit and
is read from the memory circuit 101 of.

Furthermore, in the detailed embodiment, the image information is read and written to the storage circuit in the form of parallel data;
This may be in the form of serial data. At this time, the read timing signal is output at the timing of dot display.

Furthermore, the two memory circuits 21 and 101 may not be configured to store one dot as one bit, but may be memory circuits that store character codes.

The scan conversion device of the present invention has been described in detail above, but if the scan conversion device of the present invention is used, it can be used in consumer image display devices, such as video projectors, etc.
A TV device, a video tape recorder, etc. can be easily connected as the end of a computer system, and large-capacity, high-resolution image information can be displayed in real time.

[Brief explanation of drawings]

FIG. 1 shows a conventional scan conversion device using a scan converter, FIGS. 2 and 3 show an embodiment of the scan conversion device of the present invention, and FIG. 4 shows a CRT display device. A diagram showing the display screen of
FIG. 5 is an operation timing chart of the present invention. 1...TV device, 2...CRT display, 4
...Image display device, 21...First storage circuit, 2
2... Memory control circuit, 23... First timing signal generation circuit, 24... Parallel to serial converter, 9... Video bus, 10... Scan conversion device, 101... Second
memory circuit, 102... write control circuit, 10
3...X direction start address register, 104
...Y direction start address register, 105...
...X direction display length register, 106...Y direction display length register, 107...Second timing signal generation circuit, 108...Readout control register, 10
9...Parallel-to-serial converter, 110...NTSC encoder, 111...Display position conversion circuit, 12...Video projector.

Claims (1)

[Claims] 1 a first storage circuit for storing image information displayed on a first image display section; and a first storage circuit for reading image information from the first storage circuit in synchronization with raster scan of the first image display section. a second memory connected to an image display device including a first timing signal generation circuit that outputs a timing signal, and into which image information to be output from the first memory circuit to the first image display section is written; a write control circuit that obtains a read timing signal output from the first timing signal generation circuit and controls writing in the second storage circuit; and a display for displaying image information read from the second storage device. a second image display section having a video signal standard different from that of the first image information; a readout control circuit that controls reading of the second storage device; and a video signal standard of the second image display section. a second timing signal generation circuit that outputs a readout timing signal suitable for the readout control circuit to the readout control circuit.