JPS60159789A - Display memory control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display memory control method, and particularly to a display memory control method in which image data is developed in a display memory using a bitmap method.

[Armor] A display system that displays images including characters and figures using the bitmap method on a display device that requires display refresh, such as a U1 blind cathode ray tube (11:RT), forms all the pixels that make up the display screen. Pixel data is developed into display memory. This display memory is generally constituted by a RAM.

When the resolution of a display image is improved, the time required to develop all image data into the display memory becomes longer in proportion to the square of the resolution. Also, in order to maintain a predetermined flicker-free image quality, write accesses to the display memory preferably avoid read periods to the display device.

Conventionally, display memory (video RAM) is controlled by a display control device (CRT) independently of system (host computer) control.
In most cases, the system is managed by a controller (controller). In such a system, writing to the display memory is performed in periods not involved in display, ie, blanking periods and blanking periods, avoiding the effective display period of the image signal. Due to this limitation on the writing period, a system with high image quality requires time to develop image data for one screen.

If write access is performed by interrupting the display period in order to shorten the development time, the display will flicker and the display quality will deteriorate.

Tokuko Sho 5B-3 is a conventional technology that satisfies both of these requirements.
[Display memory time division usage method J] described in Publication No. 8782
There is. This divides the display period of one pixel into two subcycles, one of which reads out the display memory.
On the other hand, it is used for writing. However, systems that require high resolution must use circuit elements that can operate at extremely high speeds, which is currently difficult to achieve due to hardware conditions.

Since the bitmap method can handle both characters and graphics, it is advantageous for displaying images containing a mixture of both characters. However, with the current state of technology, only RAM with an addressable area of about 128 bytes can be used as display memory, so a system that can use a single VRAM chip to handle various modes in addition to the mixed character/graphic mode has not been realized. Not yet. Using multiple VRAM chips allows various modes to be implemented, but complicates address calculations across multiple areas and increases the time required to do so.

1-It is an object of the present invention to overcome the drawbacks of the prior art and to provide a display memory control method that can display high-resolution images with good display quality on a display device.

1-Difference The configuration of the present invention will be described below based on one embodiment.

Referring to FIG. 1, a system to which the display memory control method according to the present invention can be applied is shown, which includes, for example, CR
A display device Wlo, such as T, that requires display refresh is connected to a system bus 14 via a display control device (CRTC) 12. A system memory 18 is also connected to the system bus 14, and the bus 14 is connected to a central processing unit (CPU) 20 as a host machine.

As schematically shown in FIG. 1, the display control device t (CRTtl:) 12 includes an image data control section (GDC) 20 and a display memory (VRAM) 1B. This basically has the function of controlling CRTlo and the function of controlling VRAM 1B. The VRAM 1B is a RAM having a storage capacity capable of storing at least one screen worth of digital image signals.

In the prior art, the CRTC 12 has a parallel buffer 22 on the output 28 side of the VRAM 1B, as shown in detail in FIG.
and a parallel/serial (P/S) converter 24 are connected in this order, and an output 26 of the P/S converter 24 is outputted to the CRT 10 as a video signal VIDEO. VRA III
The input 3o side of 1B is connected to the system bus 14 through GOo 20 and system bus interface (1/F) 32.
interfaced to.

GDG 20 performs VR according to instructions from CPU 20 (7).
The entire CRTC12 including AM 1B, and CRT 1
This is a circuit that controls 0. The address and display data of the VRAM 1B are supplied from the GDC 20 to the old VRA 6 through the bus 3o. In addition, the signal line 34 has
The latch pulse of the parallel buffer 22 is connected to the signal line 36 as P
A dot clock signal that drives the /s converter 24 at a dot frequency is output. Also, for CRT 10,
Video horizontal synchronization signal H9YNC is applied to signal lines 38 and 40.
and vertical synchronization signal VSYNC are output.

The VRAM 113 address and data for drawing are generated by the GtlC 20 according to instructions from the CPo 20, and the VRAM 1B address for display is also generated by the co.
Generated by c20. The display data read from the VRAM 1B is latched into the parallel buffer 22 as parallel data at a speed corresponding to the video signal frequency in the CRT 10. This is converted into a bit-serial video signal by the P/S converter 24 in synchronization with the dot clock on the signal line 3B, outputted from the signal line 26 to the CRT 10 as a video signal VIDEO, and displayed on it as a visible image. Ru.

Figure 3 shows the horizontal synchronizing signal HSYNC and the vertical synchronizing signal V.
A portion 10 of the total video time in the horizontal direction (■) and vertical direction (v) of the rask scan excluding the blanking period indicated by diagonal lines, so as to indicate the range 100 of the display image corresponding to SYNC.
0 is the effective display time. In other words, this shaded area is
This is a part that is not involved in display, and during this period the CPU
Display data is written from 20 to VRAM 1B. Further, the other area 100 is used for actual display, and display data, which is the storage content thereof, is read out from the VRAM 1B and displayed on [RT 10].

According to a typical conventional example, the ratio of the display time to the VRAM write time is 65:35, and at most about 173 seconds of the total time is not used for writing the VRAM Ift. In particular, when dynamic RAM is used as VRAM 1B, the refresh operation takes even more time.
Therefore, the VRAM16 is only used for about 1/4 of the total time.
was not used for writing. Therefore, it takes several seconds to develop one screen's worth of display data into the VRAM 16.

In order to avoid such conventional drawbacks, according to an embodiment of the display memory control method of the present invention, a CR as shown in FIG. 4 is used instead of the CRTC 12 in the system shown in FIG.
TC200 is used. In the apparatus shown in FIG. 4, components similar to those shown in FIG. 2 are designated by the same reference numerals to avoid duplication of explanation. CRTC200 is
VRA 16) First-in first-out memory (FI) on the output 28 side
FO) 202 is provided. This is VRAM
It has a data speed conversion function that outputs data sequentially read out in parallel from ift to the parallel buffer 22 at a speed different from the reading speed.

GDC204t*, CPU 20(7) instruction 2: The entire CRTC12 including VRAM '1B, and C
This is a circuit that controls RT 10. VR from GDC20
Display data is supplied to A old 6 through bus 20B. Further, a latch pulse is outputted to the signal line 34, and a dot clock signal is outputted to the signal line 3B. Also, CR
For T10, a video horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC are output to signal lines 38 and 40, respectively.

The address of VRAM 1B is the address counter 208.
This is counted by the counter clock control section 2.
10. The clock control unit 210 has a GDC.
A retrace signal for display video is supplied from the GDC 204 to the signal line 212, and a VRAM access prohibition signal is supplied to the signal line 214 from the clock control unit 210 to the GDC 204. Also, a signal line 2 is connected from the clock control unit 210 to the FIFO 202.
A shift clock for this purpose is supplied to 1B, and an empty signal is supplied from the FIFO 202 to the clock control unit 210.

In the case of this embodiment, one horizontal scanning line of the displayed image, that is, IH
consists of 1,024 black and white dots, FIFO20
2 is this! In this embodiment, 64 bits of display data are read out in parallel from the VRAM 1B, and the PIFo 202 stores this in 18 register stages. The scanning time for IH is 10.24 microseconds during the effective display period and 3.26 microseconds during the horizontal retrace period, for a total of 13.5 microseconds.

In this embodiment, the clock control 210 has an oscillation frequency of 10M.
It has a Hz oscillator and generates clock pulses with a period of 100 nanoseconds. In the above numerical example, the frequency of the dot clock on the signal line 36 is 100 MHz.

FI from VRAM 1B during the horizontal retrace period as described below.
The display data is read and latched into the FO202, but
The periods of the shift clocks supplied from the signal lines 220 and 21B of the VRAM 1B and the FIF0202 clock control unit 21O, respectively, are therefore approximately 200 nanoseconds. The address counter 208 increments every 200 nanoseconds.

According to this embodiment, the CPo 20 develops display data in the VRAM 18 using the vertical retrace period and the effective display period of the video, and stores the display data in the VRAM 18 during the horizontal retrace period.
The display data is read out for each horizontal scanning line from FIF
Transfer to O202. The data natched by the PIFo 202 is sequentially read out during the next effective display period of the IH, converted into a serial video signal by the PIS converter 24, and supplied to the CRT 10.

As shown by the shaded area 300 in FIG.
YNC blanking period 304 and horizontal synchronization signal H9YNC
(7) Valid display period 310 Nioite VRAM 1B
+,: Display data is expanded. The display data developed in this way is displayed in the blanking period 308 of the horizontal synchronizing signal H9YNC in the effective display period 308 of the vertical synchronizing signal VSYNC, that is, in the non-hatched area 302 of the figure.
During the period, VRAM 16 to FIF in IH unit
It is sequentially read out and latched by O202. PIFo
The 1H display data latched in 202 is supplied to the CRT 10 as a serial video signal VIDEO and displayed in an effective display period 310 in the horizontal scanning period.

This operation is performed as follows. Under normal conditions, the CPU 20 develops display data in the VRAM 1B using the effective display period of each video of 10.24 microseconds. This is done under the control of GDC 204 according to instructions from CPU 20 via system bus 14.

Meanwhile, for each horizontal retrace period of 3.26 microseconds,
In this embodiment, 18 minutes of display data is sequentially read out in 64-bit units from the VRAM IEi to the FIFO 202 and latched. This means that while the blanking signal provided from the GDC 204 to the clock controller 210 is in a significant state, the signals from the clock controller 210 to the signal lines 2168 and 220
This is carried out in synchronization with a shift clock with a period of 100 nanoseconds that is output to . That is, the FIFO 202 is latched by, for example, an odd number pulse with a period of 100 nanoseconds, and the address counter 208 is incremented by an even number pulse, and read latch and address increment are performed alternately every two cycles of this clock. Between the clock control unit 21O and V
RAM 18 Outputs a prohibition signal to the signal line 214 only while reading data to the empty FIFO 202, and outputs a GD
In response, the C204 displays to the cPU 20 that the VRAM 1B is in a write-protected state. Furthermore, if the VRAM 1B is a dynamic RAM that requires a refresh operation, refresh is performed during this period.

In this embodiment, when display data for one horizontal scanning line has been accumulated in the PIFo 202 in this way, a latch pulse is supplied from the GDC 204 to the FIFO 202 and the parallel buffer 22 in the next effective display period, and
The /S converter 24 is supplied with a dot clock having a video dot frequency. As a result, display data is sequentially read out from the VRAM 1B and converted into a serial signal at the dot frequency. This is a CRT 1 as a video signal VIDEO.
0.

When all of the display data stored in the PIFo 202 has been output, an empty signal indicating that the FIFO 202 is empty is output from the PIFo 202 to the signal line 218. In response to this, the clock control unit 210 increments the address counter 208 to update the read address of the VRAM till. In this way, the display data is sequentially read out from the VRAM 1B and the PIF 0202 in units of 1) and is output as a video signal to the CRT ion, and finally display data for one screen is output.

On the other hand, at any time during each of these valid display periods, VRA
Since the M Hl can be accessed from the CPo 20, display data from the CPo 20 can be written and expanded as described above as necessary.

Although the illustrated embodiment is an example in which image data is output to a display device, it goes without saying that the idea of the present invention can be effectively applied to a hard copy output device such as a printer.

-1 According to the present invention, when displaying an image on a display device, the VR provided in the display control device during the horizontal retrace period of the video
Display data for one or several horizontal scanning lines is transferred from the AM to the FIFO, and is sequentially displayed on a display device during the effective display period of the corresponding horizontal scanning. VR
Display data can be expanded from the system to VRAM at any time other than when display data is being transferred from AM to FIFO.

In this way, there is sufficient time available for the system to deploy the display data to VRAM, so that the system
Image data processing can be performed in a short time using M, and high-resolution images can be displayed on a display device with good display quality without display flickering.

In addition, compared to a system that prepares a VRAM that can be accessed from the system in addition to the display VRAM in order to extend the time that the system can access the VRAM, the display memory control system according to the present invention specifically uses the VRAM for this purpose. Since there is no need to provide one, the memory configuration does not become complicated. Therefore, the structure is a cylindrical portion, and the system can be realized at a low cost.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing an example of an image display system to which the display memory control method according to the present invention can be applied; FIG. 2 is a block diagram showing a conventional configuration example of a display control device of the system shown in FIG. 1; 3 is an explanatory diagram showing the image display timing of the device shown in FIG. 2, FIG. 4 is a block diagram showing an embodiment of the display control device to which the display memory control method according to the present invention is applied, and FIG. FIG. 4 is an explanatory diagram similar to FIG. 3 showing the image display timing of the apparatus in FIG. 4; Guo 1v 10, , Display device 12, , Display control device Ift, , VRAM 1B, , System memory 20, , CPU 200, , Display control device 204, , Image data control unit 20B, , , Address counter 210, . . . Counter clock control section Fig. 1 Fig. 2 Fig. 3 Fig. 5

Claims (1)

[Scope of Claims] Control means for controlling an image display device according to instructions from a host machine and displaying display data on the image display device; and first storage means for accumulating display data to be displayed on the image display device. , a second storage means for temporarily storing the display data read out from the first storage means and reading out the stored display data in a first-in, first-out manner; and a second storage means for reading the display data from the second storage means to form a video signal. and a video signal forming means for supplying a video signal to the image display device, and the control means is configured to generate a first video signal during a display prohibition period of the image display.
reads out a predetermined amount of display data for image display from the storage means and transfers it to the second storage means; reads display data from the second storage means during the effective display period of the image display and outputs the image from the video signal forming means; Display memory control characterized in that the first storage means is accessible from the host device except during a period when the first storage means is output as a signal and transferred from the first storage means to the second storage means. method.