JPS59214085A - Signal converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a signal conversion device suitable for use when displaying a natural image on a computer display device that performs high-detail display.

[Technical background of the invention and its problems]

Display devices using CRTs (cathode ray tubes) are roughly divided into two types: natural image display devices such as televisions, and computer displays that display high-definition still images such as character graphics output from computers.

By the way, when trying to display computer output on the former display device, the horizontal scanning frequency (15,734 KHz) and vertical scanning frequency (eoH
z), the number of vertical scanning lines (525 interlaced lines), the composite video signal, and the diameter of the shadow mask of the CRT monitor used (0.63 m). For example, there are only about 1000 alphanumeric kana characters. On the other hand, 3° cannot be displayed.
The latter display device has a higher horizontal scanning frequency (20~
30 KHz), CR, T itself has a high-definition CRT shadow mask diameter (o, 3tsm)
It has a long afterglow phosphor. Therefore, 2000 to 3000 alphanumeric kana characters and 10 kanji characters.
About 00 characters can be half summed, and high-definition display can be achieved. When displaying 1000 alphanumeric and kana characters, it is easy to realize a display device that can be used both for natural images and computer output display.

However, when it is necessary to display characters of 1000 characters or more and display natural images, two types of display devices have conventionally been prepared. Therefore, there are problems in terms of cost and implementation, and there is a demand for a display device that can produce a high-definition surface with more than 1,000 characters with a single display device, and that can be used in common with natural image display. was.

In order to realize this common use, a method is adopted in which the operating frequency of the deflection circuit is switched in accordance with two scanning frequencies: the scanning frequency of the NTSC system and the scanning frequency of the computer output.
A possible method is to guide the NT8C signal to a signal conversion device and convert the signal format and scanning frequency to the same signal format and scanning frequency as the computer output.

The present invention relates to the latter.

[Purpose of the invention]

The present invention has been made in view of the above demands, and is based on the NTS
Display content with C scanning frequency (natural images, videos)
An object of the present invention is to provide an improved signal conversion device required for displaying images on a computer display with high definition.

[Summary of the invention]

The present invention converts an input NTSC composite video signal into a H8YNC, VSYNC signal converter.

It consists of a separator that separates video signals, two sets of frame memories, a sampling pulse generator that generates pulses that serve as strobes for writing data to the frame memories, a counter, and a READ/WRITE gate.
The counter is a quaternary counter that receives VSYNC as a clock input, and outputs a frame memory switching signal every time VSYNC arrives twice. Based on this counter output, the above ELF! READ/VII of data to frame memory via AD/WRITE gate
It has a configuration that controls TE.

As a result, it is possible to display a natural image such as a television screen, a VTR screen, etc. on a computer display, and it is also possible to superimpose and arbitrarily switch between the computer output and the natural image output.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail using the drawings. FIG. 1 is a schematic block diagram showing only the portions related to the present invention extracted from an image display system to which the present invention is adopted. In the figure, numeral 11 is a rusk scan type CRT display device. L'' is a signal conversion device of the present invention. The CB, T display device 11 has a linear input video circuit, and has an input interface for receiving R-G-B separate computer output signals. The signal conversion device L receives the NT8C signal and performs seed signal conversion and same wave number conversion compatible with the computer output signal. Details of the internal configuration etc. are shown in Figure 2.

13 is an OR circuit. The OR circuit 13 is supplied with the computer output and the output of the signal converter L1, and the OR circuit 13 supplies the ORed result to the CRT display device 11.

FIG. 2 is a block diagram showing one embodiment of the present invention, and specifically shows the internal configuration of the signal conversion device 12 shown in FIG. In the figure, 121 is a separator. An NTSC composite signal is applied to the separator 121, where the horizontal synchronization signal (H8YNC), the image orientation M period signal (VSY
NC).

Then, it is separated into a video signal (V IDEO). still,
If the incoming input is a color composite video signal, R, G
・Has a function to separate into three types of video signals (B). 122 is a sampling pulse generator. The sampling pulse generator 122 is configured as described above.
) Receives VSYNC and H8YNC and generates sampling pulses (sp) for accurately writing VIDEO signals into frame memories 123 and 124.

125 is an inverter. Inverter 125 is 8HY
NC is inverted, the valid period of the VIDEO signal is defined, and the VIDEO signal is supplied to the gate circuits 12B and 129.

126 is a counter. Counter 126 is VSYNC
It consists of a quaternary counter that uses VSY as the input clock.
Every time NC arrives twice, the frame memory switching signal (FS
FiL) is output. An inverter 127 inverts (FEEL) this frame memory switching signal.

128 and 129 are gate circuits. Gate circuit 128
, 129 is the above-mentioned VIDEO signal.

Input the sampling pulse (sp), frame memory switching number i (FSEL, ll5I[L), warp, and inverted signal of H8YNc, and frame memory 12.9, respectively.
, 724 with the data to be written.

123 and 124 are frame memories. The frame memory zzs, xz461 has a memory capacity sufficient to store one screen worth of display content sent using the NTSC system. 13o.

131 is a gate circuit, frame memory 123゜124
An address signal (MADR issued from CRTCIJ4, which will be described later) and a frame memory switching signal (FEEL/FEEL) for instructing data to be read from are supplied.

Here, when data is written to the frame memory 123, an instruction is given to read data from the frame memory 124, and when data is written to the frame memory 124, data is read from the frame memory 123. control it as you like. 132 is an OR circuit.

The OR circuit 132 is supplied with data obtained from the frame memories 123 and 12/1, and the ORed output here is supplied to the CRT display'@device 1 as a video signal (VIDEO2).

133 is a clock generator, and 134 is a CI'LT controller (CRTC). The clock frequency of the clock generator 133 is set to a value that satisfies the horizontal scanning frequency (H8YNC) and rJ vertical scanning frequency ff (VSYNC) defined in the CRT display device 11,
C'FLTCrs4. , CnTCts4
Now, based on this frequency, the horizontal synchronization signal (H8YN
C2) and a vertical synchronization signal (VSYNC2).

In addition, gate 13o.

The contents of the read address position specified by CRTCr,v4 are supplied to the OR circuit 132 as the frame memory 123 and 124 outputs.

The operation of the present invention will be explained in detail below.

The NTSC natural image input signal to the signal conversion device 12 is input to the separator 121, and a synchronization signal (H8Y
As described above, the signal is separated into the signal (NC, VSYNC) and the video signal (VIDEO). In the sampling generator 122, based on the synchronization signal separated here, VI
A sampling pulse (sp) is generated to determine the timing at which the DEO signal should be written to the frame memories 123 and 124. The (VIDII!i0) signal following H8YNC is strobed by this sampling pulse and written to a predetermined address in the frame memory 123 (124). Although not shown in FIG. is provided with a column/lower address digitizer for memory writing, and a writing address is specified by a sampling pulse and (SYNC).

The counter 126 is a quaternary counter, and its output is supplied to the gates 12 II and 129 as switching signals for the two frame memories 123 and 124. The inputs of counter 126 are V 8 YNC and VSYNC
When is input twice, a switching signal (FSEL) is output. This is because the NTSC system performs interlaced display, and one screen is constructed by scanning the odd and even fields twice. Therefore, even when writing data to the frame memory 123 (124), when scanning an odd field, the data is written to the frame memory 123 (124).
4) When scanning an even field, the write address counter controls the writing to an even address in the frame memory 123 (124).゜1
24. When writing to the frame memory 123 is completed, that is, scanning of both odd and even fields is completed, a switching signal (FEEL) is output from the counter 126, and write control is automatically transferred to the frame memory 124 side.

Similarly, when scanning of both odd and even fields is completed in the frame memory 124@, write control is automatically transferred to the frame memory 123 side.

For reading data from the frame memory 123 (124), H8YNC2 corresponds to the computer output display interface signal.
, V8YNC2, VIDEO2 is the signal converter @, z2-
This signal is generated as follows.

An oscillation clock matching the scanning frequency of the computer output interface is generated by a clock generator 133,
Supplied to CRTCZJ4.

In the known CRTC 134, the horizontal scanning frequency and vertical scanning frequency synchronization signals H8YNC2 and VSYNC2 defined by the computer output interface are generated, and the read memory address (MADR) is specified by the relative input. The contents of the frame memory 123 (124) are read out and output as a video signal (VIDEO2').

When reading the frame memory 123 (124), the read signal is a signal (F8E
Under the control of L), the contents of the frame memo 2 IJ J z 4 (J z s ), which is different from the frame memory 123 (124) in which the writing operation of the natural image input signal is being performed, are read out. There is. Normally, the scanning frequency of the computer output interface signal side is set higher than that of the natural image input signal, so the frame memory 123 (124)
The read operation ends earlier than the write operation to the frame memory 124 (123), and the contents of the frame memory 124 (123) that were being read at that time are read out again from the beginning and displayed on the CR, T display device 11. Frame memo I of natural image input signal
When the write operation to J z z s (z 4) is completed, the read operation is shifted to the frame memory 123 (124) where the write operation was being performed until just before, under the control of the frame memory switching signal (FEEL). Then, the next screen is displayed.

Display device 114 from the signal conversion device #LJ mentioned above
It goes without saying that the corresponding signal can be supplied in either interlaced display mode or non-interlaced display mode, and is realized by setting parameters for CB/T0134.

Although the present invention has been described above only in the case where it is applied to a CRT display device, it can also be applied to a video projector that uses the Rusk scan method and a liquid crystal display that uses a connection interface similar to that of a CRT display device.

〔Effect of the invention〕

As described above, according to the present invention, a computer display device that performs high-definition display can display natural images such as television screens and VTR images. or,
In addition to superimposing display of computer output and natural image output, it is also possible to arbitrarily switch between computer output display and natural image output display.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing only the parts particularly related to the present invention extracted from an image display system to which the present invention is adopted, and FIG. 2 is a block diagram showing an embodiment of the signal conversion device according to the present invention. It is. 11...CR, T display device, and E...signal conversion device, IJ, 1.92...OR circuit, 121...
Separator, 122... sampling pulse generator,
123゜124... Frame memory, I26... Counter 125.127... Inverter, 128, 12
9゜130.131...Gate circuit, I33...Clock generator s I J4''/CRT controller (CRTC). Applicant's representative Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] Receives NTSC composite video signals, horizontal synchronization signals,
a separator that separates the vertical synchronization signal and the video signal; a sampling pulse generator that generates a sampling pulse that serves as a device when writing the video signal to the frame memory using the horizontal synchronization signal and vertical synchronization signal; a frame memory, a counter that receives the vertical synchronization signal output from the separator and generates a signal for switching write or read operations for the plurality of frame memories, and receives the video signal output from the separator; A first gate circuit that controls writing of data to the plurality of frame memories based on the counter output, and a logic of data obtained from the plurality of frame memories based on the counter output, which receives a memory address supplied from the outside as an input. and a second gate circuit that calculates the sum.