JPS63141462A - Scan converter - Google Patents

Abstract

PURPOSE:To display different kinds of pictures by one set of monitor by reading video signals asynchronous with each other and having different frequencies such as TV and text patterns while being unified into a pattern of higher frequency and displaying the result on the monitor. CONSTITUTION:At the write to a picture memory 18 at first, the image from an image pickup device 14 is separated into a picture signal PIG and a picture synchronizing signal PSY by a picture processing unit 16, the picture synchronizing signal PSY is converted into an address of the picture memory 18 by an XY address generator 17 and the picture signal PIG synchronously therewith is stored in an address corresponding to the picture memory 18. Then in reading a picture from the picture memory 18, a teletext synchronizing signal TSY outputted from a computer 19 asynchronously with the address generated from the XY address generator 17 is used to allow the storage location stored in the picture memory 18 by the XY address generator 20 and then the picture signal PIG is read as a picture signal MPS.

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Application Field The present invention relates to a scan converter for displaying two systems of video signals controlled by different synchronous frequencies on the same video monitor.

・〈Prior art 2〉 Fig. 4 is a block diagram showing the configuration of a conventional image display device.

The computer 10 receives character information such as a program from the keyboard 11, and displays this on the text CRT 12 as, for example, character information with one pixel being one bit.

On the other hand, the image processing device 13 is, for example, an industrial television (ITV).
An analog gray scale image is inputted from an image pickup device 14 such as a computer 10, which is converted into a digital value of 8 bits per pixel, for example, and outputted to a monitor CRT 15 upon receiving a control signal from a computer 10.

In this case, text 1 to CRT12 have a horizontal synchronization frequency of 26.016KI-1z and a vertical synchronization frequency of 5, for example.
4.65Hz, pixel signal representing one pixel is 21, 64
It is controlled by a control signal of 5M1-Iz, which has 640 dots in the horizontal direction of the screen and 512 dots in the vertical direction.
The screen is made up of pixels.

For example, the CRT 15 has a horizontal synchronization frequency of 15.7 Kl-1z and a vertical synchronization frequency of IJ.
The Ju++Zs picture system frequency is controlled by a control signal of 6 MHz, resulting in a screen consisting of 320 dots in the horizontal direction and 240 dots in the vertical direction.

Therefore, the text CRTI 2 and the monitor CRT 15 are independently controlled at different synchronization frequencies.

<Problems to be solved by the invention> However, in such conventional image processing devices, since the synchronization signals are different for text display and image display, a monitor corresponding to each is required, resulting in high costs. It also has the disadvantage of requiring extra space.

<Means for Solving the Problems> In order to solve the above problems, the present invention provides a dual port memory in which an image captured by an image pickup device is converted into an image signal by an image processing device and inputted; a first address generator that converts an imaging synchronization signal from the image processing device into Atonosu of the dual port memory and writes it; and a text synchronization signal from a computer having a synchronization frequency different from that of the imaging synchronization signal. a second address generator that converts the input information into an address of the dual port memory and reads it out; a text video signal whose input information is converted by the computer; and an image signal of the dual port memory that has the same frequency as the text synchronization signal; The apparatus further includes an adding means for adding these input signals and outputting the result as an output image signal, and outputs the output image signal and the text synchronization signal to a video monitor.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The image processing device 16 receives the image signal IMG, which is an analog grayscale image, from the image carrier 14, converts it into an image signal PIG using a plurality of bits without representing a grayscale image, and outputs the image signal PIG. The synchronizing signal PSY (horizontal synchronizing signal 1-ISYl, VSYl and pixel signal PXL1 representing one pixel) is separated and output.

17 is a ×Y address generator, which receives horizontal synchronizing signals 1'SYl, vSYl and pixel signal P from the image processing device 16.
When XL1 is input and the image signal @PIG is written into the memory 18, addresses in the X direction and Y direction are generated.

18 is an image memory, specifically a dual port RAM (Dual port RAM) whose address can be accessed from two ports.
Port RAM), for example, S-D
PRAM (HD63310) manufactured by Hitachi, Ltd. is used.

On the other hand, from the keyboard 11, text 1 such as a program is input.
~ is input to the computer 19, and the computer 19 receives the text synchronization signal TSY (horizontal synchronization signal 1-(S Y
2. The vertical synchronizing signal VSY2 and the pixel signal PXL2> representing one pixel are output to the xY address generator 20, and at the same time, the text video signal TXS is output. These synchronization signals and text video signals each usually consist of 1 bit, 1 to 1 bit, but in the case of color, they consist of 3 bits: R, G, B.

×Y address generator 20 receives horizontal synchronizing signals HSY2, VSY2 and pixel signal PXL from computer 19.
2 is input to generate addresses in the X and Y directions for reading data stored in the image memory 18.

The image signal MPS read out from the image memory 18 at the same timing as the text video signal TXS and the computer 1
The text video signals TXS from 9 are both input to the adder circuit 21, which adds them together and outputs the result to the D/Δ converter 22.

For example, the adder circuit 21 is composed of an OR gate as shown in the figure, and when the text video signal TXS is at a high level "H" (characters present, positive logic), the outputs of the adder circuit 21 are all 'defective', and the text is The video signal TXS is output with priority.

These XY address generator 17.20, image memory 1
8. An adder circuit 21 and a D/A converter 22 constitute a scan converter 23.

The video output of the D/A converter 22 and the text synchronization signal QTSY from the computer 19 are both input to the video monitor 24, and the image from the 1fla machine 14 and the text from the combination 7-ter 19 are simultaneously displayed on one video monitor 24. Is displayed.

Next, the operation of the 1-17 scan converter configured as above will be explained.

First, the writing to the image memory 18 is completed by the erasing device 14.
The image processing device 16 separates the captured image into an image signal @PTG and an image synchronization signal PSY, and the image synchronization signal PSY is converted into an address in the image memory 18 by an XY address generator 17, and synchronized with this. The image signal PIG is stored in the corresponding address on the image memory 18.

Next, when reading an image from the image memory 18,
The address generator 17 asynchronously generates the storage location stored in the image memory 18 using the 7 kiss 1 to synchronization signal TSY output from the combination coater 19. , the image signal PIG stored at this address is the image signal MPS
It is read as .

Here, horizontal synchronization signal 1-I S Y 2 > horizontal synchronization signal H3Y1, pixel signal P X L 2 > pixel signal P
When a frequency is selected like XLI, the computer 19 of the R image image A of the image signal gMPs on the video monitor 24
The position of the text video signal TXS outputted from the screen on the first screen B is as shown in FIG.

In Figure 2, (χ1, vI) on text screen B
The position of the imaging screen △ indicated by is the horizontal synchronization signal 1-ISYl,
Vertical synchronization signal VSY1. and pixel signal P X L 1
The text screen B composed of (χ2, y2) is determined by the horizontal synchronization signal i-+S Y 2 , the vertical synchronization signal V S Y 2 , and the pixel signal P X I-2. In this case, χ2〉χ〉χI, 7/2
]:・71>The address of the image memory 18 corresponding to the range indicated by y+ is a meaningless address selection.

At this time, the image signal MPS is set to a low level "L" and the text video signal TXS is output.

FIG. 3 is a block diagram showing the inside of the image memory.

The memory element 25 is constituted by a dual port RAM, and the image signal PG is written in synchronization with the address signal output from the address generator 17.

On the other hand, the image signal PIG written in the memory element 25 is read out in synchronization with the address signal from the address generator 20, but when the same address is selected for writing and reading, a busy signal is sent from the memory element 25. is output to a logic circuit 26 composed of an AND gate, a Nant gate, and a ΔA/G1~, and the logic circuit 26 outputs the pixel signal PXL2 of one dot before via a D-type 7 lip-flop (D-FF) 27. .

The output of the logic circuit 26 is an inverter 2 with a control terminal.
8 and two inverters to output as an image signal MPS. Note that Vc pulls up the output of the inverter 28 via a resistor R.

In the case of selecting the corresponding address of the image memory 18 in the range shown by (χ2〉χyu・χI, 7/2・y>,y,) explained in FIG. Since it has no meaning as a memory, address generator 2
The output of the address decoder 30 into which the address output of 0 has been input is set to low level, the output of the inverter 28 is turned off, and the output of the inverter 29 is set to low level rr L
Spelled out by u.

- Effects of the Invention> As described above in detail with the embodiments, according to the present invention, video signals of different frequencies and asynchronous to each other, such as a TV image such as an image pickup screen and a computer text screen, are transmitted at high frequency. Since it is now possible to uniformly read out images on the same screen and display them on the same video monitor, only one video monitor is required, reducing costs and improving the space factor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, and FIG. FIG. 3 is a block diagram showing details of the image memory shown in FIG. 1, and FIG. 4 is a block diagram showing the configuration of a conventional image display device. 10.19...Computer, 12...Text C
RT, 13... Image processing device, 15.16... Monitor CRT, 17.20-X Y 7 dress generator, 1
8... Image memory, 21... Addition circuit, 23...
Scan converter, 24...Video monitor, 25...
・Memory element, IMG...imaging signal, PSY...image synchronization signal, PIG, MPS...image signal, TSY
...Text synchronization signal, TXS...Text video signal. =11-

Claims (1)

[Claims] a dual port memory into which an image captured by an image pickup device is converted into an image signal by an image processing device and inputted; and a first address generator in which an image capture synchronization signal from the image processing device is converted into an address of the dual port memory and written. a second address generator that converts a text synchronization signal from a computer having a synchronization frequency different from that of the imaging synchronization signal into an address of the dual port memory and reads it out; an adding means that receives a text video signal and an image signal of the dual port memory having the same frequency as the text synchronization signal, adds these signals, and outputs the resultant signal as an output image signal; A scan converter that outputs a synchronization signal to a video monitor.