KR950004132B1 - Digital rgb encoder - Google Patents

Abstract

a pixel field divider for dividing the RGB pixel data into an odd number field and an even number field; a synchronization converter for converting a synchronization signal and blank signal of a progressive scanning method into those of an interlaced scanning method; an address/command decoder for decoding the control data in relation to the RGB encode from CPU of the host; and a digital encoder controlled by the decoding data of the address/command decoder, forming the synchronization and blank signals, and pixel data divided into the odd/even number fields into a composite video signal in the interlaced scanning method, and outputting it.

Description

Digital RGB Encoder

1 is a block diagram of a conventional color signal processing apparatus using an analog RGB encoder,

2 is a block diagram of a color signal processing apparatus to which the digital RGB encoder of the present invention is applied;

3 is a block diagram of a digital RGB encoder of the present invention,

Figure 4 (a) is a block diagram of the pixel feed separating means in the encoder of the present invention, (b) is a view showing the operation concept of the pixel feed separating means according to the present invention.

5 is a block diagram of synchronous conversion means in the encoder of the present invention.

6 is a block diagram of an address / command decoding means in the encoder of the present invention.

* Explanation of symbols for main parts of the drawings

6: pixel feed separation means 7: synchronous conversion means

8: address / command decoding means 9: digital encoder

The present invention relates to an RGB encoder for converting digital, blue, and green (R, G, B) pixel data into a composite analog video signal (NTSC signal). Interlaced NTSC video data of sequential scanning method is synthesized by dividing into (Odd Field) and Even Field, and synthesizing the synchronization signal and blanking signal suitable for each of the divided RGB pixel data. The present invention relates to a digital RGB encoder that converts a signal.

Conventionally, an RGB encoder is applied as a color signal processing apparatus required for a TV display of a computer graphic image or a multimedia system as a device requiring a color signal processing apparatus. Conventionally, only an analog RGB encoder capable of encoding by analog signal processing is available. The circuit configuration is shown in FIG. 1 by referring to FIG. 1, a graphics controller 1 for performing graphic processing of image information, a frame buffer 2 for storing image information in units of frames, and buffer output video pixel data. A D / A converter (3) that converts (PXL) to an analog signal, and a pixel clock (PCLK) and a line lock clock (LLC) (Line Locked Clock) are selected to dot clock (DOTCLK) in the D / A converter (3). ) And an analog encoder for converting the output analog color signal ARGB of the D / A converter 3 into an NTSC signal according to the synchronization signal SYNC supplied from the graphic controller 1. Is configured to (5).

The color signal processing operation by this is as follows.

When the graphics controller 1 supplies the control signal CTL, data DATA, and address ADDR for decoding the video data (pixel data) to the frame buffer 2, the pixel data PXL is supplied from the buffer 2. Is output and supplied to the D / A converter 3.

At this time, in order to convert the analog RGB signal into a composite NTSC signal, the graphic controller 1 converts the control program into a sequential scanning mode to a noninterlaced mode / interlaced mode, which is a graphic processing image. The NTSC signal is displayed in the interlaced scanning mode, but the synchronization signal SYNC output from the graphic controller 1 is changed and supplied at the timing suitable for the interlaced scanning method.

When the data of the frame buffer 2 is outputted, the pixel data PXL is outputted by dividing the odd and even feeds, and the pixel data PXL is divided into pixel clock PCLK and line clock clock. The LLC is converted into an analog RGB signal ARGB by a dot clock DOTCLK made by selecting the multiplexer 4.

The analog RGB signal ARGB is output as an analog NTSC signal by the synchronizing signal SYNC in interlaced scanning mode supplied from the graphic controller 1 in the analog encoder 5.

Therefore, in the conventional RGB encoder, analog signal processing for converting a color signal converted into an analog signal into an NTSC signal is performed. Therefore, the video signal of the final output terminal must be deteriorated, and it is difficult to exclude the influence of external noise. In order to convert the color signal, conversion to the interlaced scanning mode must be preceded by the controller for graphics processing. Therefore, there is a problem that the waveform synchronization display of the computer side and the TV receiver side cannot be performed.

The present invention comprises means for separating RGB pixel data into odd / excellent feeds, a means for converting a synchronization signal and a blanking signal suitable for interlaced scanning, and a means for controlling and encoding them into digital RGB. It is an object of the present invention to provide a digital RGB encoder which can perform a conversion process by a digital color signal process to ensure the improvement of image quality and the exclusion of noise effects and to simultaneously display a graphic image on a computer side and an image display on a TV receiver side. Referring to the configuration of the device and the resulting RGB signal processing operation with reference to the following.

First, referring to FIG. 2, the color signal processing apparatus according to the present invention includes a graphics controller 1 for performing graphics processing of image information, a frame buffer 2 for storing image information in units of frames, and buffer output pixel data. Is converted into an analog signal and provided to the monitor by dividing the synchronous signal of the buffer output pixel data and the graphic controller 1 into odd / excellent feeds into digital NTSC signal through digital signal processing. It consists of a digital RGB encoder 5 'which is converted and provided to the TV (VCR) receiver side.

In the RGB signal processing, the control signal CTL, the data DATA, and the address ADDR are output from the graphic controller 1 to control the frame buffer 2, and the pixel data output from the frame buffer 2 is generated. PXL) (RGB (n)) is converted into an analog RGB signal (ARGB) by the D / A converter 3 and supplied to the monitor so that a graphic processing image is displayed on the monitor screen, while the output of the frame buffer 2 is output. The pixel data PXL (RGB (n)) is supplied to the digital RGB encoder 5 'and divided into odd and even feeds, and the sync signal SYNC supplied from the graphic controller 1 is separated from the odd and good. It is composed of an NTSC signal synthesized with the signal converted according to the shield, and the NTSC signal is supplied to a TV or VCR and displayed simultaneously with the graphic image monitor display by the output of the D / A converter 3.

Such RGB conversion to NTSC signal is performed in the digital RGB encoder 5 'of the present invention. Referring to FIG. 3, the RGB pixel data (RGB (n)) is converted into an odd number and Pixel feed separation means 6 for separating into even-numbered feeds, synchronous conversion means 7 for converting a synchronous signal and a blank signal in a sequential scan method into a synchronous signal and a blank signal in an interlaced scan method, and the hoist side Address / command decoding means (8) for decoding control information related to RGB encoding from the CPU, and the odd / excellent separated pixel data and synchronization signal under control according to the decoding information of the address / command decoding means. The digital encoder 9 is configured to output a blank signal as a composite video signal by interlaced scanning. The RGB encoding operation is as follows.

The pixel feed separating means 6 divides n-bit RGB pixel data RGB (n) output from the frame buffer 2 into the odd and even feeds in the interlaced scanning method. Convert to RGB pixel data (IRGB (n)).

Referring to FIG. 4A, in order to divide the RGB pixel data RGB (n) into odd and even feeds, the frame search unit 6A receives the input vertical synchronization signal / VSYNC. As a reference, the current frame input by the sequential scanning method is searched to determine the order of the first frame and the second frame, and the frame signal FRAME1 is output as information indicating the determined frame order.

On the other hand, in order to divide the odd feed and the even feed, the feed search unit 6B divides the odd feed pixel data in the current frame based on the input horizontal synchronization signal (/ HSYNC) and the blank signal (/ VBLANK). It searches for whether or not to divide even-numbered pixel data, and outputs a feed signal FIELD1 as information indicating the searched searched data.

The feed signal FIELD1 and the frame signal FRAME1 are inputted, and the line control logic 6C corresponds to the odd clock in the first frame on the basis of the pixel clock PCLK and the line lock clock LLC. The line storage unit 6D is read / write-controlled so as to divide the pixel data and divide the pixel data corresponding to even-numbered feed in the second frame.

At this time, the clock speed to be read / written is different between the sequential scanning method and the interlaced scanning method (in the interlaced scanning mode, the pixel frame rate of the pixel frame is higher than the line lock clock frequency supplied from the line lock clock generator 6E). The frequency of the pixel clock (PCLK) is fast) The pixel stream rate is changed from the pixel clock PCLK to the line clock LCLK by applying the FIFO memory to the line storage unit 6D for clock timing adjustment.

That is, the line storage section 6D is an odd-numbered feed / write signal ORD / OWR and even-numbered feed-read / write signal ERD / supplied from the line control logic 6C as a result of decoding the frame / feed signal. The input pixel data RGB (n) is divided by frame frames by EWR and output as pixel data IRGB (n) in interlaced scanning mode.

4 (b) shows the concept of pixel feed separation. The interlaced scan is performed by taking the odd feed from the first frame and the even feed from the second frame with respect to the pixel data RGB (n). It shows how to configure 1 frame of the method.

That is, since the frame frequency = the frequency (odd + excellent) frequency = 60 Hz in the sequential scanning method, and the frame frequency = 30 Hz and the feed frequency = 60 Hz in the interlaced scanning method, the first and second frames are divided into two frames. The order is determined, the odd-numbered and even-numbered feeds are obtained from the two frames according to the order, and then reconstructed into one frame of the vial scanning method.

This configuration of the interlaced frame is a result of the data storage / decoding of the line storage unit 6D by the read / write signal in FIG. 4 as described above. For example, the frame signal FRAME1 is low and is closed. When the signal FIFELD1 is low, the read / write ERD / EWR for the even-feed configuration is executed in the line control logic 6C, and both the frame and the feed signal FRAME1 (FIELD1) are high. In the following, the read / write (ORD / OWR) for the odd-feed configuration is performed by the line control logic 6C.

On the other hand, the lead signal ORD (ERD) of the odd and even peaks is logically summed to the oragate 6F and outputted as a line clock LCLK. Since this line clock LCLK is a sum of two feeds, it is line lock. It becomes equal to the clock (LLC) speed.

The RGB pixel data IRGB (n) and the line clock LCLK in the interlaced scanning mode output in this manner are supplied to the digital encoder 9 as shown in FIG.

On the other hand, in FIG. 3, the synchronous conversion means 7 controls the timing of the vertical and horizontal synchronous signals / VSYNC (/ HSYNC) and the blank signal / BLANK in the sequential scan mode to synchronize and the blank signal in the interlaced scan mode. (/ IVSYNC) (/ IHSYNC) (/ IBLANK) and supplied to the digital encoder 9.

Referring to the circuit configuration shown in FIG. 5, the horizontal synchronization signal (/ HSYNC) and the blank signal (/ BLANK) in the graphic pixel frame (sequential scanning method) are the horizontal synchronization signal and the blank signal (/ IHSYNC) in NTSC. Since two frequencies of (/ IBLANK) are provided, the synchronous divider 7A divides them into two to output the divided horizontal synchronization signal and the blank signal (/ IH) (/ IB).

The vertical blank generator 7B receives a horizontal, vertical, and blank signal (/ HSYNC) (/ VSYNC) (/ BLANK) to generate a vertical blank signal (/ VBLANK), and the vertical blank signal (/ VBLANK) The gate 7C is input together with the divided blank signal / IB.

This is to compensate for the division of the blank signal / BLANK (vertical + horizontal) by two vertical blank components in the blank signal, which is compensated for by the AND gate 7C. And the horizontal blank signal (/ VBLANK) are combined to produce a complete blank signal (/ IBL).

In this way, the signals (/ IH) (/ IBL) converted to the timing suitable for interlaced scanning mode are synchronized with the line lock clock (LLC) in the synchronization logic (7D), thereby determining the line rate of the pixel stream per line in NTSC. The final horizontal and vertical synchronization signals and the blank signal / IHSYNC (/ IVSYNC) (/ IBLANK) synchronized with the clock LLC are converted and output. The sync and blank signals output in this manner are supplied to the digital encoder 9 as in FIG. Therefore, the digital encoder 9 converts and inputs RGB pixel data (IRGB (n)), line clock (LCLK), horizontal synchronous signal (/ IHSYNC), vertical synchronous signal (/ IVSYNC), and blank, which are converted and suitable for interlaced scanning mode. The signal / IBLANK is controlled by the decoder 8 to be configured as an NTSC signal (synthetic video data) and output.

This digital encoder 9 includes a register for processing the composite video data, and receives the selection of the register and data read / write control on the input signals from the address / command decoding means 8.

That is, the address / command decoding means 8 decodes the address ADDR (the line assigned to the I / O address or the memory address) and the command COM supplied from the CPU on the host side, and registers the register selection signal RS ( m)), and outputs a read / write signal / RD (/ WR) for access controlling these registers.

The register selection signal RS (m) depends on the number of registers included in the digital encoder 9, and if eight registers are provided, the register selection signal RS (m) can be controlled through a signal line of m = 3 bits.

FIG. 6 is a circuit configuration of the address / command decoding means 8, and the digital encoder 9 control operation by this is as follows.

First, in order to select a register of the digital encoder 9 from the CPU on the host side, an address ADDR previously agreed is supplied.

Among the addresses ADDR, the upper address HA is input to the address comparison section 8A, the lower address LA is input to the address decoder 8C, and the address comparison section 8A is set to the switch section 8B. When the matched address SA is compared with the upper address HA, the comparison signal EQ is activated.

When the comparison signal EQ is active, the address decoder 8C decodes the lower address LA to determine which register is selected, and as a result, outputs the register selection signal PS (m).

On the other hand, the instruction decoder 8D decodes the instruction COM for accessing the register of the digital enter 9 from the CPU on the host side and outputs a read signal / RD or a write signal / WR, The data is written to the register selected by the selection signal RS (m) or controlled to read the recorded data.

The operation of controlling the digital encoder 9 in the address / command decoding means 8 depends on how the register inside the encoder is controlled on the host side. For example, the I / O mapping method (I / O Mapped), the register control area is set on the host side, and eight registers are provided, and when the setting area is 230 to 237H or 240 to 247H, HA = A [3: 2], 23H or 24H is SA, LA = A [0: 2], and A [0: 2] has a value of 0 to 7H.

When m = 3 and HA = 23H, the comparison signal EQ is activated. In addition, since I / O map type, COM = / IOR, / IOW (input / output read / write signal). Therefore, in this case, when the register is read, the I / O read signal (/ IOR) is activated, the comparison signal (EQ) is activated, and the read signal (/ RD) is activated, and register access is performed. , / WR is active.

As described above, according to the present invention, the signal conversion of the RGB encoder is performed through digital signal processing, so that image information processed in a multimedia system can be easily recorded and reproduced on a VCR, and can be displayed alone or simultaneously on a TV. By eliminating the influence of noise, it is possible to improve the image quality and thus the quality of the device.

Claims (4)

Pixel feed separation means 6 for separating RGB pixel data (RGB (n)) into odd and even feeds, and a synchronization signal and a blank signal of the interlaced scanning method by synchronizing the synchronization signal and the blank signal in the sequential scanning method. Control according to the decoding information of the synchronous conversion means (7) for converting the data into the control unit, the control information relating to RGB encoding from the CPU on the host side, and the decoding information of the address / command decoding means. And a digital encoder (9) configured to output the odd / excellent separated pixel data, a synchronization signal, and a blank signal as a composite video signal in an interlaced scan method. 2. The pixel feed separating means (6) according to claim 1, further comprising: a frame retrieval unit (6A) for determining a frame for dividing the odd and even feeds and a frame retrieval unit (6A). A feed retrieval section 6B for specifying the odd or even number feed, a line control logic 6C for reading / writing the pixel data of the odd or even number feed in the determined frame, and the line control Frame in interlaced scanning mode by combining the line control unit 6D which receives the read / write control by the feed from the logic 6C and stores and outputs the pixel data divided by the feed unit, and the read / write signal by the feed. A digital RGB encoder comprising an oragate 6F that generates a line clock for determining the speed. 2. The vertical blank generator according to claim 1, wherein the synchronous conversion means (7) comprises a synchronous divider (7A) for dividing the horizontal synchronous signal and the blank signal into two, and a vertical blank signal from the horizontal / vertical synchronous signal and the blank signal. 7B, an AND gate 7C combining the two divided blanking signal and the vertical blank signal to compensate for the missing vertical blank signal at the time of dispensing, and the divided horizontal synchronizing signal and the compensated blank signal to linelock clock. Digital RGB encoder characterized by consisting of a synchronization logic (7D) for outputting the NTSC horizontal / vertical and blank signals in synchronization with the. The address / command decoding means 8 determines whether the address provided is information for RGB encoding control by comparing an address supplied from the CPU on the host side with an address set by the switch section 8B. The address comparison section 8A, the address decoder 8C which decodes the provided address into register selection information of the digital encoder 9 in accordance with the comparison / decision result, and the instruction supplied from the CPU on the host side. And a command decoder (8D) for decoding the data read / write control signal of the register.