KR20000020092A - Playback circuit of wide pdp television receiver - Google Patents

Abstract

PURPOSE: A playback circuit of wide PDP without driving a special IC only for playback is provided. CONSTITUTION: In a playback circuit of a wide PDP television receiver, an analog/digital converter(110,120,130) converts analog RGB signals into a first digital RGB data. A line memory(210,220,230) stores the digital RGB data and outputs a second digital RGB data which is delayed for one cycle of the horizontal sync signal. A multiple processor(300) vertically interpolates the first and second digital RGB data. A field memory(410,420,430) stores the first and second vertically interpolated digital RGB data from multiple processor(300). A controller controls analog/digital converter(110,120,130), line memory(210,220,230), multiple processor(300), and field memory(410,420,430) to control an output for the RGB data stored in the field memory(410,420,430).

Description

Wide PD TV Playback Method and Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel TV, and more particularly, to a method for implementing a playback of a wide plasma display panel (TV).

Wide PD TV is a TV that can realize a wide screen in PD TV. In particular, a circuit for reproducing a screen passed through the wide PD TV, that is, a circuit for implementing a playback screen, is shown in FIG. 1.

A conventional system implementing a playback screen converts an R signal, a G signal, and a B signal corresponding to a playback screen into 8-bit digital signals using an AD converter, and stores them in a field memory. That is, the digital R data, digital G data, and digital B data converted by the AD converter are stored in the field memory, respectively.

The first synchronization signal corresponding to the main picture and the second synchronization signal corresponding to the playback picture are applied to the controller, and the controller refers to the first synchronization signal and the second synchronization signal with reference to the controller. Digital RGB data stored in the field memory is implemented as an image on the PD screen. The control unit locks the second synchronization signal to the first synchronization signal and generates various control signals to control the AD converter and the field memory.

However, in the conventional circuit for implementing a playback screen, a dedicated IC for processing the playback screen must be separately installed, thereby increasing the manufacturing cost.

The present invention has been made to solve such a problem, and an object thereof is to provide a circuit and a method for processing a playback screen without using a dedicated IC.

1 is a block diagram showing a reproduction screen realization circuit of a conventional wide plasma display panel.

2 is a block diagram showing a circuit for implementing a playback screen of a wide plasma display panel according to the present invention;

3 is a view showing an area where a playback screen is displayed on a screen of a wide plasma display panel;

Fig. 4 is a diagram showing a memory area of a field memory divided by the present invention.

FIG. 5 is a diagram illustrating image data stored in 16 divided unit cells implemented on a screen of a plasma display panel; FIG.

6 shows waveforms of various signals used in the reproducing circuit of the present invention.

Explanation of symbols for main parts of the drawings

110: first converter 120: second converter

130: third converter 210: first line memory

220: second line memory 230: third line memory

300: double speed processing unit 410: first field memory

420: second field memory 430: third field memory

500 control unit 600 clock oscillator

700: Display screen of main image data 800: Display area of playback screen

The present invention is characterized by outputting the vertical interpolation of the video signal of the two lines using a double speed processor.

As shown in FIG. 2, the present invention provides an analog / digital converter (110, 120, 130) for receiving an analog RGB signal and converting it into first digital RGB data, and a second digital RGB delayed by one period of the horizontal synchronization signal. A line memory for outputting data, a double speed processor 300 for vertically interpolating the first digital RGB data and the second digital RGB data according to a double horizontal synchronization signal, and the RGB data output from the double speed processor 300 Field memories 410, 420, and 430, and converters 110, 120, and 130, line memories 210, 220, and 230, double speed processor 300, and field memories 410, 420, and 430. And a control unit 500 for controlling the output of the RGB data stored in the field memories 410, 420, and 430.

The analog / digital converters 110, 120, and 130 receive analog RGB signals and convert them into first digital RGB data. The analog / digital converter 110, 120, 130 includes a first converter 110 for converting an analog R signal into 8-bit digital R data, and a second converter for converting an analog G signal into 8-bit digital G data. Converter 120 and a third converter 130 for converting the analog B signal into 8-bit digital B data.

The line memories 210, 220, and 230 store digital RGB data corresponding to one period of the horizontal synchronization signal, and output second digital RGB data stored in accordance with a control signal of the controller 500 to distribute the digital RGB data. To apply. The line memories 210, 220, and 230 each include a first line memory 210 storing digital R data output from the first converter 110 and a digital G data output from the second converter 120. 2 line memory 220 and a third line memory 230 for storing the digital B data output from the third converter (130).

The double speed processing unit 300 vertically interpolates the first digital RGB data and the second digital RGB data according to the horizontal synchronous signal of twice. The first digital RGB data and the second digital RGB data are image data having a parallax for one period of the horizontal synchronization signal.

The field memories 410, 420, and 430 store RGB data of one field output by being vertically interpolated by the double speed processing unit 300 and output the RGB data according to a control signal of the controller 500. One field amount of RGB data output from the field memories 410, 420, and 430 is displayed on the PDIP screen together with the main picture.

The controller 500 controls the analog converter, the line memories 210, 220, 230, the field memories 410, 420, 430, and the double speed processor 300, and controls the field memories 410, 420, 430. Controls the output of stored RGB data.

The operation principle of the present invention is as follows.

An analog RGB signal corresponding to a playback image is input to the converter. The analog RGB signals input to the converters 110, 120, and 130 are output as 24-bit digital RGB data by the sampling frequency signal controlled by the controller 500. At this time, the clock required for the operation of the control unit 500 is supplied from a separate clock oscillator 600.

That is, the analog R signal is input to the first converter 110 to output 8-bit digital R data, and the analog G signal is input to the second converter 120 to output 8-bit digital G data. The analog B signal is input to the third converter 130 to output 8-bit digital B data.

The 8-bit digital RGB data output from the first, second, and third converters 110, 120, and 130 is input to the line memories 210, 220, and 230 according to an input control signal of the controller 500. The digital RGB data output from the converters 110, 120, and 130 are simultaneously input to the double speed processing unit 300. As a result, the RGB data input to the line memories 210, 220, and 230 are delayed by one horizontal synchronization period and input to the double speed processing unit 300. That is, the digital RGB data of the nth line output from the converters 110, 120, and 130 and the digital RGB data of the n−1th line output from the line memories 210, 220, and 230 are simultaneously supplied to the double speed processor 300. It is input.

The plasma display panel has at least 480 vertical lines. Therefore, the horizontal frequency should be 31.5 kHz. The analog RGB signal of 15.75 kHz at the time of input is vertically interpolated by combining the digital RGB data of the n-1th line and the digital RGB data of the nth line in order to be converted to 31.5 kHz. As a result, the RGB data output from the double speed processing unit 300 is input to the field memories 410, 420, and 430 according to the first control signal of the controller 500 with the horizontal synchronization signal of 31.5 kHz.

At this time, the first control signal of the controller 500 is a write reset signal for moving a write address pointer to address 0 in units of fields, and an 8-bit digital signal input to the memory according to a clock frequency. A write enable signal for storing, a write address signal for increasing the address of the write address position according to the clock frequency, and the like.

In addition, image data stored in the field memories 410, 420, and 430 are output according to the second control signal controlled by the controller 500.

At this time, the second control signal of the controller 500 reads a read reset signal for moving a read address pointer to address 0 in units of fields, and reads a stored 8-bit digital signal from the memory according to a clock frequency. It consists of a read enable signal and a read address signal that increases the address of the read address location with the clock frequency.

The digital RGB data output from the field memories 410, 420, and 430 by the second control signal is later switched to the image signal of the main screen and displayed on the PD. At this time, the implementation method of the playback screen according to the present invention is performed through the following steps.

First, the present invention divides the memory area of the field memories 410, 420, and 430 into m unit cells, and stores image data of one field in rotation in each unit cell. That is, according to the present invention, the image data of the first field is stored in the first unit cell, the image data of the m-th field is sequentially stored in the m-th unit cell, and the image data of the m + 1-th field is stored again in the first unit cell. Each unit cell sequentially stores the image data.

When output of the playback screen is requested by the user or by another external control signal, the present invention outputs the image data of the next unit cell of the unit cell in which the current image data is stored, starting from the image data. At this time, the output period of the image data is the same as the period of storing the image data in the unit cell.

Hereinafter, a preferred embodiment of the regeneration method of the present invention will be described with reference to FIGS. 3, 4, and 5.

(Example)

5 shows a display area of a wide PD. The entire screen area of the wide PD is basically composed of 852 columns and 480 lines, and the effective image area 700 in which a valid image is implemented is composed of 832 columns and 468 lines. The reproduced image implemented by the present invention displays an area of a size of one sixteenth in the effective image region 700 in the display region 800 of the reproduced image.

4 shows the field memories 410, 420, 430 which are divided and used according to the present invention. The field memories 410, 420, and 430 shown in FIG. 4 are divided into 16 unit areas, but may be divided into more than that.

The image data of the first field is stored in the first unit cell of the field memories 410, 420, and 430. The image data after 10 fields is stored in the second unit cell. Fields of the image data stored in the first unit cell and the image data stored in the second unit cell may be specified differently according to the control signal of the controller 500. That is, the controller 500 may control the image data stored in the first unit cell to 10 fields or 16 fields after the field data to be stored in the second unit cell. In this way, one field of image data is periodically stored in each unit cell.

Then, when the reproduction circuit according to the present invention stores the image data in the fifth unit cell, if a signal for requesting the output of the reproduction screen is generated by a user's operation or a control signal of an external device, the present invention provides the present invention. The image data stored in the 16th unit cell is sequentially output from the next unit cell of the unit cell in which the image data is stored, that is, the image data stored in the 6th unit cell. After outputting the image data stored in the 16th unit cell, the image data stored in the first unit cell is sequentially output from the image data stored in the fifth unit cell, thereby completing the output of the playback screen. At this time, the output period of the image data stored in each unit cell is twice the storage period of the image data of each unit cell. That is, if image data is stored in each unit cell for every 10 fields, the image data stored in each unit cell is output whenever the main picture data of 20 fields is displayed.

Figure 3 shows a screen of a wide PD on which a playback screen implemented according to the present invention is displayed. In the reproduction screen of the present invention, 117 lines are displayed after 296 lines, and 208 columns are displayed after 608 columns.

Figure 6 shows a timing diagram of each signal used in the present invention. The double speed processed horizontal sync signal has a period twice as long as the original horizontal sync signal, and the period of the vertical sync signal is the same before and after the double speed process. At this time, the image data corresponding to one of four lines among the image signals of one field is stored in the line memories 210, 220, and 230 by the writable signal of the horizontal synchronization signal. Then, one pixel signal among four pixel signals output after the double speed processing by the write-enabled signal of the pixel is stored in the field memories 410, 420, and 430.

As a result, of the 832 pixel signals after the double speed processing, the 208 pixel signals form a line of reproduction screen by the write-enabled signal of the pixel. Then, among the screens in which there were 468 horizontal synchronization signals during one period of the vertical synchronization signal, 117 horizontal synchronization signals form a reproduction screen of one field. In other words, the image data of the reproduction screen during one period of the vertical synchronization signal is implemented in the amount of 117 lines x 208 pixels.

According to the present invention, since the playback screen is constructed by double-speed processing of the field memory, the horizontal synchronization signal, and the writable signal of the pixel, there is an advantage that an IC dedicated to the playback screen is not required as compared to the conventional wide PD. As a result, the present invention has the effect of lowering the manufacturing cost compared to the conventional wide screen reproduction screen realization circuit.

Claims (5)

An analog / digital converter configured to receive an analog RGB signal and convert the analog RGB signal into first digital RGB data; A line memory for storing the digital RGB data corresponding to one period of the horizontal synchronization signal and outputting second digital RGB data delayed by one period of the horizontal synchronization signal; A double speed processor configured to vertically interpolate the first digital RGB data and the second digital RGB data according to a double horizontal synchronization signal; A field memory for storing RGB data output from the double speed processing unit; And, And a control unit controlling the conversion unit, the memory, the double speed processing unit, and the field memory, and controlling the output of the RGB data stored in the field memory. The method of claim 1, wherein the analog / digital conversion unit A first converter for converting the analog R signal into 8-bit digital R data; A second converter for converting the analog G signal into 8-bit digital G data; And, And a third converter for converting the analog B signal into 8-bit digital B data. Dividing a predetermined memory area into m unit cells; Rotationally storing predetermined image data in the unit cell at predetermined intervals; And, And outputting the image data of the next unit cell of the unit cell in which the current image data is stored, when the output of the playback screen is generated from the outside. 4. The method of claim 3, wherein the image data stored in the unit cell is image data corresponding to one field. 4. The method of claim 3, wherein the dividing of the unit cell comprises dividing into 16 unit cells.