SU1647628A1 - Device for data display on a tv indicator screen - Google Patents

Abstract

The invention relates to automation and computing and can be used in systems for displaying graphical information, multi-color and three-dimensional images. The purpose of the invention is to expand the field of application of the device due to the possibility of simultaneous display of several color images with the simultaneous formation of a background - achieved by the introduction of a switch, a register, a block of permanent memory and a buffer register and corresponding functional links. The invention allows the reproduction of color images, the simultaneous display of several of the images, the hardware recording of information in the memory during the formation of the background of the image. In addition, the ability to prioritize between the pages of the memory allows to obtain not only the undistorted image, but also the preservation of color gradations of the image, which is especially important in the analysis, in which various parameters (temperature, amplitude, pressure, etc.) of the object are encoded by gradation colors. 1 il. (L

Description

The invention relates to automation and computing and can be used in systems for displaying graphical information, multi-color and three-dimensional images.

The purpose of the invention is to expand the field of application of the device by allowing the simultaneous display of several color images and the simultaneous formation of a background.

The drawing shows a block diagram of the device.

The device comprises an interface unit 1, a control and synchronization unit 2, an address generator 3, a main memory unit 4, a television indicator 5, a video signal generator 6, a switch 7, a register 8, a permanent memory unit 9 and a buffer register 10.

For interface of the device with a computer cable (not shown), is used the interface 1, through which during the program exchange, information is exchanged between the computer channel and such elements of the device,

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as a memory block 4 and a register 8. The interface outputs are used to control the operation of the control block 2 CS

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laziness and synchronization and control register 8.

The control and synchronization unit 2 contains in its basis a pulse generator that generates the necessary pulse frequency to ensure the normal operation of the device, a counter (frequency divider) and logic elements to form synchronizing pulses of the required duration and frequency and control signals (not shown).

Shaper 3 of the address includes a counter that changes its state synchronously with the scanning of the electron beam (television indicator): the lower bits synchronously with the scan of the line, the higher bits by the frame, and the address register is not shown,

From the output of the control and synchronization unit 2, the horizontal and vertical sync and dying pulses go to the television indicator, the vertical sync pulses to the register 8, and the 10-clock frequency to the buffer register 10.

The content of the address generator 3 (counter) determines the current address in the frame that is used when scanning the memory in the television standard when outputting the completed information for display.

Block 4 of the RAM is made in the form of an N-page memory. Access to each of the pages from the side of the computer channel in the program exchange mode is arbitrary. At the same time, from 1 to N pages can be accessed. Reading information in parallel in time. Each page of memory in general has K bits, determined by the number of color gradations.

The addressing of the pages of block 4 of the operational memory in the process of program exchange is provided by means of the driver 3 addresses (address register), the contents of which are connected to the address inputs of block 4 of the operational memory (4).

The selection of the pages of the operative memory block 4 is performed by setting the corresponding bits in the control register 8. In one access to the pages of block 4, the RAM reads or writes 0

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with several words at the same time (raster element codes). This makes it possible to alternate in time the read cycles of the data in the display and the cycles of access to the memory from the channel of the computer. Thus, it is possible to record new information directly in the display process, which is essential when displaying dynamic processes.

In the cycle of access to the memory from the computer channel, the contents of the address register of the address maker 3 addresses are connected to the address inputs of the memory block 4, and in the data read cycle for display, the contents of the count of the imager 3 addresses are connected.

Register 8 is software accessible, so programmatically it is possible to change the operating mode of the device. Register 8 is implemented on the basis of D-flip-flops. Bit size depends on the number of pages of memory and functions performed. The higher bits of the address of block 9 are connected to register 8, which allows, by changing the mode of operation of the device, to display the necessary information. In the process of forming a picture frame, information from the RAM block 4 N-bit word arrives at the lower address inputs of block 9, providing a sample of the word encoding the corresponding color gradation.

When writing to the register 8 of the corresponding control code, the following operating modes are realized: selective display of images, setting the priority for displaying the contents of memory pages, displaying multi-color and black-and-white (half-tone) images.

The data from the output of the fixed memory unit 9 is fed to the information inputs of the buffer register 10. The recording is performed by pulses from the output of the control and synchronization unit 2. The buffer register 10 serves to eliminate the interference that occurs at the outputs of block 9 when switching the address inputs. Information from the output of the buffer register 10 is supplied to the information inputs of the video signal generator 6. The latter is a set of buffer cascades, and in the general case, for receiving tonal images, the shaper 6 of video signals contains digital-to-analog converters,

the outputs of which form the components R, G, B.

The device works as follows.

The device can be divided into three main modes of operation.

In the first mode, information is recorded from the computer to the RAM unit 4. The hardware enable bit is set to zero, therefore, to the information input of the RAM unit 4, the output of the interface unit 1 is connected via switch 7. The address of the cell into which the information is to be entered is set in the address register (not shown) of the driver 3 addresses. Recording mode is set at the control input of the main memory unit 4, the address input is connected to the address register of the address maker 3, after which the output of the interface unit 1 contains data that is written to the unit 4 via the switch 7 at the specified address.

In the second mode, the device operates autonomously if the hardware enable bit is not set. The address input of block 4 is connected to the output of a counter (not shown) of address builder 3, the contents of which sequentially change from zero to a number that determines the number of hell "- recs in a frame. At the end of the frame, the counter is set to zero. At the control input of block 4, the read mode is set, data from block 4 is sent to the address inputs of block 9. Depending on the display mode set, data from the output of block 9 is sent to the buffer register tO, from which the same data is output, but without interference 6 video signals are input to the imager. Thus, all the information stored in the memory is reproduced on the screen of the television indicator. Modes 1 and 2 can be combined in time, i.e. Information can be recorded directly in the display process.

In the third mode, when the hardware enable bit is set, switch 7 is switched, which connects the corresponding bits of register 8 to the information inputs of the main memory block 4 and, depending on

Most of the code installed in them is clouding or writing the background to the memory pages (into one or several). The recording starts and ends on frame sync pulses. The address inputs of the block 4 of the RAM memory are connected to the counter of the driver 3 addresses. The recording starts at the zero address and ends at the maximum. The execution time of this operation is equal to the frame display time.

The proposed device will also allow priority display of memory pages. When entering graphs, figures or histograms into memory pages and their subsequent display, mutual

0 is superimposed on each other, which leads to incorrect color reproduction (which is unacceptable in the analysis, in which temperature, amplitude, pressure, etc. are encoded with a gradation of color). The priority display of memory pages allows obtaining not only an undistorted image, but also the preservation of color gradations of the image.

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Claims (1)

Invention Formula A device for displaying information on the screen of a television indicator comprising an interface unit, a control and synchronization unit, an address generator, an operational memory unit, a video signal generator, the first input / output of the interface block Q is the device input-output, the second input-output of the unit the interface is connected to the input-output of the control and synchronization unit, the second input-output of which is connected to the input-output of the address generator, the output of which is connected to the address inputs of the operating memory unit that controls the inputs of which are mated to the corresponding outputs of group 0 of the control and synchronization unit, the output of which is connected to the control input of the television indicator, whose information input is connected to the output of the de-signaling device, the outputs of the first group of the operational memory unit are connected to the information inputs of the interface unit, different so that, in order to expand the region When the device is used by enabling simultaneous display of color images and simultaneous formation of a background, it contains a switch, a register, a fixed memory block and a buffer register, the input register of the control register is connected to the third input / output of the interface block whose output is connected to the first information input of the switch, the second information input of which is connected to the first output of the register, the second output of which is connected to the control input of the switch, the output which is connected to the information inputs of the main memory unit, the outputs of the second group of which are connected to the address inputs of the first group of the permanent memory unit, the address inputs of the second group of which are connected to the third output of the register, the synchronous input of which is connected to the output of the control and synchronization unit and the synchronous input the buffer register, the information input of which is connected to the output of the permanent memory unit, and the output - to the input of the video signal conditioner. External computer channel one