SU1529279A1 - Device for presentation of information - Google Patents

Abstract

The invention relates to automation and computing and can be used to display graphical information from a computer. The purpose of the invention is to increase the speed of the device. The device contains a block 1 of the interface, the first 2 and second 3 counters, the first 4 and second 14 blocks of RAM, video signal formers 5 and control pulses 7, the first 6 and second 10 registers, the first 8 and second 15 multiplexers, lower 9 blocks and frame 11 synchronization, the first 12 and second 13 shift registers with corresponding links. Information about the color image and service information through the block 1 of the conjugation is entered into the block 4 of the memory. Read addresses are generated by counters 2 and 3 and through multiplex 8 are sent to the address input of memory block 4. The information read from block 4 of the information is converted into successive codes in shift registers 12 and 13. From the output of register 12 through multiplexer 15, color codes arrive at the address inputs of memory block 14, where they can be recoded, and arrive at the first input of the imager 5 of the video signal, to the second input of which an overhead signal is applied. The control of the information display sequence is determined by the contents of the state register 10, thereby increasing the speed of the device. 2 Il.

Description

315

The invention relates to automation and computing and can be used to output color images of graphical information of the forming computer.

The purpose of the invention is to increase the speed of the device.

FIG. 1 is a functional block diagram of the device; in FIG. 2 - timing charts of the device.

The device contains a block 1 of the interface, the first 2 and second 3 counters, the first block 4 of RAM, the shaper 5 of the video signal, the first register 6, the shaper 7 of control pulses, the first multiplexer 8, the block 9 horizontal synchronization, the second register 10, block 11 frame synchronization, the first shift register 12, the second shift register 13, the second operative memory unit 1.4, the second multiplexer 15. Figure 1 also indicates the information input-output 16 of the device, the internal highway 17, the output 18 of the video signal, the outputs 19 of the personnel and 20 build of the device clock synch ..

The device works as follows.

Information is received from an external computer (not shown) through the interface 1, which, during a program exchange, exchanges information between the computer channel, the blocks, the RAM 4 and 14, the driver 7, the address registers 6 and 10 condition A portion of the lines of the internal highway 17 is used to control the operation of the RAM unit 4 by means of the former 7.

 The shaper 7 control pulses generate clock pulses at the input of the first counter 2, control the operation of the first 12 and second 13 shift registers, control the operation of the first multiplexer 8 of the address.

I

Pervy 12 and second 13 counters

they change their state synchronously with the scanning of the electronic beam of the TV monitor: the first counter synchronously with the scanning on the line, the second - on the frame. The counters work in conjunction with the lowercase 9 and frame 11 synchronization blocks, which ensure the formation of synchro (FID)

5 0 5

ABOUT

5 Q

five

0

five

(GIS, OIG) pulses. The sync pulses go to the external bus lines 20 and frame 19 synchronization and are used to synchronize the operation of the TV monitor, and damping pulses to the inputs of the imaging unit 5 of forming video signals.

The outputs of the first 2 and second 3 counters are connected to the first multiplexer 8 of the address and determine the current address in the frame that is used when scanning memory block 4 in the television standard when outputting information from it for display,

The memory unit 4 can be made in the form of a double-page memory. The access to each of the pages from the computer in the program exchange mode is carried out separately, and the information for display is read parallelly in time. The first page is for placing image information. Each cell of its memory has grooves defined by the number of used

2 color gradations. The second page is intended for placement of the information accompanying the main image: marker, zones of interest, graphic or character data - and has single-bit memory cells.

Since in the process of displaying scanning of the same frames of two pages of the RAM block 4 is carried out in parallel in time, in the imaging unit 5, the frame of the second page is superimposed on the image frame.

The addressing of the pages of the operative memory block 4 during the program exchange is provided by means of the address register 6, the contents of which are connected via the address multiplexer 8 to the address inputs of the memory block 4. Register 6 addresses software available from the computer. The selection of the first or second page of the memory block 4 is performed using a special bit of the state register 10. A sign of the page, which is connected to the input of the memory block 4.

In one access to the pages of memory block 4, several words (codes of raster elements) are read or written at the same time. This makes it possible to alternate in time the cycles of access to the memory from the computer and the cycles of reading, data during display, which

they are entered into the shift registers 12 and 13, and then shifted from them with the frequency of displaying the elements of the raster.

In this way, the ability to record new information directly in the process of displaying is provided, which is essential when displaying dynamic processes and organizing a moving marker.

In the cycle of accessing the memory from the computer side, the contents of the address register 6 are connected to the address inputs of the memory block 4 through the address multiplexer 8, and in the data reading cycle for display, the contents of counters 2 and 3 and part of the status register 10 bits. In this case, the contents of counters 2 and 3 sets the current address in a register bit of 10 sos frame,

This is neither - the number of the displayed frame

The state register 10 is programmatically accessible, so the possibility of changing the number of the displayed frame allows realizing the user-time display of several frames, the information in which has been previously recorded.

In the process of forming a frame, the images are sequentially extended from the shift register 12 through the second multiplexer addresses 15 are sent to the address inputs of the second memory block 14, providing a selection of the word encoding corresponding color gradation. The color grading code consists of three parts, each of which encodes the intensity of the corresponding color: red R, green G, blue B.

From the output of the second memory block 14, the color gradation codes and the codes from the output of the second shift register 13 are used to -form the video signal in the shaper 5, where they are converted into analog signals and replaced with blanking signals in the SGI line and the OIG frame. In addition, a control signal is supplied to the input of the imaging unit 5 from the corresponding register bit 10 of the state Resolution of the guide, which allows the contents of the frame of the second page of the memory block 4 to be superimposed on the main image.

Access to the second memory block 14 from the computer side to change the color-coding table is allowed

ten

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only during the return path of the beam over the frame (at the time of the formation of the OIG). Therefore, the contents of the address register 6, with which the address ahx and the second memory block 14 are determined, are connected to its address inputs using the second address multiplexer 15 only for the time of the OIG, in addition, the OIG signal is output as one of the register bits 10 state (reverse flag). This bit determines the time from which the second block can be accessed.

15 14 memory for entry (change). color coded tables.

If the first page of memory block 4 contains information about the intensity of distribution over the surface

20 frames of a signal, and in

cells of memory block 14, addresses of which correspond to intensity codes, codes of corresponding color gradations are entered directly into

25, the process of outputting data on a CRT is color-coded. Full or partial modification of the color coding of the image is carried out by simply changing the colorization table in the second memory block 14, which has little information 30

five

0

five

volume determined by the number of color gradations 2.

Shaper 5 implements the overlay of accompanying information on the main image. For this, the second information input of the imager receives information from the second page (one-bit) of memory block 4. through a second shift register that is scanned in parallel with the first. If in the status register 10 the Permission Accompanying permission is set, then the appearance of the signal from the second page of the memory block 4 leads to the formation of R, G, B signals of maximum intensity and, consequently, the appearance of a white dot on the color TV monitor screen.

0

FIG. 2 shows the timing diagram of the device.

The control signal MA.1 (Fig. 2a) at the time of the memory access cycles from the computer side provides connection to the address inputs of the memory block 4 of the register 6, and at the data reading time for displaying the contents of its counters 2 and 3 and portions of the status register bits 10 determining the number of the frame being displayed,

At the end of each reading cycle, the data for displaying information is fixed in the shift registers 12 and 13 (Cp CP, Fig. 2c), and then shifted (Fig. 2d). During the shifts, the first block 4 of memory is allowed to be accessed by the computer if the read / write signal of the TU (Ch / Zp TU1) is received by the driver 7.

The control pulse generator 7 coordinates the timing of operation of memory block 4 with signals BP / Zp BP1 from the interface block 1 and provides the formation of read signals to the buffer register Zp BR from RAM BP1 (Fig. 26) or writing to RAM BP1 (Fig. 2e), as well as the signal of the Response (Fig. 2e), indicating the end of the memory access operation.

The time diagram (Fig. 2d, e) shows only the resolved moments of the formation of the signals of the Sn RAM and the Answer. Their production is carried out when a 4t / 3p BP1 signal arrives. When forming the signal Zp of RAM, the signal Zp BR in this cycle does not produce, c.

Thus, the invention provides improved device performance when presenting a sequence of image frames with service dynamic information by independently controlling the display of information fields from the first memory block.

Claims (1)

Invention Formula A device for displaying information containing the first and second blocks of RAM, from the first to the fourth registers, the first and second shift registers, the first and second multiplexers, the driver of control pulses, blocks of frame and line c1-scrontization, the first and second counters , video signal generator, interface block, the first information input / output of which is connected to the information inputs / outputs of the first RAM block, the first and second registers, the first and second outputs of the first block of operas The active memory is connected to the information inputs of the first and second shift registers, respectively, the outputs of the first shift register and the first register are connected to the nepBbiM and the second information inputs of the second multiplexer, the output of which is connected to the address input of the second RAM block, respectively. information input of the video signal maker, whose frame and line sync inputs of which are connected to the first outputs of the frame and line blocks, respectively synchronization clock inputs of which are connected to the first outputs of the second and first counters, respectively, the second outputs of which are connected to the first information input of the first multiplexer, the output of which is connected to the address input of the first RAM block, the first output of the driver of the control pulse is connected to the clock input the second counter, the clock input of the first counter and the gate input of the frame synchronization block are connected to the second output of the horizontal synchronization block; the output of the driver ideosignala output device is a video signal, an information input-output of which is a second ny an information input-output interface unit. That is, in order to increase the speed of the device, the control inputs of the first and second shift registers are connected to the second output of the control pulse generator, the third output of which is connected to the control input of the first multiplexer whose second information input is connected to the first the output of the second register, the second output of which is connected to the control input of the video signal generator, the second information input of which is connected to the output of the second shift register, the third output of the second the register is connected to the control input of the first memory block, the control inputs of the second register and isToporo multiplexer are connected to the first 1 output of the frame synchronization unit. The second output of which and the second output of the horizontal synchronization unit are outputs of the frame and line sync pulses respectively devices, information G- inputs-outputs of the imager 1529279 the control pulses and the second block of the interface block, the third information-operative memory is connected to the c first input of the first multiplexer information input-output connected to the output of the first register, tpag.2