SU1661825A1 - Device for graphics display on tv monitor screens - Google Patents

Abstract

The invention relates to automation, computing and can be used in the design of display devices on the screens of television indicators. The purpose of the invention is to increase the speed of the device is achieved by introducing into the second driver of the control signals of blocks 15 and 16 of RAM, three counters 17-19, switch 20 address, comparator 21, switch 22, AND 23-27 elements, inverter 28, OR element 29 and corresponding functional relationships. The coordinates of the contours used in the instrumental filling of the fields (cuts) of the volumetric figure are recorded in the memory of the second former. The device allows reproducing stroke, fill flat and three-dimensional figures with high speed, sufficient to reflect the dynamics of fast processes. 1 hp f-ly, 2 ill.

Description

The invention relates to automation and computing technology and can be used in designing information display devices on television indicator screens.

The purpose of the invention is to increase the speed of the device.

Fig, 1 shows a functional diagram of the device; in fig. 2 is a functional diagram of the second driver control signals.

The device contains 1 image generator, 2 clock pulse generator, address counter 3, first address switch 4, clock generator 5, first 6 and second 7 memory blocks, first control signal generator 8, video signal generator 9, group 10 registers, data switch 11, television indicator 12, second control signal generator 13, control signal switch 14, control signal generator 13 (Fig. 2) contain the third and fourth memory blocks 15 and 16, the first, second third counters 17 - 19, the second address switch 20, a comparator 21, a switch 22, a first 23, second 24, third 25, fourth 26 and fifth AND gates 27, an inverter 28, an OR gate 29.

The control input counter 17 and the first input of the OR element 29 are the control inputs of the group, the control inputs of the switch 22 and the switch 20 of the address control input, the information inputs of the counter 18, the third and fourth memory blocks 15 and 16 and the information inputs the first group of the address switch 20 — the information inputs of the first group, the inputs of the AND 23 element, the control input of the counter 18, the second inputs of the AND elements 24 and 25 — the information inputs of the second group, the information input of the switch 22 — the clock input, the output of the counter 17 — n The first output, the output element And 27 - the second output, the outputs of the counter 19 and the address switch 20 - the outputs of the imaging group 13.

The device works as follows.

When creating a display file, the image highlights the fields to be filled with one color or semitone, and the display priority of each field is determined. The field observed over other image elements is given top priority. The number of fields filled with one color (half tone) is determined by the size P of the memory block 7 and the image structure.

The total number of colors and halftones of the reproduced image, including

the background of the screen is determined by the size of the memory block 6. If it contains I bits, then n 21.

The device operates in three modes: write, read, and fill in the memory. A display of an arbitrary image file formed by a computer and fed through the input-output of the device to the image generator 1 includes blocks for writing dashed figures filled in with flat and

5 volumetric figures. In block 7, the contours (borders) of the fields to be filled in are recorded, and in block 6, the codes of the colors and semitones of the bar and fill elements of the images are recorded.

In write mode, the switch 4 addresses

0 connects the address inputs of blocks 6 and 7 to the counters of the image generator 1, and a switch 14 of control signals connects the control input of block 6 to the corresponding output of generator 1

5 images. In this case, the driver of the control signals 8 excludes the recording of extreme points in the block 7 in the contours of the fields to be filled in, the reading of which may lead to malfunction of the driver 9

0 video signal.

When reading, address switch 4 connects the address inputs of blocks 6 and 7 to address counter 3, and data switch 11 connects informational inputs (for example, PCB inputs) of television indicator 12 with outputs of one of group 10 registers according to priority. At the moments when the counter selects the 3 cell address of the block 7, in which is located

0 on any line point of the contour of the field to be flooded, the video signal shaper 9 supplies the write strobe to the corresponding register 10 of the group and simultaneously the data switch 11 connects its outputs

The 5 information inputs of the indicator 12. After gating, the fill color code is stored in this register. At the moment when the counter selects the cell address of block 7, in which the second point of this contour is recorded, is located on the same line,

shaper 9 video switchboard, rum 11 disables the outputs of this register from

information inputs indicator 12.

In the fill memory mode, first in

5, the control signal generator 13 is recorded with the coordinates of the points of the contour of the field to be filled, and then 1 the actual filling of this field with color (half-angle), the code of which comes from the image generator 1, is carried out. With this switch

4 connects the address inputs of the block 6 to the outputs of the generator group 13, and the switch 14 of control signals connects the control input of the block 6 to the output of the generator 13.

When forming the image of a volumetric figure, the filling in the memory of fields (slices) of the figure is carried out sequentially. In this case, the floor, partially covered by other fields, is poured into the memory first, and the field, which is completely visible, is poured last.

The imaging unit 13 operates in two modes: write and fill to memory (read). In the recording mode, the abscissas of the contour of the field to be filled are recorded in the memory blocks 15 and 16. The recording order is determined by the structure of the former 13. which provides for the recording of the contour bypassing the field counterclockwise when recording. At that, the address switch 20 connects the address inputs of the memory blocks 15 and 16 to the outputs Y of the counter of the image generator 1, and the switch 22 connects the first inputs of the second and third elements 24 and 25 to the outputs of the generator 2 clock pulses.

When writing positive vectors (counting sign + Y), when traversing the right ascending branch of the contour, write pulses from the output of the second element 24 go to the control input of the third memory block 15, where all abscissas of the right contour branch are recorded. Similarly, all abscissas of the left descending branch of the contour (the sign of the count -Y) are recorded in the fourth memory block 16. At the moment when the maximum transitions, the counting counter sign Y of the image generator 1 changes from plus to minus. At this moment, the second counter 18 is fixed to the ordinate corresponding to the upper point of the contour,

In the first counter 27, the number of rows Y of the raster is fixed, completely covering the image of the contour of the poured floor. This is done by AND 23 and counter 17, which is set to zero before the start of the recording.

In the memory fill mode, the address switch 20 connects the address inputs of the memory blocks 15 and 16 to the outputs of the second counter 18, and the switch 22 connects the first inputs of the And 26 and 27 elements to the generator output 2 clock pulses. The fill starts from the line on which the top point of the contour of the filled field is located, the ordinate of which is recorded in counter 18. Before writing to the counter 19 of the memory block 16, the strobe from the image generator 1 is received by the abscissa of the contour point located on this line left. A comparison of the abscissa of this point with the abscissa of the contour point located on this line to the right is carried out by the comparator 21. If the comparison result is zero, the control signal at the output of the And 27 element appears at the recording control input of memory block 6 ti and to the counting input of the counter 19, increasing its output signal by one. Filling in this line is carried out until the output signal of the counter 19 becomes equal to the abscissa of the right point of the contour.

At the moment of equality at the output of the element AND 26, a signal is received through the element OR 29 at the gate input of the counter 19 and at the subtraction inputs of the counters 17 and 18. As a result, the next line address is set at the inputs of blocks 15 and 16 and the pouring process is repeated. Fill ends after resetting counter 17.

The schematic solution of the proposed image generator 1, the imager 9 of the video signal and the imager 8 of the control signals is similarly known. The resolution of the address inputs of the memory blocks 6 and 7 and the address switch 4 is determined by the resolution of the reproduced image. When using standard video control devices as an indicator (format 625 lines x 625 elements), it is advisable to limit it to 18 bits. In this case, the reproduced image will contain 512 lines x 512 elements per line.

The increase in speed in the proposed device is achieved due to the fact that the microspace is not formed, but the search is performed over the raster points bounded by the contour of the field to be filled in, the abscissas of which are recorded in memory blocks 15 and 16. The gain in speed with the simplest, point-to-point memory fill is determined by the ratio of the area of the microraster formed in the known device to the area of the contour of the field to be filled. If the fill is not made pointwise, but accelerated, for example, 4.8, etc. points, the gain in speed will increase by about the same time.

Claims (2)

1. A device for displaying graphical information on a television indicator screen, comprising an image generator, a clock generator, an address counter, an address switch, a sync driver, first and second main memory units, the first and the second control signal drivers, the video signal conditioner, the register group, the control signal switch and the data switch, the input / output of the image generator is the device input-output, the outputs of the first and second groups of the image generator are connected respectively to the information inputs of the first group of the second operational block memory and information inputs of the first group of the first address switch; the first output of the image generator is connected to the input of the first driver of control signals, output The clock generator is connected to the clock inputs of the image generator, the video signal generator and the counting input of the address counter, the output of which is connected to the input of the sync signal generator, the first output of which is connected to the synchronous input of the television indicator, the outputs of the address counter group are connected to the information inputs of the second group of the address switch, the first the control input of which is connected to the second output of the sync signal generator, the outputs of the address switch are connected to the address inputs of the primary O and the second RAM blocks, the first control input of the second RAM block is connected to the output of the first control signal generator, the outputs of the second RAM block are connected to the information inputs of the video signal generator, the outputs of the groups of which are connected to the control inputs of the group registers, the outputs of which are connected to the information inputs of the data switch, the outputs of which are connected to the information inputs of the television indicator, the control input of the data switch is connected to the output of the video signal maker, the information inputs of the group registers are connected to the outputs of the first memory block, characterized in that, in order to improve the performance of the device, the information inputs of the first and second groups of the second control signal generator are connected to the outputs of the first and third The image generator groups, the control inputs of the group and the clock input of the second driver of the control signals are connected respectively to the outputs of the fourth group of the generator. minutes and output clock generator, control inputs of the switch control signals and second control signals shaper connected to the second output image generator, the outputs of the second group shaper control signals are connected to the data inputs the third group of the first address switch, the first and second outputs of the second driver of control signals are connected respectively to the information input of the image generator and 0 to the first information input of the control signal switch, the second information input of which is connected to the third output of the image generator, and the output connected to the second control 5 input of the first RAM block, the output of the image generator connected to the second control input of the address switch, information the inputs of the second group of the first memory block are connected to the outputs of the fifth group of the image generator, the third output of which is connected to the second control input of the second block of th memory. five 2. The device according to claim 1, characterized in that the second driver of the control signals comprises the third and fourth blocks of RAM, the first, second and third counters, the second address switch, the comparator, the switch, the first, second, third, the fourth and fifth AND elements, the inverter, the OR element, the control input of the first counter and the first input of the OR element are the control inputs of the group, the control inputs of the switch and the second address switch, the information inputs of the second Meters withstand, third and fourth blocks 0 main memory and information inputs of the first group of the second address switch — information inputs of the first group of driver, inputs of the first I element, control input of the second 5 counter, the second inputs of the second and third elements And - information inputs of the second group of the imager, information input switch - clock input of the imager, the output of the first 0 of the counter is the first output, and the output of the I element is the second output of the imaging unit, the outputs of the third counter and the second address switch are the outputs of the imaging group, the outputs of the second address switch are connected to the address inputs of the third and fourth RAM blocks, the outputs of which are connected respectively to the information inputs of the first comparator group and the information inputs of the third counter, the outputs of which are connected to the information inputs of the second group of the comparator, the output of which is connected to the second input one of the fourth element I and the input of the inverter, the output of which is connected to the second input r1 of that element AND, the first inputs of the fourth and fifth elements AND are connected to the first output of the switch, the second output of which is connected to the first inputs of the second and third elements AND whose outputs are connected respectively to the control inputs of the third and fourth 0 blocks of RAM, the output of the fourth element AND is connected to the second input of the OR element and the subtraction inputs of the first and second counters, the input of the first counter is connected to the output of the first element AND, the output of the OR element is connected to the control input of the third counter, the input of which is connected to the output of the fifth element And the outputs of the second counter are connected to the information inputs of the second group of the second address switch. FIG. four