SU1575231A1 - Device for presentation of graphic information on screen of television indicator - Google Patents

Abstract

The invention relates to automation and computing and can be used in information display systems on a television display screen. The purpose of the invention is to increase the speed of the device, achieved by the introduction of the second and third memory blocks 9.10, the first control signal generator 11, the second control signal generator 13, the first and second data switches 14.15, the first and second groups 16.17 registers and corresponding functional relationships. When displaying graphic information, the invention allows hardware elements to form three-dimensional image elements and reduces the loading of the image generator, reducing the amount of computation when generating the display file and information flows between the image generator and other blocks of the device. It provides a display of high-speed processes and real-time images. 5 il.

Description

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blocks of memory, the first driver 11 of the control signals, the second driver of the 13 control signals, the first 14 and second 15 data switches, the first 16 and second 17 groups of registers and the corresponding functional connections. When displaying graphic information, the invention allows hardware elements to form three-dimensional image elements and reduces the loading of the image generator, reducing the amount of computation during the formation of the display file and the information flows between the image generator and other blocks of the device. It provides a display of high-speed processes and real-time images. 5 il.

The invention relates to automation and computing technology and can be used in designing information display devices on television indicator screens.

The purpose of the invention is to increase the speed of the device.

 Figure 1 shows the functional diagram of the device; 2 shows the numbering scheme of the contours of the fields to be flooded; FIG. 3 is an example of forming a display of a volumetric figure; 4 is a functional diagram of the second driver control signals; FIG. 5 shows a functional circuit of a video signal former.

The device comprises an image generator 1, a clock pulse generator 2, an address counter 3, an address switch 4, a sync driver 5, a first memory block 6, a television indicator 7, a second memory block 9, a third memory block 10, a first driver 11 signals, the video signal driver 12, the second control signal generator 13, the first data switch 14, the second data switch 15, the first group 16 of the registers 16i are 16t and the second group 17 of the registers 17i are 17m.

The device works as follows.

When compiling a display file for reproducing contour-shaped flood flat and volumetric figures in the image, the areas of flat figures (or background) and the elements of a three-dimensional figure displayed in one color or semitone, i.e. the fields to be filled are highlighted. The contours (boundaries) of the fields to be filled are numbered with a binary code. The numbering must correspond to the sequence of contours intersected by a register horizontal scanning ray. In a standard television scan, the numbering starts from the outlines located closer to the left edge of the frame. An example of the numbering of the contours of the fields to be filled by the i-th row of the frame is shown in Fig.2. The number m of fields filled in with one color (semitone) is determined by the resolution of the second memory block 9. If it contains K bits, then the total number of fields to be filled is.

The total number of colors and half currents of the reproduced image, including the background of the screen, is determined by the size of the first block 6 of the video signal memory. If it contains I bits, then.

The device operates in three modes: write, read, and fill in the memory. The latter mode is used when reproducing the volumetric volumetric figures. The display file of an arbitrary image formed by the computer and fed through the input-output of the device to the image generator 1 includes blocks for writing contour figures, background and three-dimensional figures. In memory block 9, the contours (borders) of the fields to be filled in are recorded, in memory block 6, the codes of the colors and semitones of the dashed and filled image elements are recorded, and in memory block 10 a sign of the figure's volume.

In the write mode, the address switch 4 connects the address inputs of all memory blocks to the image generator 1 counters, and the second data switch 15 connects the information inputs of memory block 6 to the corresponding outputs of the image generator 1, eliminating the recording of special points in memory block 9 the reading of which may lead to malfunctions in the operation of the second driver 13 of the control signals and the driver 12 of the video signal. Such points are extreme points of contours, some points on horizontal lines, and points of intersection of contours. For example, in FIG. 2, the extreme points of contour 0 ... 10 located on lines ji and J2, the extreme points of contour 1 ... 11 and all points inside the horizontal segments of contour 0 ... 01, located on lines h and 4.

When reading, the address switch 4 connects the address inputs of the memory blocks to the address counter 3, and the switch 14 connects the illuminations of the television indicator 7 to the outputs of one of the registers of the first group of 16 registers. At the moment when the counter selects 3 cell addresses of block 9, in which the contours of filled fields are written, the video signal generator 12, in accordance with the circuit number, supplies a write strobe to one of the registers of register groups 16 and simultaneously, the first data switch 14 connects its outputs to the indicator lights of indicator 7,

After gating in this register group 16 registers, the fill color code of this field is remembered, which through the switch 14 enters the information inputs of the television indicator 7. Recording gates are sent from the imaging unit 12 permanently to one of the registers group 16 registers, thanks to which all color codes recorded in block 6 of memory. However, the outputs of this register when playing contour shapes and background are connected to the indicator 7 only in those moments when there is no fill. If the registers of group 16 of registers use elements as speeds, the switch 14 can be excluded. In this case, video signal driver 12 supplies, to their control inputs, signals for enabling their outputs.

When displaying a volumetric shape, it is assumed that it is observed above the background and contour (dashed) shapes and is opaque. In the fill mode, the contours of the filled fields of the figure are first recorded in the memory block 9, and the fill color codes (semitones) are recorded in the memory block 6. When recording, the first driver 11 of the control signals prevents the recording of special points in the memory block 9. Thus, extreme points a and b on the j-th line (Fig. 3) will not be recorded. After recording the contours and color codes of the fill, the fill of the volumetric figure itself in memory block 6 is actually filled. In this case, the address switch 4 connects the address inputs of all the memory blocks to the output counters of the image generator 1, and the switch 15 connects the information inputs of the memory block 6 to the outputs of the register group 17. In the process of filling in the memory, the image generator 1 line by line searches all the addresses of the memory block cells in which the information about the volumetric figure is written, in other words, forms a microrash completely covering the volumetric figure image. AT

moments of entry into the microslot of addresses of memory cells in which the contour codes of filled fields are recorded, the second driver 13, in accordance with the contour number 5, supplies the write strobe to one of the registers of registers 17 and the second switch 15 connects its output to the information inputs of memory 6 . At the same time, the volume attribute is recorded in the memory block 10. This tag is recorded at the same addresses as the memory fill.

When the figure in FIG. 3 is filled into the memory, at the moment of reading whose 5th point, which contains the point from circuit 01, located on the i-th line, the color code of field 01 is written to the first register of register group 17, the outputs of this register are connected to block 6 of memory and starts recording this color code in all cells located on this line before the cell in which point d of contour 10 is written. At the moment of reading this cell, the second register of register group 17 is written

5, the fill color code of the next field 10 and the outputs of the second register of register group 17 are already connected to the memory block 6. A code of this color is written in all cells of this line to a cell with a record

0 contour points 10. At the moment of reading this point, the outputs of the first register of register register group 17 are connected to the memory unit 6 again and the color code that was recorded in it starts to be written.

5 Similarly

change the entry codes codes fields and at point f. Fill-in memory stops after the passage of the cell with the recording of the point q of the third circuit.

0 Record the sign of volume in block 10

The memory is being produced all the time while the micro-raster searches the cells in which information about the volumetric figure is recorded (for example, from point c to point q on the i-th line). After reading the information from the cells of the memory block 9 of the contours falling into the microraste, they are zeroed. In those cases when the number of fields into which a solid figure is divided exceeds the number

0 contours τ, determined by the width of the memory block of the contours, can be filled in memory in stages.

The reading of information from the memory block 6 for reproduction on the screen of the television 5 of the viewing indicator is carried out as described above. However, at the moments of reading the volume attribute from the memory block 10 by the video signal forming unit 12, the switch 14 connects the outputs of the indicator light 7 to the outputs of the register of register group 16 in which the current color codes (semitones) are written, t, e, the highest figure is read when reading. a priority,

The second control signal generator 13 comprises a decoder 18, a group of 19 flip-flops, a decoder 20 and elements 21-21, the information inputs of the decoder 18 are the information inputs of the driver, the control and clock inputs of the decoder 18 are respectively the control and clock inputs of the driver, and exits - exits of the group shaper.

The inputs of the elements 22, 21 and 23 and the decoder 20 are respectively the first, second, third and fourth outputs of the former. One of the inputs of the element And 22 is connected to a power source (1).

The imaging unit 13 operates as follows. At the moment of the first entry into the microspace of the cell address of the memory block 9, in which the contour of the flooded field is recorded, a signal appears on one of the outputs of the decoder 18, which registers the code of the fill color in the corresponding contour number register and simultaneously flips one of the triggers groups of 19 triggers in a single state. In this case, the decoder 20, affecting the control input of the switch 15, passes the color code recorded in this register of registers group 17 to its output. When reading the next loop number for the first time, the output signal of the decoder 18 writes its color code to the next register of register groups 17 and excites the next trigger of the group of 19 triggers, and the decoder 20 passes the color code corresponding to this contour number to the output of the second switch 15. During the second reading of the number of any circuit, the decoder 18 resets the trigger of group 19 of flip-flops corresponding to this number to O, and the decoder 20 passes a different color code to the output. When any of the triggers of the 19.trigger group are in the single state, the decoder 20, acting on the element 21, passes to its output the write pulses into blocks 6 and 10 of memory. Element 23 on the command of the image generator 1 transmits pulses to write the code of the loop number to the first driver 11 of the control signals. At the moments when the outputs of the group 17 of the fill color code registers are connected to the output of the switch 15, a single signal appears at the output of the element 22, which is recorded in memory 10 as an indication of volume, Memory 10 is used to store only one sign, so it one bit.

Shaper 12 of the video signal contains the first 24 and second 25 decoders and a group of 26 trigger 26i - 26m. The clock input and information inputs of the first decoder 24 are clock inputs and information inputs of the body, and the outputs of the first decoder 24 are the outputs of the driver. The clock input of the second decoder 25 is the control input of the driver.

The operation of the video signal generator 12 is similar to the operation of the second control signal generator 13, with the only difference that, upon receipt of signs of a volume figure from memory block 10, the decoder 25 passes to the output

0 switch 14 color code video signal recorded in the first of the registers of the group of 16 registers. In the video signal generator shown in FIG. 5, the gate input of the first register of group 16

5 registers are connected to a generator of 2 clock pulses by a circuit that passes through the shaper 12. In general, it may be necessary to switch this circuit in the shaper.

0 12,

The structure of the first driver 11 of the control signals for singling out specific points depends largely on the nature of the fields to be filled. In the simplest case, it can be built on logic circuits in the form of a discriminator of special points that controls the arrival of recording pulses in memory block 9 based on the analysis of the working signals of the image generator 1.

0 The bit width of the address inputs of the 6, 9, and 10 memory blocks and the inputs of the switch 4 is determined by the requirements for the resolution of the reproduced image. When using standard TV IGUs (625 lines X 625 elements) as an indicator, it is advisable to limit them to eighteen bits. In this case, the reproduced image will contain 512 lines X 512 elements

0 per line.

The use in the proposed device of blocks for forming the priming vectors for filling flat figures or background according to the information about the contours of the flooded fields recorded in the memory block 9 makes it possible to significantly reduce the loading of the image generator 1, reduce the amount of computations to the computer and the information flow between the computer and 1 image generator when reproducing water-filled shapes

in comparison with the known devices, as a result of which the proposed device provides high speed sufficient to reflect the dynamics of fast processes and real-time images.

Claims (1)

An apparatus for displaying graphical information on a television indicator screen comprising an image generator, a clock generator, an address counter, an address switch, a clock generator, a first memory block, a video driver, an input image of the image generator, an output input of the device, outputs the first group of the image generator is connected to the information inputs of the first group of the address switch; the output of the clock generator is connected to the clock input the image generator and the counting input of the address counter, the output of which is connected to the input of the sync signal generator, the first output of which is connected to the clock input of the television indicator, the outputs of the address counter group are connected to the information inputs of the second group of the address switch, the control input of which is connected to the second output of the sync signal generator, outputs the address switch is connected to the address inputs of the first memory block, characterized in that, in order to increase the speed of the device, it contains the second and third memory blocks, the first and second control signal drivers, the first and second data switches, the first and second groups of registers, the outputs of the address switch are connected to the address inputs of the second and third memory blocks, the outputs of the second memory block are connected to the information of the second control signal generator and video signal generator, the outputs of the group of which are connected to the control inputs of the registers of the first group, the outputs of which are connected to the information inputs of the first driver control signals, the outputs which are connected to the information inputs of the television indicator, the control input of the first data switch is connected to the output of the video signal generator, the control input of which is connected to the output of the third memory block, the information and control inputs of which are connected respectively to the first and second outputs of the second control signal generator, the control and clock inputs of which are connected respectively to the first outputs of the image generator and the clock generator output connected to the clock input of the video signal generator, the third and fourth outputs of the second control signal generator are connected to the information input of the first control signal generator and the control input of the first one, respectively data switch, informational inputs of the first and second; groups of which are connected respectively with the outputs of the registers of the second group and the outputs of the second group of the generator depicted. the outputs of the third group of which are connected to the information inputs of the second memory block, the control input of which is connected to the output of the first driver of control signals, the control input of which is connected to the second output of the image generator, the control input of the first memory block is connected to the second output of the second driver control signals whose group outputs are connected to control inputs of registers of the second group, information inputs of which are connected to the outputs of the first memory block, information inputs which are connected to the outputs of the second the data switch; the information inputs of the registers of the first group are connected to the outputs of the first memory block. Fig.Z