SU1064293A1 - Device for displaying information - Google Patents

Abstract

1. A DEVICE FOR DISPLAYING INFORMATION containing a matrix display panel, the horizontal and vertical buses of which through the first and second switching units are connected respectively to the decoder and the first register, the memory block whose first input is the input of the device, and the output is connected to one of the inputs a comparison unit whose other input is connected to the output of the counter. sweep, block synchronization, the first output of which. connected to the input of the sweep counter and the second input of the memory block, the second output to the first input of the first register, the third output of the synchronization block connected to the third input of the block, the memory, which is In order to improve the accuracy of the displayed information, it contains the second and third registers, the first and second triggers, and the continuous imaging unit, the first input of which is connected to the fourth output of the synchronization unit, the third output of the synchronization unit is connected to the second and third inputs of the pho world of the continuous image and the first input of the second register, the second output of the synchronization unit is connected to the first input of the third register, the second input of which is connected to the output of the scan counter, and the first input of the second trigger, the second input of which is connected to the output of the second trigger the trigger is connected to the input of the synchronization unit, the first output of which is connected to the first input of the first trigger, the second input of which is connected to the output of the continuous imaging unit connected to the second input of the second register, the output of which is connected to the first register, is the third output (the Pth register is connected to the decoder. 2. The device according to claim 1, wherein the continuous formation imaging unit includes the third and fourth triggers, the inputs of which are the second, fifth, third and fourth inputs of the block, respectively; NOT, AND, OR and adder in C5 modulo 2, the output of the element OR is 4 GO CO, the output of the block, one of the inputs of which is connected to the output of the element AND, and the other input is the fifth input of the block to you: 4odu fourth trigger, and the other input of the element And and one of the inputs of the adder The modules 2 are fourth input unit, one input of OR-NO element is connected to the output of the third flip-flop and another input his HVL a first input unit; the other input of the modulo 2 adder is connected to the output of the fourth trigger; the output of the modulo 2 adder is connected to one of the inputs of the AND element.

Description

The invention relates to automation and computing and is intended to reproduce graphic information on a display panel.

Known display devices include an indicator panel, memory blocks, synchronization, vertical and horizontal bus switching, a scan counter Cl3

With a large number of vertical tires, the time allocated for connecting each column in these devices is small, which is a drawback of the device.

The closest to the present invention is a display device containing a matrix indicator panel, the buses of which through - the first and second switching units are connected respectively to the decoder and the first register. The outputs of the memory unit are connected to the same inputs of the comparison circuit. ; sEe the second inputs are connected to the outputs. sweep counter. The outputs of the synchronization circuit are connected to a sweep counter, a memory unit synchronized with the input of the first register.

Reproduction of information by this device is carried out when the horizontal busbars of the display panel are connected in series and the synchronous excitation of the necessary vertical busbars, i.e. the excitation time of each of the connected cells does not depend on the number of vertical tires 2.

However, the image formed with this device is of low quality, since only panel cells associated with codes stored in the memory block participate in image synthesis, and therefore only one cell is excited in any of the columns of the display panel. If the panel displays a graph of a process that varies with high speed, then in the cells of the memory unit with neighboring addresses, the values of the codes that differ significantly from each other will be recorded. Then the cells of the neighboring columns participating in the synthesis of the image are spaced far from each other by a considerable distance, which makes it difficult to perceive the displayed information.

The purpose of the invention is to improve the accuracy of the displayed information.

The goal is achieved in that the device containing the matrix display panel, the horizontal and vertical tires of which are connected via the first and second switching units to the decoder and the first register, respectively, to the memory block whose first input is the input of the device and the output is connected to one from the inputs of the comparison unit, another input of which is connected to the output of the sweep counter, the synchronization unit, the first output of which is connected to the input of the sweep counter and the second

10 to the memory unit input, the second output to the first input of the first register, the third output of the synchronization unit is connected to the third input of the memory unit, the second and the third are entered

5 registers, first and second triggers, block:) world of continuous image, the first input of which is connected to the fourth output of the synchronization unit, the third output

The synchronization unit n is connected to the second and third inputs of the continuous imaging unit and the first input of the second register, the second output of the synchronization block is connected to the first input of the third register, the second input of which is connected to the output of the scan counter, and the first input of the second trigger, the second input of which is connected . with the output of the first trigger, and the output of the second trigger is connected to the input of the synchronization unit, the first output of which is connected to the first input of the first trigger, the second input of which is connected to

5 to the output of the continuous imaging unit connected to the second input of the second register, the output of which is connected to the first register, the output of the third register. with seshifrg tsrom.

The continuous imaging unit contains a third and

with the fourth flip-flops, whose inputs are the second, fifth, third and fourth inputs of the block, respectively, the elements OR NOT, AND, OR, and the modulo 2 adder, the OR cell of the OR element is the output of the block, one of whose inputs is connected respectively And the other input is the fifth input of the block, one of the inputs of the AND element is connected to the output of the fourth trigger, and the other input of the And element and one of the inputs of the modulo 2 adder are the fourth input of the block, one of the input of the element OR is NOT connected to the output of the third trigger,

0 and its other input is the first input of the block, another input of modulo 2 is connected to the output of the fourth trigger, the output of modulator 2 is connected to one,

5 from the input element I.

FIG. 1 shows the functional scheme of the device; Fig.2 is a functional diagram of the synchronization unit.

The device contains a matrix display panel 1, the first and second switching blocks 2 and 3, a decoder 4, a sweep counter 5, a synchronization block 6, a first register 7, a comparison block 8, a memory block 9, a second 10 and a third 11 registers, the first 12 and the second 13 triggers, block 14 forming a continuous image.

 The continuous image forming unit 14 comprises the third 15 and fourth 16 triggers, an OR-NOT 17 element, an OR 18 element, an adder 19 element 2 modulo, an AND 20 element.

The synchronization unit 6 comprises a pulse generator 21, a second 22 and a third And 23 elements, a counter 24, a decoder 25 microinstructions and a fifth trigger 26.

The device works as follows.

The input code sequence corresponding to the reference ordinates of the monitored process graph is recorded in memory block 9 and stored in it for the entire duration of the image playback. At the moment of synchronization by the synchronization unit 6 forming the next impulse arriving at the synchronization inputs of the first 7 and third 11 registers, the first register 7 records information containing c in the second register 10, and the counter 5 code of the sweep is recorded in the third register 11. The output signal of the decoder 7, arriving at the first switching unit 2, provides for the excitation of the next (adjacent) horizontal bus of the display panel 1 corresponding to the contents of the third register 11. The required vertical buses of the indicator panel 1 are selected using the second switching unit 3 which receives signals from the outputs of the first register 7.

After the information is transferred to the first 7 and third 11 registers by the synchronization unit 6, the next signal is generated, which accesses the sweep counter 5, changes its state to the smallest unit, sets the memory unit 9 to the initial state. Next, the formation of the control signals for driving vertical bars of the indicator panel 1, the cells of which will participate in image synthesis when the next horizontal bus of panel 1 is connected. For this, block 6

synchronization, a sequence of M pulses is generated, which interrogates the N cells of memory block 9 and records the output signals 14 of the formation of a continuous image in the second register 10.

Consider the operation of the continuous image forming unit 14 in more detail. When a 1st pulse of the specified sequence is generated, the code v stored in the i-th cell of the memory block 9 and associated with the i-y column of the display panel 1, which goes to one

from the inputs of block 8 comparison. Its other inputs are supplied with a code from the output of the counter 5 sweep Sg.

If the values of the codes -Sj and y are equal, then regardless of the state of the flip-flops 15 and 16 from the output of the block

  8 comparisons through the element OR 18 to the information input of the second register 10 enters a signal, which is recorded with the same 1st pulse of the sequence in the second

5 register 10. Since the number of pulses in a sequence is equal to the number of cells in register 10, after the arrival of the remaining N – i pulses, this signal will appear in the i-th cell

0 of the second register 10 and in the future will be transferred to the first register 7, ensuring the excitation of the cell of the i-ro column of panel 1 associated with the input code stored by f-y

5 address. The discussed functional-on-link provides reproduction of the image by the main (reference) codes, xpaHHtvibiM in block 9 of memory.

0 To excite cells that create a continuous graph effect, while simultaneously recording the output of the continuous imager to the second register 10,

C B triggers 15 and 16 delays record the output signals of comparison unit 8. If only the current V, or only the previous one is the code value from the output of memory block 9 less than the current value of the code of the counter 5 sweep, then at the output of the adder 19 modulo 2 the output signal is equal to one and goes to. the input element is And 20. Let the signal at its second input be equal to one.

5 Then the output signal of the element AND 20, coming through the element OR 18 to the information input of the second register 10, will provide the excitation of additional cells of the i-column, located between the horizontal tires corresponding to the reference ordinates of V, and f - f If the current V , - and previous Vj code values stored in memory block 9,

5 less or more output code

the scan counter 5, the output signal of the adder 19 modulo 2 is zero and does not affect the image formation process. If the previous output code value of memory block 9 V | .j is equal to the output code of sweep counter 5, then when generating the t-ro pulse of the considered sequence, the trigger 15 will be in an excited state. Its output | 1 input to the input element AND 20 through the element OR NOT 17 prevents the modulo 2 from the output signal of the adder 19 from passing to the information input of the second register 10. This allows unambiguous reproduction of images with any combination of the current v; & &: it. codes. Since for the code l. Associated with the first column of panel 1, the previous value may not exist, when forming the image for the first column in the proposed device, the synchronization unit 6 generates a signal prohibiting the output signal of the adder 19 to the information input second. ten.

In order to reduce the connection time of horizontal tires at the moment when the next pulse arrives at the scan counter 5, the trigger 12 is set to one. If during the formation of control signals that provide the excitation of vertical tires when connecting the next row of the panel

If one of the cells of the second register 10 does not turn out to be excited, then the state of the trigger 11 will not change. Then at the moment of transferring information to the first 7 and the third 11 registers will turn to trigger 13 in the excited state, the next the device operation cycle reduces the connection time of the next horizontal bus. If at least one of the cells of the second register 10 turns out to be in the excited state, then the trigger 12, and, consequently, the trigger 13 will be in the zero state

5 and the duration of the connection of the next horizontal bus panel 1 does not change

Thus, the proposed device provides an increase in the quality of the formed image, and for its construction a small number of elements are required, as well as image reproduction.

5 in the usual form and in the form of histograms. In the first case, the information input of the second register 10 must be output only from the output of block 8 cpaBHeHHiFi. In the second case, the first register 7 must be accumulating and be restored to its original state at the beginning of each imaging frame.

j Technical and economic efficiency of the invention is to improve the quality of the displayed information.

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Claims (2)

1. DEVICE FOR DISPLAYING INFORMATION, comprising a matrix display panel, lit. the horizontal and vertical buses of which through the first and second switching units are connected respectively to the decoder and the first register, a memory unit, the first input of which is the input of the device, and the output is connected to one of the inputs of the comparison unit, the other input of which is connected to the output of the counter 'scan synchronization, the first output of which is connected to the input of the scan counter and the second input of the memory unit, the second output is to the first input of the first register, the third output of the synchronization unit is connected to the third input of the memory unit and, in the light of the fact that, in order to increase the accuracy of the displayed information, it contains the second and third registers, the first and second triggers and the first block for generating continuous ¹ image, the first input of which is connected to the fourth output of the block synchronization, the third output of the synchronization unit is connected to the second and third inputs of the continuous imaging unit and the first input of the second register, the second output of the synchronization unit is connected to the first input of the third register, the second input of which is connected to the output of the counter scan, and the first input of the second trigger, the second input of which is connected to the output of the first trigger, and the output of the second trigger is connected to the input of the synchronization unit, the first output of which is connected to the first input of the first trigger, the second input of which is connected to the output of the continuous formation unit image connected to the second input of the second PE _with Giustra, © whose output is connected to the first register, the third register output connected to a decoder. 2. The device according to claim 1, the clause is that the continuous image forming unit comprises third and fourth triggers, the inputs of which are, respectively, the second, fifth, third and fourth inputs of the block, OR elements, AND, OR and the adder modulo 2, the output of the OR element is the output of the block, one of the inputs of which is connected to the output of the And element, and the other input is the fifth input of the block, one of the inputs of the And element is connected to the output of the fourth trigger, and the other input of the And element the first one of the inputs of the adder modulo 2 are four the first input of the block, one of the input of the element is NOT connected to the output of the third trigger, and the other input is the first input of the block; the other input of the adder modulo 2 is connected to the output of the fourth trigger, the output of the adder modulo 2 is connected to one of the inputs of the element I. SU ... 1064293