JP2537250B2 - Information signal processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information signal processing device, and more particularly to an information signal processing device for storing, reading and outputting an information signal using a memory.

[Conventional technology]

As a conventional information signal storage circuit, for example, an image signal storage circuit has a structure as shown in FIG.

In FIG. 3, 2 is a composite image signal input terminal, 4 is A /
D converter, 6 is a memory, 8 is a D / A converter, 10 is a composite image signal output terminal, 12 is a memory control circuit, 14 is a composite sync signal separation circuit, 16 is a horizontal synchronization (HS) separation circuit, 18
Is a vertical synchronization (Vs) separation circuit, 20 is a clock signal generation circuit that generates a clock signal for writing, 21 is a clock signal generation circuit for reading, 22 is an address counter of the memory, 23 is a switching switch, and 24 is a logical sum. An OR gate to be realized, 26 is an initial address designating circuit for designating an initial address to the address counter 22, and 28 is a system controller.

The operation of the image signal storage circuit shown in FIG. 3 will be described below.

The composite image signal input from the input terminal 2 is supplied to the A / D converter 4 and the composite sync signal separation circuit 14, and is separated from the composite image signal input from the input terminal 2 in the composite sync signal separation circuit 14. The composite sync signal is supplied to the horizontal sync signal separation circuit 16 and the vertical sync signal separation circuit 18, and the horizontal sync signal Hs and the vertical sync signal Vs are separated in the respective separation circuits.

On the other hand, when an instruction unit (not shown) instructs the system controller 28 to write the composite image signal, the vertical sync signal separated by the vertical sync signal separation circuit 18 is supplied from the system controller.
In synchronization with Vs, a high level (H) write instruction signal as shown in FIG. 4 is output to the memory control circuit 12, the address counter 22 and the switching switch 23.

The switching switch 23 is connected to the S side in the figure during the period when the supplied write instruction signal is H, and is synchronized with the horizontal synchronizing signal Hs separated by the horizontal synchronizing signal separating circuit 16 to generate the clock signal generating circuit 20. Causes the clock signal for memory writing to be sent to the address counter 22 via the switch 23.
Is supplied to.

The memory control circuit 12 outputs memory control signals such as predetermined RAS (row address fetch signal), CAS (column address fetch signal), and WE (write enable signal) to the memory 6 while the write instruction signal is H. To do.

WE is a signal that puts the memory into a data write enable state when it is at a high (H) level and puts the memory into a data write disable state when at a low (L) level. That is, when an H level write instruction signal is supplied from the system controller 28 to the memory control circuit 12, the memory control circuit 12 outputs WE at an H level to the memory 6 and sets the memory 6 in a data write enable state. Conversely, when the system controller 28 supplies the L level write instruction signal, the memory control circuit 12 outputs the L level WE to the memory 6, and the memory 6 is in the data write inhibit state, that is, the data write state. To the read state.

On the other hand, the address of the memory 6 is the address counter 22.
The address counter 22 outputs the initial address data output from the initial address designating circuit 26 in synchronization with the falling edge of the vertical sync signal Vs input via the OR gate 24. take in.

Then, the address counter 22 initializes the address using the fetched initial address data, and then, in synchronization with the write clock signal supplied from the clock signal generation circuit 20 via the switching switch 23. The address data to be set is supplied to the memory 6 and is incremented by one.

The memory 6 fetches the row address data and the column address data supplied from the address counter 22 based on RAS and CAS output from the memory control circuit 12,
A write address on the memory 6 is designated.

When the storage of the composite image signal is instructed as described above, for example, the input composite image signal for one field is input to the A / D converter 4
The clock signal generating circuit 20 converts it to digital composite image data based on the clock signal supplied via the switching switch 23, and then supplies it to the memory 6 for writing on the memory 6 designated as described above. Stored in the address.

Next, as shown in FIG. 4, the write instruction signal output from the system controller 28 returns to the low level (L),
When a data read operation from the memory is instructed, the switching switch 23 is connected to the R side in the figure and the memory control circuit 12 outputs the L level WE to the memory 6 so that the memory 6 can be read. Then, the image data stored in the memory 6 is read out.

The address counter 22 sets the read address on the memory 6 at the time of reading.

The write instruction signal output from the system controller 28 is supplied to the address counter 22, and the address counter 22 is synchronized with the falling edge of the supplied write instruction signal by the initial address designating circuit 26. After the data is fetched and the initial address data is fetched, the address is initialized, and then the switch signal is switched from the clock signal generation circuit 21.
The address data set in synchronization with the read clock signal supplied via 23 is supplied to the memory 6 and incremented by one count.

The address counter 22 used here outputs the carrier signal CR when the counter in the address counter 22 counts up, and outputs the carrier signal CR.
CR is re-input to the address counter 22 via the OR gate 24, and at the input timing of this carrier signal CR, the initial address data output from the initial address designating circuit 26 is again fetched to the address counter 22 and stored in the address counter. Initialize the address in the counter.

The address counter 22 outputs the carrier signal CR one field after the initial address is captured, and when the image data is read from the memory, the carrier signal CR captures the initial address data. Is continued in the field cycle, and the reading operation of the image data is continued.

[Problems to be solved by the invention]

However, in the above-mentioned conventional apparatus, the counter in the address counter during the operation of reading the image data from the memory reads the image data by re-acquiring the initial address data by the carrier signal output when the count-up is performed. Since it is continued, the field cycle at the time of reading the image data is from the time when the initial address data is fetched to the time when the carrier signal is output, and one device can output a plurality of types of image signals (for example, NTSC) with different field cycles. In the case of the system television signal, color signal: 59.94Hz, monochrome signal: 60Hz, PAL
Or in the case of SECAM method: 50Hz), when reading out, the type of the input image signal must be detected and the setting of the initial address must be changed according to the type of the detected image signal. The initial address designating circuit must be constructed so as to be able to output a plurality of types of initial address data, which complicates the configuration of the device and leads to cost increase.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide an information signal processing device capable of reducing the cost by simplifying the configuration of a device for temporarily storing and reading an information signal including a synchronization signal. To do.

[Means for solving problems]

In consideration of the above problems, the information signal processing device of the present invention,
An apparatus for handling an information signal including a synchronization signal, comprising: storage means for storing information data obtained by digitizing the information signal; reading means for reading the information data from the storage means; and the storage means. The restoring means for converting the read information data into an analog signal and restoring and outputting the information signal, and the synchronizing signal included in the information signal output from the restoring means are detected, and the synchronizing signal is synchronized with the detected synchronizing signal. And a control means for controlling the read timing of the predetermined address by the read means.

[Action]

With the above configuration, when the information data is read, the read timing of the predetermined address in the storage unit is controlled by the synchronization signal included in the restored information signal, thereby simplifying the control of the read timing of the predetermined address. You will be able to do things.

〔Example〕

 Hereinafter, the present invention will be described based on examples.

FIG. 1 is a diagram showing a schematic configuration of an image signal storage circuit to which the present invention is applied, as an embodiment of the present invention. In FIG. 1, the same parts as those in the circuit shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, 50 is a composite sync signal separation circuit for separating a composite sync signal from a composite video signal read from the memory 6, D / A converted by the D / A converter 8 and restored, and 52 is the composite sync signal. A vertical sync signal separation circuit for separating the vertical sync signal Vs' from the composite sync signal separated by the separation circuit 50, 51 an address counter for forming a write or read address of the memory 6, 54 a vertical sync signal separation circuit 18. OR gate 24 of the generated vertical synchronization signal Vs ′
A switch 53 for supplying or squeezing to and from a system controller 53 for controlling the memory control circuit and the switch 54.

The operation of the image signal storage circuit shown in FIG. 1 will be described below.

The composite image signal input from the input terminal 2 is supplied to the A / D converter 4 and the composite sync signal separation circuit 14, and is separated from the composite image signal input from the input terminal 2 in the composite sync signal separation circuit 14. The composite sync signal is supplied to the horizontal sync signal separation circuit 16 and the vertical sync signal separation circuit 18, and the horizontal sync signal Hs and the vertical sync signal Vs are separated in the respective separation circuits.

On the other hand, when an instruction unit (not shown) instructs the system controller 53 to write the composite image signal, the vertical sync signal separated and supplied by the vertical sync signal separation circuit 18 is supplied from the system controller 53. In synchronization with Vs, a high-level (H) write instruction signal as shown in FIG. 2 is output to the memory control circuit 12, the address counter 51, and the switching switch 23. The write instruction signal becomes H level in synchronization with the fall of the first vertical sync signal, and switches to the L level after the time T shown in FIG. 2 from the fall of the second vertical sync signal. It is a signal.

In addition, the system controller 53 switches in synchronization with the timing when the write instruction signal is switched to the H level.
An H level switch control signal is output to 54. Switch
As shown in FIG. 2, 54 is in the ON state when the switch control signal output from the system controller 53 is at the H level, and is in the OFF state when it is at the L level. The switch control signal is adapted to switch to the L level in synchronization with the switching of the write instruction signal output from the system controller 53 to the L level, and the switch 54 is inputted after the completion of the write operation to the memory 6. The supply of the vertical synchronizing signal Vs separated from the composite image signal is stopped.

As described above, while the write instruction signal output from the system controller 53 is at the H level, the address counter is
The vertical sync signal Vs separated by the vertical sync signal separation circuit 18 from the input composite image signal is connected to the switch 51 and the OR gate 24.
The counter in the address counter 51 is reset in synchronism with the falling edge of the first vertical synchronizing signal Vs supplied.

On the other hand, the switching switch 23 is connected to the S side in the figure during the period when the supplied write instruction signal is at the H level, and the horizontal synchronizing signal Hs separated by the horizontal synchronizing signal separating circuit 16 is supplied.
In synchronism with the above, the clock signal generating circuit 20 supplies the clock signal for memory writing to the address counter 51 via the switching switch 23.

Further, during the period when the write instruction signal is at H level,
The memory control circuit 12 uses predetermined RAS (row address fetch signal), CAS (column address fetch signal), WE
A memory control signal such as a (write enable signal) is sent to the memory 6
Output to.

WE is a signal that puts the memory into a data write enable state when it is at a high (H) level and puts the memory into a data write disable state when at a low (L) level. That is, when the memory controller circuit 12 is supplied with the H level storage instruction signal from the system controller 53, the memory control circuit 12 sends the H level WE to the memory 6.
Is output, and the memory 6 is set to the data write enable state,
On the contrary, when the L level storage instruction signal is supplied from the system controller 53, the memory control circuit 12 outputs the L level WE to the memory 6, and the memory 6 is in the data write prohibited state, that is, the data read. Enable it.

The address of the memory 6 is the address counter 51.
The address counter 51 is set in the address counter 51 in synchronization with the falling edge of the first vertical synchronizing signal Vs input via the switch 54 and the OR gate 24 as described above. The counter is reset and the reset address counter 51 has a clock signal generating circuit.
Address data set in synchronization with the write clock signal supplied from the switch 20 via the switching switch 23 is supplied to the memory 6 and is incremented by one.

The memory 6 fetches the row address data and the column address data supplied from the address counter 51 based on RAS and CAS output from the memory control circuit 12,
A write address on the memory 6 is designated.

When the storage of the composite image signal is instructed as described above, the input composite image signal is converted into a digital signal based on the clock signal supplied from the clock signal generating circuit 20 by the A / D converter 4 through the switching switch 23. It is supplied to the memory 6 after being converted into the composite image data of and stored in the write address on the memory 6 designated as described above.

Next, as shown in FIG. 2, when the write instruction signal output from the system controller 51 returns to the L level, the data writing operation to the memory 6 is terminated and the L level write instruction signal is supplied. The switching switch 23 is connected to the R side in the figure and also has a memory control circuit.
As described above, W of L level is output to the memory 6 from 12 and the image data stored in the memory 6 can be read.

When the system controller 53 outputs a read start pulse Ps as shown in FIG. 2, the address counter 22 sets the read address on the memory 6 during the read operation and stores it in the memory 6. Image data is read.

That is, the read start pulse Ps is supplied to the address counter 51 from the system controller 53 via the OR gate 24 as described above, and the address counter 51 resets in synchronization with the falling of the supplied read start pulse Ps. After resetting, the address data set in synchronization with the read clock signal supplied from the clock signal generating circuit 21 via the switching switch 23 is supplied to the memory 6 and incremented by one count.

The row address data and the column address data output from the address counter 51 are supplied to the memory 6,
Output from the memory control circuit 12 in the memory 6
The read address on the memory 6 is designated based on the RAS and CAS.

The composite image data stored at the designated addresses by sequentially designating the read addresses on the memory 6 as described above is supplied to the D / A converter 8.

The D / A converter 8 is supplied with a read clock signal from the clock signal generation circuit 21 via the switching switch 23, and is converted into an analog composite image signal based on the read clock signal and output from the output terminal 10. To be done.

On the other hand, the analog composite image signal output from the D / A converter 8 is supplied to the composite sync signal separation circuit 50, which separates the composite sync signal from the analog composite image signal read out here, and further the vertical sync signal separation circuit. Vertical sync signal Vs ′ at 52
Is separated and supplied to the OR gate 24.

Then, the address counter 51 is reset to the initial address value in synchronization with the timing of the falling edge of the vertical synchronizing signal Vs' input via the OR gate 24, and after the reset, the switching switch 23 from the clock signal generating circuit 21. The address data set in synchronization with the reading clock signal supplied via the memory 6 is supplied to the memory 6, and the image data written at the address designated by the address data on the memory 6 is read out. It is incremented by one count.

As described above, the image data stored in the memory 6 is designated by the address data output from the address counter 51 and repeatedly read, and the reset of the address counter 51 is restored from the read image data. Since it is performed at the timing of the falling edge of the vertical synchronizing signal Vs ′ separated from the composite image signal, it is not necessary to output a carry signal as in the conventional case from the address counter 51, and a plurality of types having different field periods are used. Even when the image signal is stored, it is not necessary to provide the initial address designating circuit 26 and change the setting of the initial address, so that the structure of the device can be simplified.

〔The invention's effect〕

As described above, according to the present invention, the information signal including the synchronization signal is temporarily stored at a low cost with a simple configuration,
It is possible to provide an information signal processing device which can be read.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an image signal storage circuit to which the present invention is applied, as an embodiment of the present invention. FIG. 2 is a diagram showing operation timing charts of the image storage signal circuit shown in FIG. FIG. 3 is a diagram showing a schematic configuration of an image signal storage circuit as a conventional example. FIG. 4 is a diagram showing an operation timing chart of the image signal storage circuit shown in FIG. 6 …… Memory 50 …… Composite sync signal separation circuit 51 …… Address counter 52 …… Vertical sync signal separation circuit 53 …… System controller

Claims (1)

(57) [Claims] 1. An apparatus for handling an information signal including a synchronization signal, comprising: storage means for storing information data obtained by digitizing the information signal; and reading means for reading the information data from the storage means. A restoring unit that converts the information data read from the storage unit into an analog signal and restores and outputs the information signal; and a synchronizing signal included in the information signal output from the restoring unit is detected, and the detected synchronizing signal is converted into the detected synchronizing signal. And an information signal processing device, which synchronously controls a timing of reading a predetermined address by the reading means.