JP3274479B2 - Image storage method and image storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image storage method and an image storage device, and more particularly to an image storage method and an image storage device for storing an image of one frame of a television signal.

[0002]

2. Description of the Related Art Conventionally, there has been known an image storage device for storing image data obtained by analog-to-digital conversion of a video signal of one frame of a television signal in a memory (storage means). An image-dedicated SRAM (static random access memory), which has a buffer circuit for holding data for one horizontal scanning period and outputting the data to a memory cell, which can switch a column address of a storage address at a high speed, is used. It had been.

[0003]

However, in the conventional image storage device, since the SRAM dedicated to image data has a small storage capacity, for example, a 256 Kbit SRAM is used to store one frame of a television signal. 5 to 8 were used. Further, since the SRAM has a relatively large number of elements per bit, it is difficult to reduce the size of the device. Furthermore, the SRAM dedicated to image data is very expensive and has the disadvantage of increasing the manufacturing cost.

If a general-purpose DRAM (Dynamic Random Access Memory) is used as a storage means to make the apparatus inexpensive, the switching speed of the storage address is slow. There was a problem that image quality was lost due to partial loss.

In view of the above, the present invention provides a general-purpose DRA
It is an object of the present invention to provide an image storage method and an image storage device that can be configured to be small and inexpensive without deteriorating image quality using M.

[0006]

In order to solve the above-mentioned problems, an image storage device according to the present invention comprises input means for inputting digital image data, and delays the digital image data input by the input means for a predetermined time. The first to output
Delay means and an output of the first delay means for a further predetermined time
Second delay means for delaying, address control means for controlling output of address data defined by a row address and a column address for controlling data storage in a DRAM, and the digital image inputted by the input means Storage control means for storing data in the DRAM in accordance with address data output from the address control means, wherein the storage control means controls the DRAM in accordance with a first switching of a column address of the address data. switching to digital image data delayed digital image data to be recorded in the first delay means, then before
In response to the second switching of the column address of the
Digital image data to be recorded in the DRAM
To the digital image data delayed by the second delay means.
Characterized in that it comprises a switching Ru switching means.

[0007]

[0008]

According to the present invention, the digital image data to be recorded in the DRAM 4 is switched to the digital image data delayed by the delay means 1 in accordance with the switching of the column address of the address data.
4 can prevent loss of digital image data at the time of switching addresses when recording digital image data . In particular, since a plurality of delay circuits are provided, one
The number of pixels in the horizontal video period is recorded at one column address of DRAM
If the number of pixels is larger than the number of pixels that can be
DRA while preventing loss of digital image data during
It is possible to record over three column addresses of M
You.

[0009]

[0010]

FIG . 1 shows a principle diagram of the present invention. That is,
Control signal C and dress data Dad and the clock signal C _K
Signal generating means 4 for generating _TL and digital image data.
Delay means 1 for delaying the data Dp by a predetermined time τ,
Captures address data Dad by the clock signal C _K
Input data Din is specified by the address data Dad.
Storage means 3 for sequentially storing the data at a plurality of storage addresses,
Digital image data Dp to the last storage address of the storage means 3.
After being stored as input data Din,
The digital image data Dp (τ) is stored in the storage means 3 this time.
Digital image to be stored on the ground as input data Din
Data Dp and digital image data D from the delay means 1.
p (tau) and storage means 3 is switched by the control signal C _TL
And the switching means 2 for outputting the output. The above configuration
According to the above, the switching means 2 outputs the digital image data D
p and the digit delayed by the predetermined time τ by the delay means 1
Control of the total image data Dp (τ) by the signal generation means 4
It operates so as to be switched and output by the signal _CTL . You
That is, the digital image data Dp is transmitted to the signal generating means 4.
The clock signal C _K more address data Dad
A memory device fetched and specified by the address data Dad
After being stored in the previous storage address of the stage 3, the delay unit 1
Of the digital image data Dp (τ)
Switching means 2 by means of the control signal _CTL
Is switched to the current storage address of the storage means 3.
To act. FIG. 2 is a block diagram of one embodiment of the present invention.

An image storage device according to the present embodiment captures an NTSC standard television signal as digital image data of a still image, and processes image data subjected to arithmetic processing such as reduction and enlargement to image data of a copying machine or the like, or Day
The data is transferred to a storage device for storing the data. This embodiment
Here, for the sake of simplicity, a copying machine will be used .

In FIG. 2, N coming into input terminal 11
The TSC standard television signal is separated into a luminance signal Y ₁ and a chrominance signal C ₁ by a 1HYC separation circuit 13 and input to a switch circuit 14. The switch circuit 14 also receives a luminance signal Y ₂ and a chrominance signal C ₂ from the input terminal 12, and is configured to select and output any desired luminance signal and chrominance signal by the switch circuit 14. ing.

The luminance signal Y output from the switch circuit 14 is set to a predetermined level by the AGC circuit 15 and is input to the decode circuit 16 and the sync separation circuit 25. The color signal C from the switch circuit 14 is also input to the decode circuit 16. The decoding circuit 16 decodes the luminance signal Y and the chrominance signal C, and outputs primary color signals R, G, B. The synchronization separation circuit 25 separates the composite synchronization signal Cs from the luminance signal Y from the AGC circuit 15 and outputs the composite synchronization signal Cs to the gate array 22.

The television signals converted into the primary color signals R, G, and B as described above are passed through the switch circuit 17 through the LPF.
After being band-limited by a (low-pass filter) circuit 18, it is converted into an NTSC standard television signal by an encoding circuit 19 and output to an output terminal 20 as a monitor signal.

On the other hand, the DR
One frame of still image digital image data is written into the memory circuit 24 which is an AM . That is, the R, G, and B signals band-limited by the LPF circuit 18 are input to the input means.
Are converted into parallel 24-bit digital image data, each of which is quantized by 8 bits by an AD (analog-digital) conversion circuit 21. And delay means and address
The data is written into the memory circuit 24 via the data bus 26a at a predetermined timing described later by the gate array 22 including the data control means , the storage control means, and the switching means .

The gate array 22 includes the memory circuit 2
4 is read out and output to the DA (digital-analog) conversion circuit 23. The R, G, and B signals digital-to-analog converted by the DA converter 23 are input to the switch circuit 17.

The switch circuit 17 includes R, G, and B signals obtained by decoding the NTSC standard television signal from the input terminal 11 or 12 and R, G, and B signals obtained by digital-to-analog conversion of the still image digital image data from the memory circuit 24. G and B signals are switched and output. Therefore, any one of the through composite video signal from the input terminal 11 (or 12) and the still image digital image data read from the memory circuit 24 is selectively output to the output terminal 20.

The still image digital image data stored in the memory circuit 24 is output to the arithmetic circuit 27 via the data bus 26b at a predetermined timing by the gate array 22 in accordance with a control command from the arithmetic circuit 27, and the image is converted. After reduction or enlargement processing, the image is output to a copying machine (not shown).

FIG. 3 is a block diagram of a main part of one embodiment of the present invention.

FIG. 3 shows a part of the internal block configuration of the gate array 22 in detail. Gate array 22
Generally includes a delay unit 1, a data buffer circuit 31 as a switching unit, an address control unit, and a storage control unit.
An address control circuit 32 as means and a synchronization control circuit 33
Consists of

The delay means 1 comprises D-type flip-flops 30 ₁ , 30 ₂ ,..., 30 ₅ connected in series, and sequentially delays and outputs input data in synchronization with a clock pulse Cp (clock signal). . Although omitted in FIG. 3,
A total of 24 sets of delay means 1 are prepared for a total of 24 bits of data of R, G and B signals.

The delay time of the Q output of each D-type flip-flop is the product of the period Tp of the clock pulse Cp and the number of D-type flip-flops until output. That is, the image data Dp (tau ₀₎ of Q output of D-type flip-flop 30 ₁ is delayed by the period Tp of the clock pulses Cp, the image data Dp (tau ₁₎ of the Q output of D-type flip-flop 30 ₃ only 3Tp delayed, the image data Dp (τ ₂₎ of the Q output of D-type flip-flop 30 ₅ is delayed by 5TP, is outputted to the respective data buffer circuit 31.

In this embodiment, the clock frequency is set to 776 f
_H (f _H is a horizontal synchronization frequency of 15.734 kHz), that is, 12.21 MHz. Therefore, the cycle Tp of the clock pulse Cp is set to about 82 nsec. Thus, D-shaped flip-flop 30 ₃ Q output image data Dp of (tau ₁₎ is 2 × 82 nsec delayed with respect to the image data Dp of the Q output of D-type flip-flop 30 _{1 (τ 0),} D-type flip-flop 30 ₅ Q output image data Dp of (tau ₂₎ are further 2 × 82 nsec delay.

The synchronizing control circuit 33 receives the composite synchronizing signal Cs from the synchronizing separating circuit 25 and outputs to the address control circuit 32 data for writing and reading image data and data for specifying a storage address. .

The address control circuit 32 generates a strobe signal CAS '(Column Address Strob) based on the address.
e), RAS '(Row Address Strobe), memory circuit 2
4 to the memory circuit 24, and the switching signals S1 and S0, which are control signals, to the data buffer circuit 31.

The data buffer circuit 31 switches the image data from the delay means 1 which has been delayed by predetermined times Tp, 3Tp and 5Tp in synchronization with the clock pulse Cp, respectively.
1, is switched by S0, selectively outputs to the memory circuit 24 via the data bus 26a _1.

When sampling 595 horizontal pixels and 440 vertical pixels and quantizing them with 8 bits, a memory having a capacity of 595 × 440 × 8 = 2.0944 M bits is required.

On the other hand, the memory circuit 24 has 1M bits (25
The DRAM comprises six DRAMs (6K words × 4 bits), each of which has a column address (CAS) and a row address (RA).
S) is also composed of 512, and one address stores 4-bit data. That is, the memory capacity is DRA
For each M, 512 ² × 4 = 1.049 M bits.

In this embodiment, two DRAMs are allocated to each of the R, G, and B signals, and the memory capacity is set to 2 × 512 ² × 4 = 2.0972 M bits for each signal. As a result, image data obtained by sampling one signal for 595 horizontal pixels and 440 vertical pixels and quantizing it with 8 bits can be stored. It should be noted that four bits of 8-bit data of one signal for one pixel are stored in separate DRAMs.

The total memory capacity was 3 × 2 × 512 ² × 4 = 6.2915 M bits.

FIG. 4 is a timing chart of a main part of the embodiment of the present invention shown in FIG. In FIG.
(A) is a clock pulse Cp, (B) is a strobe signal RAS ', (C) is a strobe signal CAS', (D) is a write control signal WE ', (E) is address data D _ad , and (F) is switching. Signals S0 and (G) indicate the switching signal S1, (H) indicates the image data Dp (τ ₀ ), and (I) indicates the image data Dp (τ ₁ ).

In FIG. 4, address data D _ad is based on a so-called address multiplex system, and includes column address data R ₁ , R ₂ ,... R ₅₁₂ and row address data C ₁ , C _{2 ,.}
Are input from one terminal at a shifted timing as shown in FIG.

The address data D _ad is supplied to the memory circuit 2 at the fall of the strobe signals RAS 'and CAS'.
4 For example, the strobe signal RAS '
In falling on after the column address data R ₁ is incorporated in the row address data C ₁ at the falling edge of the strobe signal CAS 'every 1Tp, C _2, ... C ₅₁₂ is sequentially taken into the DRAM of the memory circuit 24. When the write control signal WE 'is at a low level, writing is possible.
When at the high level, writing is prohibited.

Next, a case where one frame of still image data is written into the memory circuit 24 will be described with reference to FIGS.

[0035] First, writing at the start, the switching signal S1, S0 than the address control circuit 32 have been both the low level, this time the data buffer circuit 31 is the image data Dp of from D-type flip-flop 30 ₁ (tau ₀ ) is output.

The strobe signal in Fig. 4 during the time t ₀ R
AS 'column address data R ₁ is captured on the falling edge of, followed strobe signal CAS at time t ₁ and'
Row address data C ₁ is acquired at the falling of.
Similarly, row address data C ₂ ,..., C ₅₁₂ are sequentially taken into the DRAM at time t ₂ every clock signal period Tp.

[0037] Incidentally this time, D-shaped image data Dp (tau ₀₎ of from flip-flop 30 ₁ (FIG. 4 (H)) first image data D ₁ of the first pixel of the horizontal video period at time t ₁ It has become. Then, until a time t ₁ after the time t ₂ at every clock signal period Tp, until the image data D ₅₁₂ of 512-th pixel are sequentially outputted.

Then, after a predetermined access time from the fetching of each address data, the image data D ₁
From the first horizontal video period up to image data D ₅₁₂
The 8-bit image data of each signal up to the second pixel is
The data is taken into a 1M DRAM by four bits.

Next, at time t _3, in synchronization with the rising edge of the clock pulse Cp, the strobe signal RAS '
, CAS ′, the write control signal WE ′, and the switching signal S0 go high. The switching signal S1 when S0 at the low level is high, the image data D from the data buffer circuit 31 D-type flip-flop 30 ₁
D-type flip-flop 3 delayed by 2 Tp from p (τ ₀ )
0 ₃ image data Dp (tau ₁₎ than to output (FIG. 4 (I)).

Accordingly, the output of the data buffer circuit 31 outputs the image data D ₅₁₁ of the 511-th pixel from time t ₃ to time t ₄ . However, at this time, since the write control signal WE 'is at the high level, the image data _D511 is not taken into the DRAM.

Next, at time t ₄ , the write control signal WE ′ becomes low level, and data can be taken into the DRAM.

Subsequently, at time t ₅ , the D-type flip-flop 30 ₃ is applied to the output of the data buffer circuit 31.
The image data D512 of the _512th pixel is output.

Strobe signal RAS 'is supplied at time t_FiveIn
1.5T_PClock pulse after the high level period
Low level in synchronism with the pulse Cp.
R _TwoIs taken into the DRAM. This allows memorizing
Address column address is R₁To R_TwoIs switched to. This
, The column address data R_TwoIs loaded into DRAM
However, the row address data has not
Data D₅₁₂Is not loaded into the DRAM.

Then, at time t ₆ after 1 Tp, the strobe signal CAS ′ is set to the low level, and the row address data C ₁ is taken into the DRAM.
The row address data C ₁ , C ₂ ,... Every clock signal period Tp
C ₈₃ is taken in order.

By the way, at time t₆In the
The output of the buffer circuit 31 is a D-type flip-flop 30._Three
Image data of the 513th pixel in the first horizontal video period
TA D ₅₁₃Is output. And time t₆From time
t₇Up to the first horizontal video period every clock signal period Tp
Image data D of the 513-th to 595-th pixels between
₅₉₅Are sequentially output.

Thus, the image of the pixels up to the 512th pixel
Row address data of data storage address ... C₅₁₂Capture
Time t_ThreeIn the data buffer circuit 3
1 output is a D-type flip-flop 30 delayed by 2 Tp.
_ThreeImage data Dp (τ₁) To output the control signal S
Switched by 0. And time t_ThreeFrom 2T
Time t after p_FiveAt column address data R_TwoTake
Time t _FiveTime t after 1 Tp from₆Or later
For each clock signal period, the image data of
Row address data C of data storage address₁... taken in order
I will.

[0047] Thus, 512th address data row address data C ₅₁₂ storage address of the image data D ₅₁₂ of the pixel is taken into the next captured the 513-th address data storage address of the image data D ₅₁₃ pixels And the continuous image data is fetched into the continuous storage addresses.

Then, after a predetermined access time from the fetching of each address data, the image data D
From ₅₁₃ the first image data of 8 bits of each signal of 513-th and subsequent pixels in the horizontal picture period until image data D ₅₉₅ is, each row from the row address C ₁ of the column address R ₂ to C _83, four bits It is taken into a 1M DRAM.

As described above, in order to take in data of 595 pixels in one horizontal video period as continuous data in a DRAM composed of 512 (rows) × 512 (columns), image data Dp (τ ₀ ) the image data Dp (τ ₀₎ D-type flip-flop 30 ₂ against, 30 ₃ 2Tp delayed image data Dp (tau _1), and outputs switching the data buffer circuit 31 at time t _3. As a result, the data of 595 pixels in one horizontal video period is converted to the DR of the memory circuit 24 as continuous data over two column addresses.
We are taking in AM.

Next, at time t _8, RAS ', CA
S 'and WE' go high at the same time, and writing of image data is prohibited. And 98 Tp from time t ₈
At time t ₉ the later, the image data Dp (tau ₀₎ of the output from the D-type flip-flop 30 _first switching signal S0 is set to the low level data buffer circuit 31 (FIG. 4
(H)).

Note that a horizontal synchronizing signal period is included between time t ₈ and time t ₉ , and at the time t ₉ , the output of the data buffer circuit 31 is switched and DRA
M stored data is refreshed. The refresh of the data stored in the DRAM is performed once in one horizontal blanking period.

The data for 595 pixels in the second and subsequent one horizontal video period is also D data as continuous data over two column addresses or three column addresses in the same manner as described above.
It is taken into RAM.

[0053] That is, at time t ₁₀ the later 80Tp from time t ₉ the write control signal WE 'becomes possible to write data to the DRAM goes low. Then, at time t _11, 'column address data R ₂ is again taken at the falling edge of the strobe signal CAS at time t ₁₂ Following' strobe signal RAS row address data C ₈₄ at the fall of captured. Thereafter, similarly, the row address data C is output every clock signal cycle Tp.
₈₅ ,... _C512 are sequentially taken into the DRAM. Incidentally, it includes a horizontal blanking period between the time t ₈ to time t _10.

At this time, the D-type flip-flop 30₁Yo
Image data Dp (τ₀) At time t ₁₂Second in
Image data D of the first pixel in the horizontal video period₁′
ing. And time t₁₂Thereafter, the clock signal period Tp
The image data of each pixel in the second horizontal video period is
Output next. Column address R_Two, Line address₅₁₂Has 2
The image data of the 429th pixel in the horizontal image period is
It is captured.

Then, similarly to the previous time, the output data of the data buffer circuit 31 is switched from the image data Dp (τ ₀ ) to the image data Dp (τ ₁ ) simultaneously with the switching of the row address from R ₂ to R ₃ . , Row address data C ₁ ,.
₁₆₆ are taken in order and after a predetermined access time, 2
The image data of the 430th pixel to the 595th pixel in the horizontal image period is taken into the DRAM as continuous data over _two column addresses R ₂ and R ₃ .

When storing data for the seventh one horizontal video period, the column address is switched twice. That is, after a predetermined access time after the row address data C _{499 at the} column address R ₇ not shown in FIG. 4 is taken into the DRAM, the data of each signal of the first pixel is divided into two data. It is taken into a 1M DRAM.

Further, 512 of a column address R ₈ (not shown)
The data of the fifteenth through 527th pixels are sequentially taken into all the row addresses, and further, a column address R (not shown)
After a predetermined access time after the row address data _{C69 at} the time of ₉ is taken into the DRAM, data of each signal of the 595th pixel is taken in, and the DRAM as data continuous over three column addresses in total. It is taken in.

[0058] At this time, the output image data in the data buffer circuit 31 is first switched from the D image data Dp of from flip-flop 30 ₁ (tau ₀₎ in the image data Dp (tau ₁₎ than D flip-flop 30 _3, It is switched to the second time image data Dp of from D flip-flop 30 ₅ (tau ₂₎ followed. That, is a control signal S0, S1 both low level, the image data Dp of from D-type flip-flop 30 ₁ (τ ₀₎ is output when the column address data R ₇ are taken.

Next, when the column address data R ₈ is taken is the control signal S0 in synchronism with the rising edge of the strobe signal RAS 'is set to the high level, image data from D-type flip-flop 30 ₃ Dp (tau ₁ ) is output. Then, at a high level with the control signal S1 in synchronization with the rising edge of the strobe signal RAS 'is S0 when the column address data R ₉ is captured, the image data Dp of from D-type flip-flop 30 ₅
(τ ₂ ) are sequentially output from the data buffer circuit 31 and are respectively taken into the DRAM.

In this manner, the data of 595 pixels in one horizontal video period up to the 440th of the video signal of one frame of the television signal can be similarly obtained by the continuous data over two column addresses or three column addresses. Therefore, one frame of digital still image data can be stored in the memory circuit 24 without losing part of the image data when the storage address is switched.

As described above, according to this embodiment, a general-purpose D memory which is smaller and cheaper than an SRAM dedicated to image data is used.
Using the RAM, one frame of digital still image data can be stored without deteriorating image quality, and it can be read out at any time, subjected to desired image processing such as enlargement or reduction, and sent to a copying machine. .

If the capacity of the memory circuit is sufficient,
General-purpose DRAM as not only one-frame digital still image data but also moving image data as continuous image data
Can also be stored.

[0063]

As described above, according to the present invention, the digital image data to be recorded in the DRAM is switched to the digital image data delayed by the delay means in accordance with the switching of the column address of the address data.
It is possible to prevent loss of digital image data when switching addresses when recording digital image data in M. In particular, since a plurality of delay circuits are provided, one
The number of pixels in the horizontal video period is recorded at one column address of DRAM
If the number of pixels is larger than the number of pixels that can be
DRA while preventing loss of digital image data during
It is possible to record over three column addresses of M
You.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of one embodiment of the present invention.

FIG. 3 is a block diagram of a main part of one embodiment of the present invention.

FIG. 4 is a timing chart of one embodiment of the present invention.

[Explanation of symbols]

 1 delay means 2inputMeans 3Address controlMeans 4DRAM 5 Storage control means  22 Gate array 24 Memorycircuit  30₁, ... 30₅ D type flip flowUp  31 Data buffercircuit  32 Address controlcircuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-44980 (JP, A) JP-A-60-65678 (JP, A) JP-A-62-256300 (JP, A) (58) Investigation Field (Int.Cl. ⁷ , DB name) H04N 5/76-5/937

Claims (2)

(57) [Claims] An input means for inputting digital image data.
And the digital image data input by the input means.
Output with a delay of a predetermined timeFirstDelay means;The output of the first delay means is further delayed for a predetermined time.
2 delay means;  Row address for controlling data storage in DRAM
And output of address data specified by the column address.
Address control means for controlling the digital image data input by the input means.
The address data output from the address control means
Therefore, storage control means for storing the data in the DRAM is provided.
And the storage control means is a column address of the address data.
ofFirst timeAccording to the switching, the data should be recorded in the DRAM.
Digital image dataFirstDelayed by delay means
Switch to digital image dataAnd then the address
In response to the second switching of the column address of the data,
The digital image data to be recorded on the DRAM is
2 Switching to digital image data delayed by delay means
eImage storage device comprising switching means
Place. 2. An input device for inputting digital image data.
And the digital image data input in the input step.
Output with a delay of a predetermined timeFirstA delay step;The output of the first delay step is further delayed for a predetermined time
Two delay steps,  Row address for controlling data storage in DRAM
And output of address data specified by the column address.
Controlling the digital image data input in the inputting step.
Address data output from the address control step
Therefore, there is a storage control step for storing the data in the DRAM.
The storage control step includes: a column address of the address data;
ofFirst timeAccording to the switching, the data should be recorded in the DRAM.
Digital image dataFirstDelayed in the delay process
Switch to digital image dataAnd then the address
In response to the second switching of the column address of the data,
Digital image to be recorded on DRAM Data
2 Switching to digital image data delayed by delay means
eImage storage method characterized by including a switching step
Law.