KR19990031623A - Line buffer control device in dynamic RAM interface device of PDTV. - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for interfacing data by providing a line buffer in front of the main memory in order to match the access time and cycle time of image information displayed on a screen in a PDP television. will be. In particular, a line buffer control unit for controlling a line buffer in a DRAM interface device of a PDP television that stores and reads line data of a PDP television using a dynamic RAM (DRAM) includes a recording unit, a reading unit, and a vertical position selection unit. The recording clock, the recording reset, and the recording enable signal are applied to the line buffer section to record valid data in the horizontal synchronization signal of one section. The reading section starts from the position determined by the vertical position pulse applied from the vertical position selection section. Enable to read valid data. Therefore, the line buffer unit receives a certain control signal from the line buffer control unit, records valid data for one line, and reads the valid data by a vertical position pulse, thereby facilitating control of the data and storing the line data. A line buffer control apparatus is proposed in a dynamic ram interface device of a PDTV television which is reduced in size.

Description

Line buffer controller in dynamic RAM interface of PDTV.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line buffer control apparatus that temporarily stores data in order to adjust timing before storing image information displayed on a screen in a memory in a PDP television. In particular, the present invention includes a recording unit, a reading unit, and a vertical position selection unit. The present invention relates to a control apparatus of a line buffer in a DRAM interface of a PDP television that enables recording and reading of valid data of a line buffer unit by applying a control signal.

In general, there are two problems that occur when using IC memory. That is, the speed of handling the video signal is much faster than the speed of reading and writing the memory and the amount of data in the video signal is very large. For example, if the sampling frequency is 14.3 MHz, the data should be about 70 Hz (1 / 14.3 MHz). In order to be able to read and write to memory in real time, read and write operations must occur within 70 ms, and the DRAM cycle time is much slower than 200 ms. Therefore, it is necessary to collect a few bits to read and write or to slow down the external environment in which data is sent.

To help understand, the following briefly describes the access time and cycle time. First, the time required to actually read and write data by addressing the memory is called the access time, and when it is accessed continuously, the time required is called the cycle time, and the cycle time is generally longer than the access time. . In the case of SRAM, the access time and the cycle time are generally the same, but in the case of DRAM, the cycle time is usually longer than the access time because it takes time to complete the access until the next address can be accepted. In addition, DRAM (Dynamic RAM) accepts externally applied X-address and Y-address signals, selects one of many cell capacitors having a value of about 30 fF, and converts the stored charge into voltage to amplify a series of signals. The process amplifies and delivers it to the outside. At the same time as the address, the voltage input corresponding to the data from the outside is stored in a specified cell capacitor as a charge. In order to perform this function, various circuits must operate organically in several steps. On the other hand, recently developed SDRAMs (synchronously synchronous RAMs) of semiconductor memories have been widely used because they have a lower cost than SRAMs (static RAMs) and have faster access time than SRAMs (static RAMs).

1 is a block diagram of an interface apparatus for storing and accessing image information in an SDRAM instead of a DRAM according to the related art according to the present invention.

The SDRAM interface device shown in FIG. 1 is connected to a tuner circuit unit and is connected to a video decoder unit 10 for outputting a constant resolution of image information of a screen, and is connected to the video decoder unit 10 from the video decoder unit 10. Records and reads the image information applied, that is, the mode switching unit 20 for converting the interlaced mode signal into the sequential mode signal, the image information connected from the mode switching unit 20 and applied from the mode switching unit 20. A parallel input serial output (PISO) unit 40 connected to the line memory unit 32 and the line memory unit 32 and rearranging data applied in parallel from the line memory unit 32 in series; The frame memory section 34, which is connected to the section 40 and comprises a frame memory A 34a and a frame memory B 34b, which performs a process of writing and reading the serial signal applied from the PISO section 40 on a frame basis. , The mode switching unit 20 and line Rib is connected to the 32 address unit 50 to provide an appropriate address according to the write signal and the read signal of the frame memory unit 34; And

A data selection unit connected to the frame memory unit 34 and selecting image data output in the read mode from the frame memory A 34a and the frame memory B 34b of the frame memory unit 34 to be provided to the PDP unit. And a PDP 70 connected to the data selector 60.

Fig. 2 is a block diagram schematically showing the configuration of a CMOS type SDRAM in an interface device of a conventional SDRAM having the above configuration.

In one embodiment, the SDRAM has a memory array consisting of 2 banks of 1,048,576 words x 8 bits. On the other hand, in bank selection 78, program key A ₁₁ is latched by the / RAS and / CAS signals, bank A is selected when A ₁₁ is low, and bank B is selected when A ₁₁ is high.

In addition, the memory cell array 70 includes memory cells (not shown) arranged in a matrix in the row and column directions, a word line (not shown) provided in one row for each row, and a pair for each column. Contains bit line pairs (not shown). Each of the memory cells is connected to a word line of a corresponding row and a bit line pair of a corresponding column. Further, the word line is selected by the row decoder 77, and the bit line pair is selected by the column decoder 72. The word line selection in the row decoder 77 and the bit line pair selection in the column decoder are performed after the signal is applied to the column buffer 76 and the row buffer 80 by the address register 79, respectively. This is done in response to an address signal output from the decoder.

On the other hand, the / RAS (row address strobe signal) and / CAS (column address strobe signal) input to the timing register 75 again apply a clock to the row address register and the column address register. Initially, / RAS and / CAS are high, but after the setup time for the row address register elapses, the / RAS input goes low. When a row address is applied to the row buffer unit 80, the corresponding address is represented as a row decoder input. That is, in / RAS, the row enables the decoder to decode the row address and selects one row array. At the time when the row address ends and the column address starts, the corresponding column address is applied to the address input, and the / CAS input goes low to apply the column address to the column address register. The / CAS can also enable the column decoder to decode the column address and select the corresponding column array.

In addition, the refresh counter 80 of the row buffer 80 allows all cells in the same row to be refreshed every time a read operation occurs in one cell, and the sense amplifier 71 reads the data in the memory cell array. Amplify the data (read data) appearing in each bit line pair in the block.

The input / output controller 82 transmits a bit line pair in the memory cell array 80 to the data input register 81 and the output buffer 83 so as to correspond to each of the bit line pairs. And a data input register 81 and an output buffer 83 based on the most significant bit signal and the / WE signal in each of the address signals output from the row and column buffers.

A conventional SDRAM interface device for realizing a PDP screen by storing and accessing image information of a PDP television using the SDRAM as described above will be described in detail with reference to the drawings shown in FIGS. 1 and 2.

The video signal and the audio signal transmitted from the broadcasting station are received by the tuner circuit and then applied to the video decoder 10 through a predetermined process. The signals applied to the video decoder unit 10 are output to the mode switching unit 20 as signals having a constant resolution.

Since the signal applied from the video decoder 10 is an interlaced mode signal, the signal is converted into a sequential mode signal. The reason is that, unlike the cathode ray tube driving pixel by pixel, the PDP-TV's three primary color light components of red, green, and blue (RGB) produced by the target image are broken by line for a certain period of time. This is because it is a line sequential method that is converted into an electrical signal and transmitted and received. In addition, the signals converted into the sequential signals are applied to the line memory unit 32 by 8 bits for each of RGB, and are simultaneously applied to the address unit 50.

The upper 4 bits of the R 8 bits applied by the mode switching unit 20 are stored in the RA of the line memory unit 32, the lower 4 bits are stored in the RB, and the upper 4 bits of the G 8 bits are lower 4 bits in the GA. Is stored in GB, and the upper 4 bits of B 8 bits are stored in BA, and the lower 4 bits are stored in BB, respectively. Data stored in the line memory section 32 is applied to the PISO section 40 in accordance with the read and write signals.

The image data provided in parallel (MSB to LSB) in the line memory unit 32 is rearranged to be stored as bits having the same weight at one address of the frame memory 34. That is, while the first shift resister loads eight samples of image data, in the second shift resister, eight samples of previously loaded image data are sequentially ordered from the most significant bit (8 bits) to the least significant bit (8 bits). It is output while shifting to. Therefore, in order to continuously rearrange the image data provided by the line memory section 32, two first and second shift resist sections are provided, and they alternately repeat the load and shift operations. In addition, two frame memory units 34 capable of storing a single piece of image data are also provided so that they can be written and read in units of frames alternately, so that image data can be continuously stored and displayed.

Therefore, in the above-described SDRAM interface device, many modes are required in the process of storing data using the SDRAM, loading the stored data, writing and reading the data into the memory unit, and complicated control of the SDRAM.

Accordingly, the present invention has been made to solve the above problems, and the present invention relates to an interface device for recording and reading image information using a DRAM that is easier to control than an SDRAM. A line buffer control apparatus is proposed in a dynamic RAM interface device of a PDTV that controls a line buffer so that normal data can be recorded and read out according to time and cycle time.

1 is a block diagram of an SDRAM interface device of a conventional PDP television.

2 is a block diagram schematically showing a configuration of a CMOS SDRAM

3 is a block diagram of a DRAM interface device of a PDP television;

4 is a waveform diagram showing a reading and writing section for valid data during a vertical synchronization section;

5 is a block diagram of a line buffer control unit according to the present invention.

6 is a timing diagram showing a recording cycle and a reading cycle for the recording unit and the reading unit of FIG.

<Explanation of symbols for main parts of the drawings>

10: video decoder 20: mode switching unit

50: address portion 100: frame buffer portion

40, 110: PISO section 30, 120: memory section

60, 130: data selector 70, 140: PDP

150: DRAM address generator 160: load clock and shift pulse generator 170: line buffer control unit 170A: recording unit

170B: reading part 171, 174: first output port

172, 175: second output port 173, 176: third output port

180: vertical position selector

Hereinafter, embodiments of the present invention described above will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a DRAM interface device of a PDP television according to the present invention. FIG. 3 illustrates the separation of analog R / G / B and horizontal and vertical synchronization signals from an NTSC composite video signal transmitted from a broadcasting station, and APL (Average Picture Level) corresponding to an average value of brightness signals is analog to digital. A line buffer unit 100 for temporarily storing the R / G / B color signal digitized and output from the convertor unit; A parallel input serial output (PISO) unit 110 connected to the line buffer unit 100 and rearranging data in series since the R / G / B signals applied from the line buffer unit 100 are applied in parallel; A memory unit 120 connected to the PISO unit 110 and comprising a first RAM 120a and a second DRAM 120b for storing R / G / B data output from the PISO unit 110; A data selection unit 130 connected to the memory unit 120 and configured to read and output data corresponding to an address applied from the DRAM address generator 150 from the memory unit 120; A PDP (140) for displaying the R / G / B data output from the data selector (130);

A line buffer controller 170 connected to the line buffer unit 100 and controlling the line buffer unit 100; A load clock and shift pulse generating device (160) connected to the PISO unit (110) and generating load clocks and shift pulses necessary for loading data of the PISO unit (110) and shifting them to the memory unit (120); A DRAM address generator connected to the line buffer control unit 170 and the memory unit 120, applying a read clock to the line buffer control unit 170, and providing an address required by the memory unit 120. 150; The vertical position setting device 180 applies a vertical position pulse to the line buffer control unit 170 by inputting valid data and a vertical synchronization signal V Sync.

Referring to FIG. 3, the PDP television configured as described above receives an NTSC composite signal, separates analog R / G / B and horizontal and vertical synchronization signals, and uses an APL (Average Picture) corresponding to an average value of the luminance signal (Y). Level is obtained and converted into a digital signal. The R / G / B data converted to the digital value is temporarily stored in the line buffer unit 100. The R / G / B data stored in the line buffer unit 100 may be written from the output terminal of the line buffer controller 170 by a write clock, a write reset, a read clock, and a read reset. The R / G / B data is applied to the PISO unit 110 under the control of the (Read reset) signal. On the other hand, in the PDP television, for the PDP gradation processing, video data of one field is reconstructed into a plurality of subfields, and then the most significant bit (MSB; least significant bit) to least significant bit (LSB) is used. Since it is necessary to rearrange until, the PISO unit 110 rearranges the data. That is, 16 bits of R / G / B data are outputted to the R / G / B data applied in 8 bits. In addition, the PISO unit 110 reads the R / G / B data by the load clock applied to one end of the load clock and the shift pulse generator 160 and outputs the data by the shift pulse applied to the other end. do.

Data output from the PISO unit 110 is alternately output by the first DRAM 120a and the second DRAM 120b of the memory unit 120. For example, when data of the first DRAM 120a is shifted to the data selector 130, the second DRAM 120b loads data from the PISO unit 110, and the data of the second DRAM 120b is stored. When shifted to the data selector 130, the first DRAM 120a loads data from the PISO unit 110. Therefore, the first DRAM 120a and the second DRAM 120b of the memory unit 120 alternately perform load and shift operations. The data selector 130 selects data from the memory unit 120 according to a signal applied from the DRAM address generator 150 and provides the data in the form of data required by the address driving IC (not shown) of the PDP 180. Play a role.

The DRAM address generator 150 converts the image data input by the interlaced scanning method into the sequential scanning method and displays the order of writing addressing and reading addressing. That is, as described above, image data of one field stored in the memory is repeatedly read even line data after reading one line of Odd line data. Further, in the PDP gradation process, one field is divided into several subfields, and image data corresponding to each subfield must be read in order to output data, thereby having a reading order that is structurally very different from the writing order. Therefore, the DRAM address generator 150 serves to provide a corresponding address according to each operation mode (write and read mode) of the first DRAM 120a and the second DRAM 120b.

The vertical position selector 180 inputs valid data and a vertical sync signal V Sync to provide the vertical position pulse to the line buffer controller 170. The line buffer controller 170 includes a write clock, a horizontal sync signal H sync, a vertical position pulse, a vertical sync signal V sync, and a read clock applied from the DRAM address generator 150. The line buffer 100 is controlled by applying a write reset, a write clock, a read clock, a read clock, and a read reset signal to the line buffer unit 100. That is, the line buffer unit 100 stores all of the applied R / G / B image data, and then outputs data consistently with the output timing according to the control signal of the line buffer control unit 170.

4 is a timing diagram for writing and reading a horizontal sync signal. In general, the horizontal resolution of a video signal represents a horizontal direction and the vertical resolution represents how many lines can be displayed in a vertical direction. There are 525 scanning lines in the vertical direction, and about 480 lines of the 525 scanning lines are visible on the monitor. The horizontal resolution is a signal of 4.2 MHz in the effective screen portion 52.7 Hz (= 63.5 Hz x 0.83) of one scan line 63.5 Hz (= 1 / 15.734 Hz), which is 221 (= 52.7 Hz x 4.2 MHz) cycles. In television, black and white must be counted as one line, which is doubled to 442 lines. Thus, as shown in Fig. 4, the line buffer unit 100 is effective in the recording section 100b of the H sync signal. It is only necessary to record the data 100a, and the next reading section 100c reads out the recorded data.

FIG. 5 is a block diagram of a line buffer control unit including a recording unit, a reading unit, and a vertical position selecting unit for controlling the line buffer unit shown in the interface device of the DRAM according to the present invention. FIG. 6A is a write cycle, and FIG. 6B is a read cycle. Represent a timing diagram for. In addition, the line buffer unit 100 illustrated in FIG. 3 has a first input first output method, and a data input port and an output port are separated from each other and simultaneously perform a write operation and a read operation. Therefore, it is easy to control the data, and operates separately from recording and reading, so there is an advantage of not setting a high impedance section. Referring to FIGS. 5 and 6, the recording unit 170A of the line buffer control unit 170 corresponds to a write clock, a horizontal sync signal H sync, and data valid. The signal is input. The recording unit 170A first outputs a write reset signal through the second output port 171 to initialize the line buffer unit 100 by the input signal. After a write enable signal is applied through the third output port 173, a write clock (write clk) is applied through the first output port 171. Therefore, the data corresponding to the image information is recorded to the line buffer unit 100 by the control signal applied from the recording unit 170A of the line buffer control unit 170. In addition, the reading unit 170B of the line buffer control unit 170 reads through the second output port 175 of the reading unit 170B by inputting a read clk and a horizontal synchronization signal H sync (⒣). Initialize by applying a reset signal to the line buffer unit 100, and after applying a read enable signal through the third output port 176, the first output port 174 is Through the read clock (read clk) is output to the line buffer unit 100. The reading unit 170B is a vertical position set from the vertical position selection unit 180 to which the horizontal sync signal H sync, the vertical sync signal V sync, and the data valid signal are applied. Valid data corresponding to the above can be recorded and read.

That is, referring to the recording cycle of FIG. 6A, a write reset signal is applied to the line buffer unit 100 in the valid data existing in the horizontal synchronization period H sync. When the write enable signal is applied and a write enable signal is applied, data valid data can be written by the write clock. There are 853 clock cycles in the 853x480 mode and 640 clock cycles in the 640x480 mode in the data valid interval.

The data recorded in the line buffer unit 100 through the above process is read by the control signal of the reading unit 170B. According to the reading cycle of FIG. 6B, the data is written in the vertical synchronization signal V sync: There is valid data (data valid) corresponding to 480H, and the horizontal sync signal (H sync) is generated in the high section of valid data existing in the vertical sync signal (V sync :). Control to go low. Also, when the horizontal sync signal H sync goes low, a pulse for setting the vertical position V position goes high. Data in the horizontal sync signal (H sync :) in which the vertical position (V position:) is set is read when the read enable signal is applied. Therefore, the line buffer controller 170 records valid data of 640/853 corresponding to 1H in the line buffer unit 100, and reads the recorded data by the line buffer controller 170.

As can be seen from the above description, it relates to the control of the line buffer included in the interface device of the DRAM that stores and reads the line data of the PDP television. In particular, the line buffer unit of the First In First Out method is a recording unit. Data is easily controlled by receiving a control signal from a line buffer control unit provided with a read unit and a vertical position selector to record valid data for one line, and read the valid data for one line to interface data with a DRAM. In addition, since the effective data for one line is recorded and read, the memory size can be reduced.

Claims (3)

In a PDP television system for gray-scale display of digital image data from the memory unit 120 using an interface device, It receives NTSC composite video signal transmitted from broadcasting station, separates analog R / G / B and horizontal and vertical sync signal, and APL (Average Picture Level) corresponding to average value of brightness signal is from ADC (Analot to Digital Convertor) A line buffer unit 100 for temporarily storing data of one line of digitalized R / G / B color signals; A parallel input serial output (PISO) unit 110 for rearranging data in series since the R / G / B signals applied from the line buffer unit 100 are applied in parallel; A memory unit 120 for storing R / G / B data output from the PISO unit 110; A data selector 130 reading and outputting corresponding data from the memory unit 120 according to an address applied from the DRAM address generator 150; A PDP (140) for displaying the R / G / B data output from the data selector (130); A line buffer controller 170 for controlling the line buffer unit 100; A load clock and shift pulse generator 160 generating load clocks and shift pulses necessary for loading data of the PISO unit 110 and shifting them to the memory unit 120; A DRAM address generator 150 applying a read clock to the line buffer control unit 170 and providing an address required by the memory unit 120; Line buffer control in a dynamic RAM interface device of a PDTV, comprising a vertical position selector 180 for applying a vertical position pulse to a line buffer controller 170 by inputting the horizontal synchronization signal and valid data. Device. The line buffer control of the dynamic RAM interface apparatus of PDTV according to claim 1, wherein the line buffer unit 100 has a first in first out method having an input port and an output port. Device. 2. The write buffer of claim 1, wherein the line buffer control unit 170 receives a write clock, a horizontal sync signal, and valid data as inputs to the first output port 171. clk), a recording unit 130 for outputting a write reset signal to the second output port 172 and a write enable signal to the third output port 173; Read clk to the first output port 174, read reset to the second output port 175, and read third, using the read clk and the horizontal sync signal H sync as input. A read unit 170B for outputting a read enable signal to the output port 176; Characterized in that the vertical position selection unit 180 for applying the vertical position pulse to the reading unit 170B by inputting the horizontal synchronization signal (H sync), vertical synchronization signal (V sync) and data valid Line buffer controller in dynamic RAM interface of PDTV television