JP3401334B2 - Image signal input / output device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image input / output which, when recording or reproducing an image signal on a recording medium such as a magnetic disk, temporarily stores the image signal in a memory and then outputs it by adding a blanking period. Regarding the device.

[0002]

2. Description of the Related Art In a still video device, when an image signal is recorded on a recording medium such as a magnetic disk or when the image signal recorded on the recording medium is reproduced, the image signal is once A / D converted and stored in a memory. It is stored, read from the memory, D / A converted, and recorded or reproduced.
The memory does not store the horizontal and vertical blanking periods. When reading from the memory, the horizontal and vertical blanking periods are added to the image signal to set the pedestal level.

FIG. 5 shows a conventional example of a circuit for setting a pedestal level by adding horizontal and vertical blanking periods to an image signal input from an image sensor or the like. In this figure, the input image signal is converted into digital data by the A / D converter 11 and stored in the memory 12. This image signal is read from the memory 12, then input to the D / A converter 14 via the AND circuit 13, converted into an analog signal, and recorded on a recording medium. The AND circuit 13 is provided to add a blanking period to the image signal to set the pedestal level. That is, during the blanking period, the output signal from the memory 12 is D / A converted by the operation of the AND circuit 13. Formed by blocking transfer to the container 14.

[0004]

As described above, since the conventional image signal input / output device is provided with the AND circuit 13 for forming the blanking period, it has a large and complicated structure. The AND circuit 13 has been a cause of hindering downsizing of the still video device. SUMMARY OF THE INVENTION It is an object of the present invention to provide a small and simple image signal input / output device that does not require a special circuit to set horizontal and vertical blanking periods and set a pedestal level. There is.

[0005]

An image signal input / output apparatus according to claim 1 is connected to a memory for storing digital image signals and a D / A converter, and has a plurality of signal lines. /> Pull-up connected to a predetermined signal line of the memory data bus.
And up resistor, and means for controlling the output of the image signal by the data bus, the control means blanking period is formed by stops the output of the image signal, and from the data bus during the formation of the blanking period The specified signal line is pedestal level so that the pedestal level is output.
It is characterized in that it corresponds to the bit indicating the digital value of . The image signal input / output device according to claim 4.
Is a memory for storing digital image signals and a D / A converter.
Data with multiple signal lines of memory connected to the converter
Image with data bus and resistors connected to each of the buses
And a means for controlling the output of the signal.
The blanking period is set by stopping the output of the signal.
And the resistor includes a pull-up resistor.
Data bus to pedestal level during formation of the King period
Signal line corresponds to pull-up resistor so that
Is grounded via a pull-down resistor except for the signal line
It is characterized by being.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to illustrated embodiments. FIG. 1 is a block diagram of an image signal input / output device which is an embodiment of the present invention.

The system control circuit 20 is a microcomputer, and processes the entire image signal input / output device. An operation unit 21 is connected to the system control circuit 20. By operating the operation unit 21, processing such as recording of an image signal is executed.

A luminance signal (Y + S) and a color difference signal (RY, BY) generated according to, for example, the NTSC system.
Is input via an external input / output terminal (not shown). The luminance signal (Y + S) is separated from the A / D converter 23 by a sync signal.
It is input to the clock generation circuit 22. Luminance signal (Y +
S) is converted into a digital signal by the A / D converter 23 and output to the Y memory 26 and the D / A converter 31. The color difference signal (RY) is input to the A / D converter 24, converted into a digital signal, and converted into the R memory 27 and the D / A converter 32.
Is output to. The color difference signal (BY) is sent to the A / D converter 25.
Is input to the B memory 28 and the D / A converter 33.

The synchronizing signal separating / clock generating circuit 22 separates the synchronizing signal from the luminance signal (Y + S), and the clock signal f _S1 and the blanking signal /
BLK4 is generated and output to the memory control circuit 29 and the system control circuit 20. The memory control circuit 29 receives the clock signal CL based on the clock signal f _S1 and the blanking signal / BLK4.
K and the address signal ADDR are generated. Clock signal C
LK is the A / D converter 23, 24, 25 and the memory 2
6, 27, and 28, which controls A / D conversion and data write timing to the memory.
The address signal ADDR is input to the Y memory 26, the R memory 27, and the B memory 28, and thereby the write address of the memory is controlled. Further, blanking / BLK1 is generated based on the blanking signal / BLK4.

The luminance signal and the color difference signal stored in the Y memory 26, the R memory 27 and the B memory 28 are read out from these memories, and the D / A converters 31, 32, 3 are read out.
It is converted into an analog signal by 3. As will be described later, the luminance signal and the color difference signal are stored in the memories 26, 27, and 2.
In the operation of reading from 8 and inputting to the D / A converters 31, 32 and 33, a blanking period is formed between the horizontal scanning lines. The memory control circuit 29 controls the read operation and the D / A conversion of the luminance signal and the color difference signal from each memory.

The luminance signal read from the Y memory 26 is converted into an analog signal in the D / A converter 31 and input to the adder 39. The brightness signal input to the adder 39 is added with the sync signal / SYNC (“/” represents a negative logic signal) generated in the sync signal generation circuit 34, and a magnetic disk recording device or a display device not shown. Etc. are output. The color difference signal read from the R memory 27 is converted into an analog signal in the D / A converter 32 and output to a magnetic disk recording device or the like. Similarly, the color difference signal read from the B memory 28 is also converted into an analog signal in the D / A converter 33 and output to a magnetic disk recording device or the like.

The synchronizing signal generating circuit 34 includes a synchronizing signal / SY.
In addition to NC, it generates a blanking signal / BLK2 and a clock signal f _S2 . The blanking signal / BLK2 and the clock signal f _S2 are input to the memory control circuit 29. In the memory control circuit 29, based on the blanking signal / BLK2, the blanking signal / BLK3
Is generated. The blanking signal / BLK1 and the blanking signal / BLK3 are respectively A / D converters 23, 2
Output enable terminals 4 and 25 and memories 26 and 27,
28 is input to each output enable terminal. In the memory control circuit 29, the clock signal CLK and the address signal ADDR are generated based on the clock signal f _S2 . The address signal ADDR is stored in the memories 26, 27, 28.
, Which controls the read address of the memory. The clock signal CLK is sent to the D / A converter 31,
32 and 33, and the timing of D / A conversion is controlled by this.

FIG. 2 is a diagram showing a logic circuit for generating blanking signals / BLK1 and / BLK3 in memory control circuit 29. As shown in this figure, the logical sum of the blanking signal / BLK2 (negative logic signal) input from the synchronization signal generation circuit 34 and the memory / write / read switching signal input from the system control circuit 20 is the AND circuit. An AND circuit 66 obtains the logical sum of the blanking signal / BLK4 (negative logic signal) input from the sync separation circuit 22 and the memory / write / read signal. The memory / write / read switching signal indicates a data write command to the memory when it is at a low level, and indicates a memory data read command when at a high level. The output of the AND circuit 66 is the blanking signal /
BLK1 is input to the A / D converters 23, 24, 25, and the output of the AND circuit 36 is the blanking signal / BLK.
3 is input to the memories 26, 27 and 28.

Referring again to FIG. 1, the Y memory 26, R
Terminators 41, 42 and 43 are connected to the memory 27 and the B memory 28, respectively. These terminators 41, 42, 43 are used for the memory 2 as described later.
It is provided to set the pedestal level when the horizontal and vertical blanking periods are added to the image signals output from 6, 27 and 28.

FIG. 3 shows the configuration of the terminator 41 connected to the Y memory 26. As shown in this figure,
The data buses of the memory 26 and the A / D converter 23 each include 8-bit signal lines, and these signal lines are D
It is connected to the input terminal of the / A converter 31. Each signal line of the memory 26 is connected to the corresponding signal line of the A / D converter 23.

In the data bus of the Y memory 26, the signal line D4 of the fifth bit from the lower order is connected to the power supply Vcc via the pull-up resistor RA, and the other signal lines are grounded via the pull-down resistor RD. In addition, A / D converter 2
Each signal line 3 is also grounded via the pull-down resistor RD. The values of the pull-up resistor RA and the pull-down resistor RD need to have such a value that the image signal is not disturbed when the image signal (luminance signal) is output from the memory 26. For example, 100K
Ω and the pull-down resistance RD are, for example, 10 KΩ.

At the output enable terminal of the Y memory 26,
Blanking signal / B from memory control circuit 29
LK3 is input. When the blanking signal / BLK3 is at high level, the image signal stored in the Y memory 26 is read, and when it is at low level, the output terminal of the Y memory 26 is set to high impedance. On the other hand, the blanking signal / BLK1 is input from the memory control circuit 29 to the output enable terminal of the A / D converter 23. When the blanking signal / BLK1 is high level,
When the image signal is A / D converted by the A / D converter 23 and has a low level, the output terminal of the A / D converter 23 is set to high impedance.

Therefore, the blanking signal / BLK1
When both the blanking signal / BLK3 and the blanking signal / BLK3 are at a low level, all output terminals of the Y memory 26 and the A / D converter 23 have high impedance except for the signal line D4 of the fifth bit from the lower order of the Y memory 26. Also, since it is grounded via the resistor RD, only the signal line D4 becomes "H", and 16/255 data is input to the D / A converter 31. This data is defined in Rec-601 Recommendation of CCIR (International Radio Advisory Committee),
This is the pedestal level when the luminance signal is quantized with 8 bits. That is, the signal line D4 provided with the pull-up resistor RA has a binary digital value 1 of the pedestal level.
Corresponds to the bit indicating.

Terminator 4 connected to the R memory 27
2 and the terminator 43 connected to the B memory 28
Also has the same configuration as the terminator 41, except that the pull-up resistor is connected to the signal line D7 of the most significant bit instead of the signal line of the fifth bit from the lower order.

Next, the operation of the apparatus of this embodiment will be described. In the sync signal separation / clock generation circuit 22, the luminance signal (Y +
The sync signal included in S) is separated, and the clock signal f _S1 whose phase matches that of the sync signal is generated. The clock signal f _S1 is input to the memory control circuit 29, which generates the clock signal CLK and the address signal ADDR.
The clock signal CLK is input to the A / D converters 23, 24, 25 and the memories 26, 27, 28, and in the A / D converters 23, 24, 25, a luminance signal and a color difference signal (R- Y, BY) are converted into digital signals. When the signals are stored in the memories 26, 27 and 28, the memory / memory
Since the write / read switching signal is input as a low level (L) (that is, a write command), the blanking signal / BLK1 becomes high level during the effective period of the input video signal in synchronization with / BLK4, and the blanking signal / BLK4 BLK3 always keeps low level. These luminance signal and color difference signal are respectively sent to the Y memory 26 and the R memory 27.
And the address signal ADDR input to the B memory 28.
Is stored at a predetermined address in accordance with.

When the storage of the image signal for one frame or one field in the Y memory 26, the R memory 27 and the B memory 28 is completed, a signal indicating the completion of this operation is sent from the memory control circuit 29 to the system control circuit 2.
It is output to 0. In response to this, the system control circuit 20 outputs a command for reading the image signal from each of the memories 26, 27 and 28, that is, a memory / memory command to record the image signal stored in each memory on, for example, a magnetic disk.
The read / write switching signal is output to the memory control circuit 29 as a high level (H).

In response to this command, the memory control circuit 29 sets the blanking signal / BLK1 to the low level and sets the blanking signal / BLK3 to the high level, and in synchronization with the clock signal f _S2 , the address signal ADDR and the clock signal. Generates signal CLK and outputs each memory 2
6, 27 and 28 and D / A converters 31, 32 and 33, respectively. As a result, one horizontal scanning line forming the image signal is read from the memories 26, 27 and 28, and D
The signals are converted into analog signals in the / A converters 31, 32, 33 and output to a magnetic disk or the like.

When the output of the horizontal scanning line is completed, that is, when the blanking period starts, the blanking signal / BLK is output.
Since 2 becomes low level (L), the memory control circuit 29 sets the blanking signal / BLK3 to low level. As a result, a pedestal level signal is generated on the data bus of each memory 26, 27, 28, and the D / A
It is output to the converters 31, 32 and 33. This pedestal level signal is converted into an analog signal in the D / A converters 31, 32 and 33 and output to a magnetic disk or the like.

When the blanking period ends, the memory control circuit 29 again causes the blanking signal / BLK3.
Is set to a high level and the address signal ADDR
And a clock signal CLK are generated, and each memory 26, 27,
28 and D / A converters 31, 32 and 33 respectively. As a result, the next horizontal scanning line is stored in the memories 26, 27, and 2.
It is read out from the memory 8, and converted into an analog signal in the D / A converters 31, 32 and 33 and output to a magnetic disk or the like.

By repeating such an operation, a horizontal or vertical blanking period is formed between the horizontal scanning lines, and an image signal of one field or one frame is recorded on the magnetic disk or the like.

FIG. 4 shows the luminance signal output from the D / A converter 31 and the synchronization signal / SYNC output from the synchronization signal generation circuit 34. As shown in this figure, the blanking period S1 coincides with the period in which the blanking signal / BLK3 is set to the low level. Further, during the blanking period S1, a signal indicating the state of the level of each bus, that is, the pedestal level is D / A converted in the D / A converter 31 (FIG. 1), and during the image valid period S2,
The data output from the Y memory 26 is D / A converted. In the blanking period S1, the synchronization signal / SYNC is added to the pedestal level signal.

As described above, according to the present embodiment, it is not necessary to provide a dedicated circuit for forming the pedestal level in the blanking period as in the conventional case, and therefore the circuit configuration of the image signal input / output device is further simplified. be able to.

The present invention can be used as a device for converting a signal format when recording an image signal such as an NTSC system, a PAL system or a high definition signal in a still video device for recording a still image. it can. Further, when displaying one frame of a still image on a display or the like in a video tape recorder or an optical disk device in which a moving image is recorded, the image signal read from the video tape or the like is stored in one frame memory and displayed on the display. It can be used in a device.

[0029]

As described above, according to the present invention, there is no need to provide a special circuit for setting the pedestal level by forming the horizontal and vertical blanking periods, and an image having a small and simple structure is provided. A signal input / output device is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image input / output device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a logic circuit for generating a blanking signal / BLK1 in a memory control circuit.

FIG. 3 is a diagram showing a configuration of a terminator connected to a Y memory.

FIG. 4 is a diagram showing a luminance signal output from a D / A converter and a synchronization signal output from a synchronization signal generation circuit.

FIG. 5 is a diagram showing an example of a conventional device for forming a Braking period.

[Explanation of symbols]

26 Y memory 27 R memory 28 B memory RA, RD resistance

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5 / 91,5 / 16

Claims (4)

(57) [Claims] 1. A memory for storing a digital image signal, and a pull-up connected to a D / A converter and connected to a predetermined signal line of a data bus of the memory having a plurality of signal lines.
A resistor and means for controlling the output of the image signal by the data bus, wherein the control means stops the output of the image signal to form a blanking period, and at the time of forming the blanking period. The predetermined signal line is connected to the pedestal so that a pedestal level is output from the data bus.
An image signal input / output device characterized in that it corresponds to a bit indicating a digital value of a level . 2. The image signal input / output device according to claim 1, wherein the resistance value has a size such that the image signal is not disturbed when the image signal is output from the memory. 3. The plurality of signals excluding the predetermined signal line
Note that the wire is grounded through a pulldown resistor.
The image signal input / output device according to claim 1, which is a characteristic. 4. A memory for storing a digital image signal.
And a signal connected to the D / A converter and having a plurality of signal lines.
A resistor connected to each of the memory data buses, and means for controlling the output of the image signal by the data bus.
And the control means stops the output of the image signal
When the blanking period is formed, the resistance is pulled
Including the up resistance, when forming the blanking period
Output pedestal level from the data bus
The signal line corresponds to the pull-up resistor
Via a pull-down resistor except that the ground is
Characteristic image signal input / output device.