JPS63170730A - Hard copying device - Google Patents

Abstract

PURPOSE:To efficiently perform a hard copy processing by providing a data buffer. CONSTITUTION:When copying is requested, a video signal switching circuit 2 is selected and the video signal from a request source CRT is A/D-converted by an A/D converter 3 and is stored in a preceding-stage frame memory 5. If the printing state is already set, data stored in the memory 5 is transferred to a magnetic disk file 6, but if it is not set, data is transferred to a succeeding- stage frame memory 7. That is, the magnetic disk file 6 is used as a data buffer when the succeeding-stage frame memory 7 is not empty and if there are unprinted files, they are successively transferred to the succeeding-stage frame memory 7 and are inputted to a printer 12 through a picture processing part 8 and are printed. Thus, the hard copy processing of pictures is efficiently and continuously performed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a hard copy device that digitally processes and prints a CRT display signal, that is, a video signal.

(Prior Art) Conventionally, there are hard copy devices that copy CRT images as they are, but with conventional devices, the display contents on the CRT cannot be changed while hard copy is being performed, and during this time, the system is restricted and the throughput is reduced. In particular, when a plurality of CRTs and one hard copy device are connected in a multiplex manner, the throughput is significantly reduced.

(Objective) It is an object of the present invention to solve the problems of the prior art described above and to provide a hard copy device that can efficiently and continuously perform hard copy processing of images.

(Structure) An object of the present invention is to solve the problems of the prior art described above and to provide a hard copy device that can efficiently and continuously perform hard copy processing of images.

(Structure) In order to achieve the above object, the present invention provides a CRT display device, a CRT display device for multi-value conversion of a video signal, an analog/digital converter for multi-value conversion of a video signal, and a CRT display device for multi-value conversion of a video signal. A pre-stage frame memory that receives and inputs the output of the analog/digital converter, a synchronous clock generation circuit that generates a sampling clock for the analog/digital converter and a write timing clock for the pre-stage frame memory from the synchronization signal, and a data transfer from the pre-stage frame memory. a magnetic disk file to be received, a subsequent frame memory that stores print data, a data bypass switch that directly transfers data from the preceding frame memory to the subsequent frame memory, and an image processing unit that generates printer print data from the subsequent frame memory. , a printer engine, a control circuit that controls each part, and an operation section that interfaces with an operator.

Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

FIG. 1 is a block diagram showing the entire embodiment of the present invention, FIGS. 2(a) and 2(b) are flowcharts, FIG. 3 is a block diagram showing the video signal switching circuit, and FIG. 4 is a block diagram showing the entire embodiment of the present invention. 5 is a perspective view showing the operation section; FIG. 6 is a diagram showing the correspondence between CR7 pixels and memory addresses; FIG. 7 is a block diagram showing the PLL circuit; FIG. The figure is a block diagram showing the internal circuit of the operating section.

In FIG. 1, la, lb, and lc are CRT display devices, which are driven by video signals 15a, 15b, and 15c. Further, the video signal is sent after converting the image data of the host system. Note that there is no particular restriction on the number of CRTs to be connected, and it is determined based on the efficiency and speed of the entire system.

Further, 2 is a video switching circuit for switching the signal selected for hard copying from among the video signals 15a, 15b, and 15c, and as will be described later, a general coaxial switch or a semiconductor analog switch is used. be done. 3 is an analog/digital (A
/D) converter, and 4 is an image memory section to be described later for storing the output 20 from the A/D converter 3.

The image memory unit 4 includes a pre-frame memory 5 having a storage capacity for one screen of a CRT, and the image data to be hard-copied is first stored in the 0-image memo 11 section 4 stored in the pre-frame memory 5. is provided with a magnetic disk file 6 and a subsequent frame memory 7, and the image data stored in the preceding frame memory 5 is transferred to the magnetic disk file 6. At this time, if the subsequent frame memory 7 is already empty, the image data in the previous frame memory 5 is directly transferred to the subsequent frame memory 7 via the data bypass switch 18. That is, the preceding frame memory 5 functions as a buffer memory,
The main function is to adjust the data speed between the magnetic disk file 6 and the CRT.

The magnetic disk file 6 includes a plurality of CRTla, l
This magnetic disk file 6 is necessary because the subsequent frame memory 7 is occupied during operation of the color printer and cannot be used for writing.

The output 25 of the subsequent frame memory 7 is transferred to the image processing section 8. The image processing section 8 is divided into three blocks: a scaling processing circuit 9, a color conversion circuit 10, and a gradation processing circuit 11. The color conversion circuit 10 is a circuit for converting a CRT video signal from an optical system (R, G, B) to an additive color system (Y, M, C), and performs gradation processing. The circuit 11 performs gradation processing for rendering on a color density printer.

Reference numeral 12 denotes a color printer, and various types of printers such as thermal transfer, inkjet, and laser printers are applicable. 13
14a is a control circuit for controlling each of the above-mentioned parts;
, 14b, and 14C are operation units provided one-to-one on each CRT, and as shown in FIG.
usy lamp 31. 26 is a synchronous clock generation circuit which generates a sampling clock for the A/D converter 3 and a write timing clock 28 for the front frame memory 5 from a synchronous signal 27 from the CRT.

Next, the operation of this embodiment described above is explained in Figs. 2(a) and 2(a).
This will be explained based on the flowchart of b). First, CR
7 Screen data is imported when the copy start button 30 of the operation unit 14 is pressed and a copy request is made (2-1).
, take in the video signal from the requesting CRT (2-2)
, turns on the Busy lamp 31 of the operation unit 14 of the requesting CRT (2-3), and selects the video signal switching circuit 2 as the requesting CRT NO (2-4). and requester C
A/D converter 3 converts the video signal from RT into A/D
The data is converted (2-5) and then stored in the previous frame memory 5 (2-6). The above-mentioned Busy lamp 31 is turned on to prevent the CRT screen from being up-dated, since the hard copy of the screen cannot be performed properly if the CRT screen is up-dated. If printing is already in progress (2-7), the data stored in the preceding frame memory 5 is transferred to the magnetic disk file 6 (2-8), and if printing is not in progress (2-7) 7) and transferred to the subsequent frame memory 7 (2-9).

The magnetic disk file 6 is stored in a subsequent frame memory 7.
Used for data buffer when is not empty. The magnetic disk file 6 is required to shorten the time taken to capture data on the CRT screen and the time required for the host system to be tied down, and a device with a high data transfer speed, such as a hard disk device, is also required. After the data in the front frame memory 5 has been transferred, there is no longer a need to constrain the system, so the Busy lamp 31 of the operation section 14 of the requesting CRT is turned off (2-10).
)', (2-11).

If there is an unprinted file in the magnetic disk file 6 (2-12), the data in the magnetic disk file 6 is sequentially transferred to the subsequent frame memory 7 (2-13).
This image data is transferred to the image processing unit 8 for printing (2-14), and after undergoing scaling processing, color conversion, and gradation processing, enters the printer 12, where printing is started (2-15).
.

Note that during printing, it is necessary to respond to a hard copy request for images CRTI a, 1 b, lc, so after sending a print start (2-15) to the printer 12, the routine for checking a copy request is returned.

The processing routine after the copying is completed is executed by interwoven processing from the printer 12, as shown in FIG. 2(b). However, this processing is not necessarily an interwoven process (or it may be inserted into the main loop).

Next, specific examples of each part in this embodiment will be explained. First, the second part of the video signal switching circuit is shown in FIG. In the same figure, the part surrounded by the broken line is the video signal switching circuit 2.
and an analog switch 32 for R-G-B video signals.
and a relay driver 3 that operates this switch 32.
3 and AND gates 23 and 24 for synchronizing signals.

The analog switch 32 includes one CRT 1a, l
Three, R, G, and B are provided for b and lc.

However, in this example, an RGB separation type CRT is shown, but if a composite type such as NTSC is used, the analog switch is one CRT.
Only one selector is required for each RT, and a selector for synchronization signals is not required.

The AND gate 23.24 is the OR gate 34°35.
In combination with , they constitute selectors for horizontal synchronization (CHsync) and vertical synchronization (Vsync), respectively.

The selection signal 22 from the control circuitry 3 determines which one is selected from the connected CRTIs a, 1b, and 1c. These selected signals, that is, R, G, and B video signals, are each input to the A/D converter 3, converted into multivalued digital signals, and input as data to the previous frame memory 5. In addition, the horizontal and vertical synchronization signals are input to the synchronization clock generation circuit 26, and the sampling clocks to the A/D converter 3,
It serves as the source of the write timing clock for the previous stage frame memory 5.

Next, FIG. 4 shows a specific example of the image memory section 4 and its surroundings. In the figure, the front frame memo IJ 5 and the rear frame memory 7 are dual boat memories (Du
al-Port-MeIlory), the internal memory cells are the same, and there are two access systems. The input of the front frame memory 5 is the A/D converter 3.
output 19, the memory address is x on the CRT screen.
, are positioned corresponding to the y coordinates. That is, the sixth
As shown in the figure, the CRT sub-scanning direction -X direction and the CRT main scanning direction -X direction. Therefore, the address counters 36 and 37 are also composed of two counters, x and y, and the X address is incremented with the sampling clock of each dot, and the X address is incremented in horizontal synchronization.

Note that the sampling clock is generated by the synchronous clock generation circuit 26.
is generated by the PLL circuit or crystal oscillator shown in FIG. The PLL circuit shown in Fig. 7 uses phase comparison (
PhaseCornparato: P C) 3rd,
Low-pass filter (L, oiyPasFiLer
: LPF) 39, voltage controlled oscillator (Voltage
Controlled: V
CO) 40, N-divider
It consists of 41. However, N of the N frequency divider 41 is the total number of pixels in the horizontal direction of the CRT.

The DMA controller 42 determines whether the data in the preceding frame memory 5 is to be transferred to the magnetic disk file 6 or the subsequent frame memory 7. However, if the data transfer speed of the MPU 43 is fast, the DMA controller 42 is not necessary.

Main control of each of the above-mentioned parts is performed via a bus 13a within the control circuit 13.

The MPU 43 has I10 ports 44 and 45 for controlling the operating units 14a, 14b, and 14C, and for controlling the color printer engine 12, respectively. Operation unit 1
4a, 14b, and 14c are shown in FIG.
and a busy signal 47 indicating that CRT screen data is being taken in are input to the 110 hoard 44.

In Figure 8, hard copy copy start button 3
Inverters 48 and 49 are connected to the 0 and Busy lamps 31, respectively, and the on signal of the copy start button 3 degrees is
The hard copy request signal 46 and the busy signal 47 are transmitted through the flip-flop 50, and the busy lamp 31 is turned on.

Each of the operating units 14a, 14b, and 14c may be installed near the CRT, integrated with the CRT, or remotely controlled, but in any case, when the operator desires a hard copy, the copy start button 30 is pressed. Press , confirm that the Busy lamp 31 goes out, and then update the CRT screen (Up-Date).
).

Therefore, it is possible to monitor in real time whether the system is tied up because the operator is in the process of hard copying.

In this embodiment, when a plurality of CRT display devices are used and one color hard copy device is shared, the system becomes extremely efficient in use.
Even with a T display device, when performing continuous screen copying,
This is effective because it eliminates the need to wait in line.

(Effects) As explained above, the present invention has a data buffer and can move on to the next process without waiting for the end of printing.
When continuous screen printing is performed using one display device, it is possible to provide a hard copy device that can perform efficient hard copy processing, such as eliminating the need to wait for a turn.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and FIG. 1 is a block diagram showing the whole, FIG. Figure 4 is a block diagram of the image memory section, Figure 5 is a perspective view of the operation unit, Figure 6 is a diagram showing the correspondence between CR7 pixels and memory addresses, and Figure 7 is a block diagram of the PLL circuit. , FIG. 8 is a block diagram of the internal circuit of the operating section. 1 a, 1 b, IC/CRT display device, 3... analog/digital converter, 5... front stage frame memory, 6... magnetic disk file, 7... rear stage frame memory, 8... Image processing unit, 12... Printer engine, 13-... Control circuit, 14.14a, 14
b. 13C...Operation unit, 1st...Data bypass switch, 26...Synchronized clock generation circuit. Prisoner 5, Figure 6, Figure 71! l Section 8 1°4a (14b, 14c)

Claims (1)

[Claims] A CRT display device, an analog/digital converter for multi-value conversion of a video signal, a pre-frame memory that receives and inputs the output of this analog/digital converter, and a synchronization signal that converts the sampling clock of the analog/digital converter and the pre-stage frame. A synchronous clock generation circuit that generates a memory write timing clock, a magnetic disk file that receives data transfer from the previous frame memory, a subsequent frame memory that stores print data, and directly transfers data from the previous frame memory to the subsequent frame memory. The printer is characterized by comprising a data bypass switch, an image processing section that generates printer print data from the subsequent frame memory, a printer engine, a control circuit that controls each section, and an operation section that interfaces with an operator. hard copy device.