JPH088941A - Single direction loop transmission circuit - Google Patents

Abstract

PURPOSE:To allow a circuit to conduct reception and rewrite transfer of communication data in real time. CONSTITUTION:An idle signal (a) outputted from a FIFO memory 6 is inverted by an inverter 10 in a station 1 receiving communication data to obtain a reception interrupt signal (e), which is given to a processor 11 to start reception interruption. Furthermore, a weight control signal (c) generates the idle signal (a) to input it to the processor 11 thereby adjusting a reception data access timing. On the other hand, when a head part of communication data is read by the processor 11 in the reception interrupt program, the scheduling of data processing is decided based on the length of data written in control head data of the head part to start processing of the communication data. When communication data in a FIFO memory 6 are addressed to both own and other stations, the communication data are received in the processor 11 and outputted to a transmission line 4 while being rewritten in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a unidirectional loop type transmission circuit used in a distributed control system for general industry.

[0002]

2. Description of the Related Art Communication data to be input and output is stored in a FIFO (f
The conventional unidirectional loop type transmission circuit that temporarily stores the data in the first-in first-out memory and adjusts the read / write timing of data by the processor is
In order to manage the boundary of continuously input communication data, there is a system in which a part of the bit width of communication data is assigned to a control bit (or control code) and this control bit is constantly monitored. . In another method, a dedicated control line is laid on the transmission line, a data number counter is provided by dedicated hardware, and the boundary of communication data in the FIFO memory is stored and managed.

[0003]

However, in the former case, since the FIFO memory monitoring process by the processor at the time of reception and transmission of communication data is complicated, reception and transmission must be processed at different timings. I won't.
In the latter case, the circuit configuration is complicated and the processor needs to perform polling control by a hardware line. Therefore, the reception processing of the processor is limited in timing, and data is transmitted and received at the same time. It was difficult to carry out complex processing such as. Therefore, if it is necessary to rewrite some of the communication data addressed to another station when it receives the communication data addressed to the other station and is sent to the other station, the processor fetches the communication data once and There is a problem in that the transmission rate is lowered due to the procedure of transmitting after rewriting in the processing cycle. The present invention has been made to solve the above problems, and an object of the present invention is to receive communication data addressed to another station as well as to the own station, and partially rewrite the communication data addressed to the other station. It is an object of the present invention to provide a unidirectional loop type transmission circuit capable of simultaneously processing reception and transmission when it is necessary to transmit from a device.

[0004]

In order to achieve the above object, the present invention is a FIFO for temporarily storing communication data input / output via a transmission line in a station installed on the transmission line.
Unidirectional loop transmission circuit having a memory and a processor connected to the FIFO memory via a bus, and performing transmission / reception and bypass transmission of communication data to / from another station connected via a transmission path. In the above, means for adding the data length of the communication data to the head portion of the communication data originated from its own station, and a reception interrupt signal output circuit for outputting a start signal of the reception interrupt to the processor based on an empty signal output from the FIFO memory, A wait control signal output circuit that outputs a wait control signal to the processor based on an empty signal output from the FIFO memory, and a processor reads the head portion of communication data in the FIFO memory, and schedules data processing based on the data length of the head portion. Means for starting the processing of communication data and the communication data in the FIFO memory. Wherein the communication data in the FIFO memory and means for outputting to the transmission path rewriting in parallel with taking the processor if it is addressed to both stations.

[0005]

According to the present invention, the data length of the communication data is added to the head portion of the communication data originated from the own station, and the station receiving the communication data receives the reception interrupt based on the empty signal output from the FIFO memory. A reception interrupt signal is output from the signal output circuit to the processor. Similarly, a wait control signal is output from the wait control signal output circuit to the processor based on the empty signal output from the FIFO memory. Thereby, even if the processing speed of the processor is higher than the transmission speed of the communication data, the communication data is smoothly received by the processor. Next, the data length of the head portion of the received communication data is read by the processor, the scheduling of data processing is determined, and the processing of communication data is started. Here, when the communication data in the FIFO memory is addressed to both the own station and the other station, the communication data in the FIFO memory is rewritten in parallel with being taken into the processor and then output to the transmission path.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, 1 is a station, 2 and 3 are other stations than the station 1, and these stations 1 to 3 are transmission lines 4 composed of optical cables or the like.
Are connected in a loop. Communication data is transmitted in the clockwise direction on the transmission path 4. The drawing shows that the communication data transmitted by the other station 2 is received by the station 1, and the communication data transmitted by the station 1 is received by the other station 3. The station 1 includes an input buffer circuit 5, a FIFO memory 6, a bus 7, an output buffer circuit 8, a switch 9 and an inverter 1.
0, a processor 11, an AND circuit 12, and a timer 13. The switch 9 and the inverter 10 constitute a reception interrupt signal output circuit, and the switch 9, the AND circuit 12 and the timer 13 constitute a wait control signal output circuit.

FIG. 2 shows the format of communication data generated and transmitted by the stations 1 to 3, the communication data 30 is divided into three parts, and the control head data 31 is added to the head portion of the head of the transmission data body 32. , Diagnostic tail data 33 is added to the end. In this control head data 31, the data length of the communication data 30 is written as the number of times of reading (word number) of the processor 11, and the boundary of the communication data 30 is managed by this number of times of reading.

When the communication data 30 thus constructed is transmitted from the other station 2 in FIG. 1 and received by the station 1, first,
It is input to the FIFO memory 6 via the input buffer circuit 5. Then, the FIFO memory "empty" signal a that has been output from the FIFO memory 6 is inverted from 1 to 0. The signal a is inverted via the switch 9 and the inverter 10 and input to the reception interrupt terminal of the processor 11 as the reception interrupt signal e. As a result, the reception interrupt of the processor 11 is activated to start fetching data from the FIFO memory 6, and outputs the signal b to switch the switch 9. Then, the signal a is the AND circuit 12
And is input to the timer 13.

In this way, when the processor 11 starts the reception interrupt, the control head data 31 of the communication data 30 input to the FIFO memory 6 is read by the processor 11 via the bus 7. Based on the number of times the control head data 31 is read, the processor 11 determines the scheduling for reading the communication data 30 and rewriting transfer, and starts access. Here, if the processing speed of the processor 11 is higher than the input speed of the communication data 30 to the FIFO memory 6, the data in the FIFO memory 6 temporarily disappears even during the input of the communication data 30.
The signal a may be inverted from 0 to 1.

In this case, the wait control signal c output from the AND circuit 12 becomes 1 and the W of the processor 11 becomes W.
The FIFO memory access is waited until it is input to the AIT terminal and the communication data 30 is input to the FIFO memory 6. When the next communication data is input to the FIFO memory 6, the signals a and c become 0, the wait is released and the access is restarted.

If the communication data 30 during transmission is interrupted due to a failure of the transmission path 4 or the like during this wait, the standby time exceeds the set time of the timer 13. As a result, the timer 13 outputs the time-over signal d to interrupt the wait control signal c, and the time-over signal d is input to the abnormal processing interrupt terminal of the processor 11 to start the abnormal processing interrupt. In this way, when an abnormality such as an interruption occurs in the received communication data, the weight control based on the FIFO memory "empty" signal a allows the abnormality to be easily detected.

FIG. 3 is an explanatory view showing a process of sequentially reading the communication data 30 from the FIFO memory 6. F
The reception interrupt is activated at the timing when the IFO memory "empty" signal a is inverted from 1 to 0, and the head portion of the communication data is first read. In the figure, since the data size of the first received communication data is N1, the transmission data is N
While accessing once, the WAIT control is in progress. Upon completion of N1 accesses, the next reception interrupt waits. Here, the next communication data is the FIFO memory 6
When the data is input to, the reception interrupt is activated again and the head of the communication data is read, and the data size N
Based on 2, the data access is similarly started. Similarly thereafter, the reception interrupt is activated in response to the input of the communication data.

As described above, in the embodiment, when the communication data 30 is input to the FIFO memory 6, the data size of the head portion is first read, and the scheduling of data processing is decided based on the data size. As a result, the boundary of the communication data 30 can be managed by software without using a special control circuit. At the same time, operation control between the FIFO memory 6 and the processor 11 is performed by a dedicated circuit based on the FIFO memory "empty" signal a.

As a result, there is no restriction on the program of the FIFO memory 6 of the processor 11, and the processor 11 reads and rewrites the communication data 30 from the FIFO memory 6 in real time and then transfers it to another station. It will be possible. Although the station 1 has been described in the embodiment, the other stations 2 and 3 have the same configuration as the station 1.

[0015]

As described above, according to the present invention, the data length of the communication data is added to the head portion of the communication data originating from the own station, and the reception interrupt signal output circuit and the wait control signal output circuit are provided. Controls the data reception process of the processor. As a result, when communication data addressed to both the own station and other stations is received, it is possible to rewrite the communication data for transmission in real time and output it to the transmission path in parallel with the communication data being taken into the processor. Become.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a format of communication data transmitted in the embodiment.

FIG. 3 is an explanatory diagram showing a process of reading communication data from a FIFO memory.

[Explanation of symbols]

 1 station 2 3 other station 4 transmission line 5 input buffer circuit 6 FIFO memory 7 bus 8 output buffer circuit 9 switch 10 inverter 11 processor 12 AND circuit 13 timer 30 communication data 32 transmission data body 31 control head data

Claims (1)

[Claims] 1. A station installed on a transmission path has a FIFO memory for temporarily storing communication data input / output through the transmission path, and a processor connected to the FIFO memory via a bus for transmission. In a unidirectional loop type transmission circuit that sends / receives communication data to / from another station connected via a path and bypass transmission, adds the data length of the communication data to the head part of the communication data originated from the own station. Means, a reception interrupt signal output circuit for outputting an activation signal of a reception interrupt to the processor based on an empty signal output from the FIFO memory, and a weight control for outputting a wait control signal to the processor based on the empty signal output from the FIFO memory The signal output circuit and the head portion of the communication data in the FIFO memory are read by the processor, and the data is read based on the data length of the head portion. A means for determining the scheduling of data processing and starting processing of communication data, and rewriting in parallel with fetching the communication data in the FIFO memory into the processor when the communication data in the FIFO memory is addressed to both the self and other stations. A unidirectional loop type transmission circuit characterized by comprising: