JPH0251760A - Data suppression control circuit - Google Patents

Abstract

PURPOSE:To shorten the data transfer time and to improve the data transfer efficiency by transmitting a data suppressing instruction based on the quantity of data transferred to a main memory from a data buffer. CONSTITUTION:In case a data buffer 102 of a channel device exceeds a prescribed level when the read data is transferred to the channel device from an input/output device 2, a suppressing instruction is given to the device 2 for transfer of the data. The channel device stores the data on the buffer 102 into a main memory. Thus the channel device releases the data suppressing state for a period of time required to transfer the data equivalent to the quantity of data stored in the main memory between the device 2 and the channel device. Then the device 2 sends data to the channel device just for a period of time during which the data suppressing state is kept released.

Description

[Detailed Description of the Invention] [Summary] Regarding a data suppression control circuit provided in a channel device in a data processing device, an object is to improve data transfer efficiency by effectively timing suppress data instructions during data transfer. In a channel device in a data processing device, a first register means for temporarily storing an amount of data transferred from a data buffer to a main memory device, a second register means for decrementing the amount of data, and a second register means for decrementing the amount of data; a detection means for detecting zero in the count of the second register means and outputting an on signal; and a detection means for detecting zero in the count of the second register means and outputting an on signal; and an AND gate for transmitting data, and is configured to control suppress instruction and cancellation of data transfer from the input/output device to the data buffer based on the amount of data stored in the main memory 1 from the data buffer.

[Industrial application field]

The present invention relates to a data suppression control circuit provided in a channel device in a data processing device, and more particularly to a data suppression control circuit that controls the amount of data transferred from an input/output device to a main storage device via a channel device.

[Conventional technology]

3rd rA is a diagram showing the configuration of a channel device and an input/output device in a general data processing device.

In the figure, 1 is a channel device, 2 is an input/output device, 3 is a main storage device, 11 is a data buffer, 12 is an optical ink face control circuit, 13 is a suppress signal circuit, 21 is an optical interface control circuit, and 22 is a data buffer. , 23 is a data suppress circuit, and 24 is an internal recording medium. Channel device 1 and input/output device 2 are coupled via optical fiber 4 .

In such a configuration, data transferred between each other is temporarily stored in each data buffer, and then transferred at the time of occurrence 1. Stored in the own device, etc. That is, data is read from the internal recording medium 24, stored in the data buffer 22, converted into an optical signal by the optical interface control circuit 21, and then optically transmitted by the optical interface control circuit I2 on the channel device side via the optical fiber 4. After the signal is converted into an electrical signal, it is stored in the data buffer 11 and then transferred to the main memory. In this case, since multiple channel devices cannot simultaneously transfer data to the main memory, data is temporarily stored in a data buffer until the data bus becomes free. When the suppress signal circuit 13 detects that data has accumulated in the data buffer, it sends a data suppress instruction (instruction to suppress data transfer) to the input/output device side via the optical interface control circuit, and stops the data transfer.

In general, when transmitting data between a channel device and an input/output device, connecting the channel device and the input/output device using an optical fiber can extend the transmission distance and improve the data transfer rate compared to an interface using a coaxial cable. It became possible. However, on the other hand, as the transmission distance increases, it takes time to send and receive signals between devices. Therefore, when data is transferred from an input/output device to a channel device, once the data buffer of the channel device is filled,
It has become necessary to send a data suppression instruction to the input/output device as soon as possible.

Also, when the data stored in the data buffer is transferred to the main memory and stored and the data buffer becomes free, the data suppression instruction is canceled, but it takes time for this cancellation instruction to reach the input/output device. . In such a case, the time during which data is suppressed becomes long, which causes a timing lag between data transfer and data suppression instruction, resulting in a decrease in the efficiency of data transfer.

FIG. 2 is an example of a conventional circuit. This circuit is a block diagram of the main parts inside the channel device, and shows a data buffer, peripheral registers, and a suppress signal circuit.

101 is an optical interface control circuit, 102 is a data buffer, 103 is an address register (MBA) for the data buffer when storing data in the main memory side, and 104 is an address register for storing data from the input/output device side into the data buffer. (IBA), 105 is a subtraction circuit (StlB), 1 (16
is a temporary holding register for sending data read from the data buffer 102 to the main memory.

In such a configuration, the optical fiber 4 is connected from the input/output device.
The data 111 is sent to the optical interface control circuit 10 via
1, the optical interface control circuit 101 converts the optical signal 111 into an electrical signal 112 and stores it in the data buffer 102. The address at which data is stored is specified by the register 104.

The register 104 is a counter that is incremented by 1 for each byte of data. Register 103 is a counter that specifies an address when storing data in the main memory, and is similarly incremented every byte. When, for example, 16 bytes of data are accumulated in the data buffer, the register 103 causes the data in the data buffer to be transferred to the main memory via the register 117. In this case, the register 103 will be incremented by +16, and when the data transfer to the main memory is stopped, data will accumulate in the data buffer. If the difference is zero, no data is accumulated, but if this difference becomes large and exceeds a certain amount, a suppress data instruction signal 116 is sent to the optical interface control circuit 101. The optical interface control circuit 101 converts the data suppression instruction signal 116 into an optical signal and sends it to the input/output device. When the input/output device receives this signal, it stops data transfer.

[Problem to be solved by the invention]

As explained above, the transmission distance between a channel device and an input/output device has expanded due to optical fiber technology, etc., but on the other hand, in data transfer suppression control, the channel device issues a data suppression instruction and then cancels it. In case,
The transmission of the release instruction will be delayed by the amount of time the distance has increased. For example, if the distance between the channel device and the input/output device is 1 to 2
km, the transmission speed of the data suppression signal is 5 n
At 5 ec/m, it takes 5 to 10 μSec. For this reason, there is a problem that the time for suppressing data becomes longer, and as a result, the time for data transfer becomes longer, resulting in a reduction in transmission efficiency.Therefore, it is necessary to shorten the time required for suppressing instructions.

[Means to solve the problem]

The present invention provides a channel device (1) provided in a data processing device.
, from the data buffer (102) to the main memory (
3) a first register means (RDB) for temporarily storing the amount of data transferred to the device; a second register means (SDC) for decrementing the data; and detecting zero in the count of the second register means. a detection means (DEC) for outputting an ON signal, and an AND gate (204) for determining a match between the ON signal of the detection means and the difference in the amount of data input and output in the data buffer and outputting a data suppression instruction signal. The present invention is characterized in that suppression instructions and cancellation of data transfer from the input/output device (2) to the data buffer are controlled based on the amount of data stored from the data buffer to the main memory.

[For production]

In such a configuration, when the data buffer 102 of the channel device exceeds a predetermined constant value when read data is transferred from the input/output device to the channel device, the input/output device is instructed to suppress data transfer. Here, the predetermined constant value is the data sent from the channel device instructing the input/output device to suppress data until the instruction reaches the input/output device and data transfer from the input/output device is stopped. The value is such that the data buffer of the channel device is not filled by l.

Then, when the channel device stores the data in the data buffer in the main memory, the data suppression is released for the time required to transfer the amount of data commensurate with the amount of data stored in the main memory to and from the input/output device. , the input/output device sends data to the channel device only during the time when data suppression is released.

As described above, the feature of the present invention is that a data suppression instruction is sent based on the amount of data transferred from the data buffer to the main memory. It's not something you do. By performing suppression control in this manner, the data suppression instruction can be canceled before the amount of data in the data buffer becomes equal to or less than a predetermined value. Furthermore, since only the amount of data stored in the main memory is sent out from the input/output device, overruns do not occur. Furthermore, when accesses to the main memory from the data buffer of the channel device are in contention, it takes longer to suppress the data when the amount of data stored in the data buffer is full. Since the time is shortened, data transfer efficiency can be improved.

〔Example〕

FIG. 1 is a block diagram of a main part of a channel device including a data subless control circuit according to an embodiment of the present invention. The data suppression control circuit 200 includes a read data counter 20
1, suppress data counter 202, and detection circuit 2
03 and 42 are formed by the AND gate 204.

The read data counter 201 is a counter that counts the number of bytes of data transferred to the main memory in one access, and is incremented by 1 when 1 byte data is set in the register 106. Therefore, the amount of data transferred from the data buffer to the main memory can be known from this counter value.

The suppress data counter 202 is a counter that decrements (-1) the value set by the output of the counter 201 until it becomes zero. That is, it is a counter that decrements the amount of data transferred to the main memory.

The cycle of -1 is the time required to transfer 1 byte to the input/output device. For example, if it takes 100 ns (IOMB/S) to transfer one byte between the input/output device, then the value is incremented by 1 every 100 ns.

The detection circuit 203 is a circuit that detects that the counter 202 is not zero. When the difference between register 103 and register 104 exceeds a certain value, the amount of data in the data buffer increases, that is, when the difference between register 103 and register 104 becomes large and exceeds a certain value, The output signal 216 of the subtraction circuit 105 is turned on and AN
Input to D gate.

Therefore, the detection port W! Output signal 213 of r203 is on"
If it is 1#, the suppress data instruction signal 215 from the AND gate 204 is turned on, this signal is inputted to the optical interface control circuit 101, and the suppress data is transmitted from the optical interface control circuit 101 to the input/output device via the optical fiber 4. Instructions are given.

In this state, when data is stored from the data buffer to the main memory, the value of counter 201 is set in counter 202. Then, the counter 202 decrements by -1 until the value of the counter 202 becomes zero. During the time until the value of the counter 202 becomes zero, the output signal 213 of the detection circuit 203 becomes off "0". Therefore, the suppress data instruction signal 215 from the AND gate 204 instructs cancellation of suppress data only while the output signal 213 is off. In this way, when data is stored from the data buffer to the main memory, suppressed data is released for a period of time commensurate with the amount of data.

〔Effect of the invention〕

As explained above, according to the present invention, when the data buffer of the channel device U is filled with a large amount of data due to competing accesses to the main memory, data suppression for the input/output device is performed. is performed efficiently, the data transfer time can be shortened, and data transfer efficiency is improved as a result.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a main part of a channel device including a data subless control circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a main part of a conventional channel device, and FIG. FIG. 2 is a block diagram of main parts of a channel device and an input/output device of a data processing device on a boat. (Explanation of symbols) 1... Channel device, 2... Input/output device, 3... Main storage device, 4... Optical fiber, If, 22.102... Data buffer, 12.2
DESCRIPTION OF SYMBOLS 1... Optical interface control circuit, 13... Suppress signal circuit, 23... Data suppress circuit 200... Data suppress control circuit 201, 202... Counter 203... To detection circuit 2 of the present invention Figure 2 is a block diagram of the main parts of a channel device including an embodiment of the data suppression control circuit.

Claims (1)

[Claims] 1. In a channel device in a data processing device, a first register means (RDB) for temporarily storing the amount of data transferred from the data buffer to the main memory; and a first register means (RDB) for decrementing the amount of data. 2 register means (
(SDC); a detection means (DEC) that detects zero in the count of the second register means and outputs an on signal; and a difference between the on signal of the detection means and the amount of data input and output in the data buffer. and an AND gate (204) that detects a match and sends a data sub-response instruction signal, and stores a suppression instruction for data transfer from the input/output device to the data buffer and its release from the data buffer in the main memory. A data suppression control circuit characterized by controlling based on the amount of data.