JPH045748A - Information processor - Google Patents

Abstract

PURPOSE:To realize data transfer between two devices, and to improve a throughput by executing the data transfer through a register in a microcomputer. CONSTITUTION:The address of a data transfer destination and the number of pieces of transferred data are set. Storage data on the address of the transfer destination in a RAM 3 is transferred to the register in the microcomputer 1. Then, the value of the address of the transfer destination is advanced by 1. The number of pieces of the transferred data is decreased by 1, and it is decided whether the transfer of all the data is completed or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that performs information processing.

[Prior Art] Conventionally, data has been transmitted between a plurality of information processing devices via serial or parallel input/output devices.

[Problems to be Solved by the Invention] When connecting a plurality of devices, each information processing device operates asynchronously, so some kind of synchronization processing is required when transmitting data. Therefore, there is a problem in that the time required for synchronization is wasted and the data transmission speed is reduced.

An object of the present invention is to provide an information processing device that solves the above problems.

[Means for Solving the Problems] In the present invention, in order to solve the above-mentioned problems, the system buses of the respective information processing devices are logically directly connected to exchange data.

[Function] According to the present invention, the time required for synchronization processing is omitted, making it possible to transfer data at higher speed.

[Example] As an example of the present invention, an example of a system in which microcomputers are connected will be described. Figure 1 shows a block diagram when this system is connected. The operation when transmitting data from microcomputer 1 to microcomputer 2 will be explained.

When the connection device 6 is disconnected, control of the first microcomputer 1 is realized by a first control program that is built-in and exists inside the first 80M2.

Further, the control of the second microcomputer 7 is realized by a second control program that exists in the built-in and second ROMB.

When data is to be transferred, when the system buses 5 and 11 of the microcomputer 1 and the microcomputer 7 are connected to each other by the connecting device 6, the microcomputer 7 is logically disconnected from the system bus and becomes non-functional. Control at this time is realized by the microcomputer 1 and a third control program stored in the ROM 2.

4 is the first Ilo, and to is the second Ilo.

The operation when transferring data from microcomputer 1 to microcomputer 2 will be explained with reference to the flowchart in FIG. The address of the second RAM 9 is ROM
RAM 2 and the first RAM 3 are arranged in a different address space. The data to be transferred exists consecutively starting from the address within the RAM 3.

In step S1, a data transfer source address, a data transfer destination address, and the number of data to be transferred are set. Next, in step S2, the data stored at the transfer destination address in the RAM 3 is transferred to a register within the microcomputer 1. Then, for the next data transfer, the value of the transfer source address is incremented by one.

Then, in step S3, the data stored inside the register is transferred to the transfer destination address. Then, for the next data transfer, the value of the transfer destination address is incremented by one. In the next step 4, the number of data to be transferred is reduced by one, and it is determined whether the transfer of all data has been completed. The process ends when all data transfer is completed. If the data transfer is not completed, the process returns to step S2.

As described above, in this example, data is transferred via a register in the microcomputer, but by adding special hardware, data can be transferred directly from the first RAM to the second RAM using a method such as DMA. It is also possible to transfer to.

[Effects of the Invention] According to the present invention, it has become possible to transfer data between two devices at high speed, and it has become possible to improve the throughput of the system.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention, and FIG. 2 is a flowchart showing the operating procedure of the present invention. ■, 7...Microcomputer, 2.8...ROM, 3.9...RAM. 4.10... Input/output device (Ilo), 5.11...
System bus, 6... connection device. Figure 2

Claims (1)

[Claims] 1) A system bus of a first information processing device having a first input/output means, a first control means, and a first storage means; An information processing apparatus characterized in that a system bus of a second information processing apparatus having a control means and a second storage means is detachably connected to the system bus by means of a connecting means. 2) The device according to claim 1, further comprising function stopping means for stopping the function of the second control means after connection by the connecting means, and third control means for controlling the entire connected device. Information processing equipment.