JPH11110015A - Inter-cpu module data exchange device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To update the data right after an instruction is executed by preparing a shared register which serves as a common memory space between the 1st and 2nd CPU modules and reading in real time the data on other CPU modules via an instruction. SOLUTION: The execution of an instruction is started in a scanning mode (S20), and the data are read to a data register #2 of a CPU module 1 via a READ instruction based on a device number 3 of the file register of a CPU module 2 (S22). Meanwhile, the numeric value 5555 is stored in the device number 3 of the module 2 and then transferred as data (S23). Then the value 5555 is read to the data register #2 of the module 1 (S24), and the module 1 executes an END instruction (S26) and then performs the service processing (S28) and the refresh processing (S30) to end a scanning operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CPU module for executing a sequence program for controlling a machine tool or the like, particularly when a plurality of CPU modules can be used simultaneously on a data bus used for communication between modules. The improvement of data exchange.

[0002]

2. Description of the Related Art FIG. 4 is a diagram for explaining the operation of a conventional program controller (hereinafter referred to as a PLC). In PLC, a program created in advance is
Store in module memory. Next, the CPU sequentially calculates one instruction at a time from the first step, and after executing the END instruction,
In this method, service processing and refresh processing are performed, and instruction execution is repeated from the first step. One repetition of this instruction execution process is called one scan, and the time required for one scan execution is called a scan time.

[0003] The refresh process is a process in which data changes in units of 1 bit or 16 bits called input / output / shared / link devices are collectively processed by an input / output module / CP.
Data processing for storing data in each device area of the memory in the CPU module from the shared device area / link module in the U module and outputting the data to each device collectively.

By the way, with one CPU module,
It is assumed that the number of input / output contacts is 3000 points per 100 msec of scan time. At this time, the number of input / output contacts of the controlled
Suppose that a scan time of 100 ms must be secured at 6000 points. Then, it becomes necessary to provide two CPU modules in parallel. Each CPU module can directly access only the input / output module that has its own input / output contact. On the other hand, depending on the operation instruction,
There is also a need to access other CPU module contacts. Therefore, when data is exchanged between the CPU modules, the data is mutually transferred for each scan of the shared device by the shared refresh processing.

FIG. 5 is an explanatory diagram of the shared refresh processing. For example, there is a case where a transporter for transporting components and an actuator for processing are controlled by separate CPU modules, and it is desired to perform processing smoothly by synchronizing. In such a case, it is necessary to copy the contents of the data register of the CPU module 1 to the data register of the CPU module 2. In the conventional shared refresh processing, data is exchanged at regular intervals in a shared register shared by the CPU modules 1 and 2. So, CPU
The contents of the data register of the module 1 are moved to the shared register, then the shared refresh processing is performed, and finally the CPU
Three steps of transferring data transferred from the shared register of the module 2 to the data register are required.

[0006]

However, in the conventional data exchange by the shared refresh processing, even if data is manipulated by executing an instruction in a program, data update in another CPU module waits until the shared refresh processing. There was a problem that it had to be real-time. Furthermore, when data exchange needs to be performed by another device such as a data register or a file register other than the shared register, it is necessary to temporarily transfer data to the shared register, which takes a long time. The present invention has solved such a problem, and it is possible to exchange data between CPU modules in real time and to perform data exchange with another device such as a data register other than a shared register or a file register. It is another object of the present invention to provide a data exchange device that can cope with the problem.

[0007]

In order to achieve the above object, a data exchange device between CPU modules according to the first aspect of the present invention takes charge of a first CPU module and the first CPU module. A device having a second CPU module having input / output contacts and individual devices independent of input / output contacts and individual devices, and a shared register serving as a common memory space between these CPU modules. It is characterized by having an instruction to read data in real time. According to the first aspect of the present invention, since an instruction to read data of another CPU module in real time is provided, data can be updated immediately after execution of the instruction, and there is no need to wait for a shared refresh process.

According to a second aspect of the present invention, there is provided an apparatus for exchanging data between CPU modules, comprising: a first CPU module; an input / output contact independent of an input / output contact or an individual device assigned to the first CPU module; A device having a second CPU module having a device and a shared register serving as a common memory space between these CPU modules, characterized by having an instruction to write data to another CPU module in real time. According to the second aspect of the present invention, since an instruction for writing data to another CPU module in real time is provided, the data can be updated immediately after the instruction is executed, and there is no need to wait for the shared refresh processing.

Here, when the read / write instruction in real time is configured to cause an interrupt to another CPU module, the interrupt processing is processed with higher priority than the normal processing. Therefore, real-time property is ensured. In addition, when a read / write instruction in real time is targeted for a device assigned to a shared register, the instruction may be handled in accordance with the conventional shared refresh processing.
Good consistency with previous operation instructions. Furthermore, when the read / write instruction in real time is directed to a device uniquely assigned to another CPU module, the device can directly access a device other than the shared register, and the difference between the CPU modules can be reduced. You can create programs without being conscious.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a configuration block diagram showing one embodiment of the present invention. In FIG. 1, components having the same functions as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted. Here, CP
READ / WR in instruction execution processing of U modules 1 and 2
An ITE instruction has been newly established. The READ instruction is
This is an instruction to read data of the U module in real time, which is an interrupt process for other CPU modules. The WRITE instruction is an instruction for writing data of another CPU module in real time, and is an interrupt process for the other CPU module. The target device of the read instruction or the write instruction may be a shared register or a data register or a file register unique to another CPU module.

Next, the operation of the thus constructed apparatus will be described. FIG. 2 is a flowchart for explaining the processing procedure of the write instruction. First, the instruction execution process in the current scan is started (S10). From CPU module 1 to CPU
In the device number 4 of the file register of module 2,
The numerical value 1234 is written by a WRITE instruction (S12).
Then, data transfer is performed, and the numerical value 1234 is written to the device number 4 of the file register of the CPU module 2 (S13). Then, the CPU module 1 executes the END instruction (S14), and executes the service processing (S1).
6), refresh processing (S18) is performed, and the current scan ends.

FIG. 3 is a flowchart for explaining the processing procedure of a read instruction. First, the instruction execution process in the current scan is started (S20). From the device number 3 in the file register of the CPU module 2, the CPU module 1
The data is read into the data register 2 by the READ instruction (S22). Here, since the numerical value 5555 is stored in the device number 3 of the file register of the CPU module 2, the data is transferred (S23).
Then, the numerical value 5555 is read into the data register 2 of the CPU module 1 (S24). And CPU
In the module 1, an END instruction is executed (S26), a service process (S28), a refresh process (S30) are performed, and the current scan ends.

In the above embodiment, a read / write instruction is used for reading / writing. However, the present invention is not limited to this, and it is sufficient that reading / writing processing can be performed in real time. .

[0014]

As described above, according to the first aspect of the present invention, since an instruction to read data of another CPU module in real time is provided, the data is updated immediately after the instruction is executed. And there is no need to wait for the shared refresh process. According to the invention described in claim 2,
Since there is an instruction to write data of another CPU module in real time, the data can be updated immediately after the instruction is executed, and there is no need to wait for the shared refresh processing.

Next, if the read / write instruction in real time is configured to cause an interrupt to another CPU module, the interrupt process is processed with higher priority than the normal process. Therefore, real-time property is ensured. In addition, when a read / write instruction in real time is targeted for a device assigned to a shared register, it can be handled in accordance with the conventional shared refresh processing. Good consistency. Furthermore, when the read / write instruction in real time is directed to a device uniquely assigned to another CPU module, the device can directly access a device other than the shared register, and the difference between the CPU modules can be reduced. You can create programs without being conscious.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing procedure of a write instruction.

FIG. 3 is a flowchart illustrating a processing procedure of a read instruction.

FIG. 4 is a diagram for explaining an arithmetic processing process of a conventional program controller.

FIG. 5 is an explanatory diagram of a shared refresh process.

[Explanation of symbols]

 READ Read instruction WRITE Write instruction

Claims (5)

[Claims] 1. A first CPU module and a first CPU module.
A second C having input / output contacts and individual devices independent of the input / output contacts and individual devices assigned to the PU module
What is claimed is: 1. A data exchange device between CPU modules, comprising: a PU module; and a shared register serving as a common memory space between the CPU modules, comprising an instruction to read data of another CPU module in real time. 2. A first CPU module and a first CPU module.
A second C having input / output contacts and individual devices independent of the input / output contacts and individual devices assigned to the PU module
An apparatus having a PU module and a shared register serving as a common memory space between the CPU modules, wherein the apparatus has an instruction to write data to another CPU module in real time. 3. The data exchange apparatus according to claim 1, wherein the read / write instruction in real time is accompanied by an interrupt to another CPU module. 4. The data exchange device between CPU modules according to claim 1, wherein said read / write instruction in real time is directed to a device assigned to a shared register. 5. The data exchange device between CPU modules according to claim 1, wherein the read / write instruction in real time is directed to a device uniquely assigned to another CPU module.