JPH09218863A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer data without being affected by the throughput of respective function blocks. SOLUTION: A CPU 11 stores transfer data D1 to a slave function block 20 in a storage area 12a corresponding to the slave function block 20 and issues a transfer command to a common communication control circuit 13. The common communication control circuit 13 reads the transfer data D1, adds the address A1 of the slave function block 20 and outputs them to a bus 40. The respective slave function blocks 20 and 30 receive the transfer data on the bus 40 and store the received data D1 in their own memory 22 only when a destination address A1 matches with their own address. The CPU 21 of the slave function block 20 reads the data D1 stored in its own memory 22 and processes them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system for dividing a series of data processing into a plurality of processing and executing each divided data processing by a plurality of processors connected to a bus in, for example, a digital exchange. (Hereinafter, simply referred to as “system”), and particularly relates to data transfer between processors.

[0002]

2. Description of the Related Art Conventionally, in such a system, a method of transmitting and receiving information between respective processors via a shared memory has been used. This has been realized by setting an area for each processor in the shared memory in advance and each processor accessing the area for writing and reading. FIG. 2 is a block diagram showing an example of a bus connection between processors using a shared memory in a conventional system such as a digital exchange. This system includes a processor 1 that controls the entire system, and the processor 1.
Multiple processors that perform individual processing according to the instructions
3 and a shared memory 4 for storing data commonly used among the processors 1, 2, and 3. These processors 1, 2, 3 are commonly connected to the shared memory 4 via the address bus 5, the data bus 6, and the control bus 7 in order to access the shared memory 4.

FIG. 3 is a sequence diagram showing an example of data transfer between processors in the conventional system of FIG. Data transfer in the conventional system will be described below with reference to FIG. When transferring the data D1 from the processor 1 to the processor 2, first, the processor 1 outputs the address A1 of the shared memory 4 assigned to the processor 2 to the address bus 5 and the data D1 to be transferred to the data bus 6, respectively. , And outputs a write control signal to the control bus 7. As a result, the data D1 is written to the address A1 of the shared memory 4. When writing data to a plurality of addresses, the above operation is repeated for each address. In this way, the data D1 is sent to the shared memory 4.
After the writing of the
Notify that the writing is completed. This writing completion notification is, for example,
This is performed by outputting the address of the processor 2 to the address bus 5, outputting a code indicating the completion of writing to the data bus 6, and outputting a write control signal to the control bus 7.

Upon receiving the write completion notice, the processor 2 reads the data D1 from the address A1 of the shared memory 4. The reading of the data D1 is performed, for example, by outputting the address A1 to the address bus 5 and outputting the read control signal to the control bus 7. When reading data from a plurality of addresses, the read operation is repeated for each address. In this way, after the reading of the data D1 from the shared memory 4 is completed, the processor 2 notifies the processor 1 of the read completion. This read completion notification is performed, for example, by outputting the address of the processor 1 to the address bus 5, outputting a code indicating the read completion to the data bus 6, and outputting a write control signal to the control bus 7. The transfer of the data D2 from the processor 1 to the processor 3 is also performed in the same sequence.

[0005]

However, the data transfer of the conventional system has the following problems.
For example, the data D1 from the processor 1 to the shared memory 4
The common address bus 5, the data bus 6, and the control bus 7 are used for the writing of data and the reading of the data D1 from the shared memory 4 to the processor 2.
Therefore, when any one of the processors is accessing the shared memory 4, the other processors cannot access the shared memory 4. Since this access time depends on the processing speed of each processor, in order to improve the transfer speed between the processor 1 and the processors 2 and 3, it is necessary to increase the processing capacity of all the processors 2 and 3. Become. Therefore, in order to improve the data transfer rate, each processor is required to have more processing capacity than necessary, and it is difficult to select a processor having an appropriate processing capacity for each distributed function. The present invention provides a system capable of data transfer that does not depend on the processing capability of a processor, as a problem that the above-mentioned conventional technique has.

[0006]

In order to solve the above-mentioned problems, a first function of the present invention is to provide a master functional block for controlling the entire system, and a plurality of digital data processing units to which an address is assigned and which executes digital data processing under the control of the master functional block. In the system in which the slave function block and the slave function block are connected to each other via a bus, the master function block and the slave function block are configured as follows. That is, the master functional block is assigned to each of the slave functional blocks, and a common storage unit having a plurality of storage areas for storing transfer data instructing processing contents in each slave functional block; The data stored in the area is added to the address of the slave functional block and output to the bus, and the common data transfer unit that receives the data transferred via the bus, and the processing of each slave functional block And a common control unit that monitors the state and accesses the common storage unit to instruct each of the slave functional blocks and controls the operation of the common data transfer unit. Each of the slave functional blocks has a storage capacity corresponding to the storage area, stores a transfer data transferred from the master functional block via the bus, and stores the transfer data with an address. Only when the address of the transfer data with this address received and the address of its own coincides, there is a reception function of storing the received transfer data in the storage section, and the data is output to the bus. A data transfer unit having a transmission function and a control unit for controlling the storage unit and the data transfer unit to execute the digital data processing are provided. In the second invention, the transfer data to which the address is added is serially transferred through the bus.

According to the first and second aspects of the invention, since the system is configured as described above, the following operation is performed in the data transfer between the functional blocks. The master functional block receives data from each slave functional block via the bus and monitors the status of each slave functional block process. When the processing of each slave functional block progresses and the master functional block needs an instruction to the slave functional block, the common control unit stores the transfer data instructing the processing content in the storage area corresponding to the slave functional block. . Then, the common transfer unit is instructed to transfer the data in the storage area. Upon receiving the instruction, the common transfer unit adds the address of the slave functional block of the destination to the data stored in the storage area and outputs it to the bus. On the other hand, in each slave function block,
The data transfer unit receives the transfer data with the destination address transferred via the bus. Then, when the destination address matches its own address, the received transfer data is stored in the storage unit. If they do not match, they are not stored in the storage unit. When the storage of the transfer data is completed, the data transfer unit notifies the control unit that the transfer data has been received. After that, the control unit reads the transfer data from the storage unit and executes the data processing. When the data processing on the transfer data is completed, the slave functional block notifies the master functional block that the next transfer data can be received via the bus. As described above, since the data transfer between the storage area of the master functional block and the storage section of each slave functional block is performed without passing through the control section of the slave functional block, the storage section of each slave functional block is , Acts as if they were common storage units of distributed master function blocks.

[0008]

FIG. 4 is a schematic configuration diagram of a digital exchange showing an example of an embodiment of the present invention. In this digital exchange, a master functional block 10 for controlling communication between processing devices, a slave functional block device 20 for performing signal processing of a subscriber line, and a slave functional block device 30 for performing signal processing of a trunk line connect a bus 40. Connected through. Further, the bus 40 is connected with a slave function block device 50 that performs signal processing of a common line, a slave function block 60 that performs call control processing, and the like. The master function block 10 includes a common control unit (for example, a central processing unit, hereinafter referred to as “CPU”) 11 that monitors and controls the processing of the entire digital exchange, and a common storage unit that stores data necessary for controlling the entire exchange (for example, a central processing unit). A memory) 12, a common data transfer unit (for example, a common communication control circuit) 13 that controls data transfer between each slave function block such as the slave function block 20 via the bus 40, and a peripheral device (not shown). It has a communication path bus control circuit and the like for making the connection.

The slave function block 20 controls a subscriber line signaling device 20A accommodating a plurality of subscriber lines 20a to which individual telephones are connected. (Eg CPU) 2
1, a storage unit (for example, a memory) 22 that stores data necessary for processing, and a master functional block 10 via a bus 40
A data transfer unit that controls data transfer between
The communication control circuit 23 includes a communication path bus control circuit (not shown) for performing data transfer with the subscriber line signaling device 20A via the communication path bus. The slave function block 30 is a relay line 30a for connecting to another exchange.
For controlling the relay line signal device 30A, which has a CPU 31, a memory 32, a communication control circuit 33 and the like having substantially the same functions as the slave function block 20.

The slave function block 50 controls the common line signal device 50A that houses the common signal line 50a for transmitting and receiving control signals between the exchanges, and has a CPU 5 having substantially the same function as the slave function block 20.
1, a memory 52, a communication control circuit 53, and the like. The slave function block 60 monitors and controls the state of connection control in each subscriber line 20a and relay line 30a, and a CPU that performs processing in the slave function block 60.
61, a memory 62 for storing data required for processing, a communication control circuit 63 for controlling data transfer with the master functional block 10 via the bus 40, and the like. Also,
The master function block 10, the subscriber line signaling device 20A, the trunk signaling device 30A, and the common signaling device 50A are connected to a time division speech path switch 70 that performs time division switching.

Here, the processing in the slave function block will be described by taking the subscriber line signal processing device 20 as an example. Subscriber line signal device 2 connected to subscriber line signal processing device 20 via a communication path bus control circuit (not shown)
0A transmits and receives signals for connection control to and from each telephone connected to the subscriber line 20a, and also connects analog call signals of individual subscriber lines 20a to the time division speech path switch 70. In addition, processing such as analog / digital conversion and multiplexing / demultiplexing is performed. For example, when the subscriber line control device 20A receives a call request from a certain telephone,
The destination telephone number is decrypted and transferred to the slave function block 20. The slave function block 20 is the bus 4
The call request including the destination number is transferred to the master function block 10 via 0. On the other hand, the subscriber line signaling device 20A
When there is an incoming call to the telephone housed in the slave function block 2 from the master function block 10 via the bus 40.
An incoming request including the number of the destination subscriber line 20a is transferred to 0. As described above, each slave function block such as the slave function block 20 is organically connected by data transfer with the master function block 10 connected via the bus 40, and given from the master function block 10. A series of telephone exchange processing is executed according to the instruction.

FIG. 1 shows an embodiment of the present invention.
FIG. 5 is a configuration diagram of a system including a master function block 10, slave function blocks 20 and 30, and a bus 40 in FIG. 4. In this system, a master functional block 10 that adjusts the processing of the entire system whose functions are divided and slave functional blocks 20 and 30 that perform the divided individual functions are commonly connected by a bus 40. The master function block 10 includes each slave function block 2
It has a CPU 11 that performs adjustment processing between 0 and 30,
The common memory 12 is connected to the PU 11. The common memory 12 stores the data to be transferred to the slave function blocks 20 and 30, and therefore, the storage areas 12 a, which are allocated corresponding to the slave function blocks 20 and 30,
12b. A communication control circuit 13 that outputs data stored in the common memory 12 to the bus 40 according to an instruction from the CPU 11 is connected to the CPU 11 and the common memory 12.

On the other hand, the slave function block 20 has a CPU 21 for performing individual processing of a system whose functions are divided, and a memory 22 for storing data necessary for performing the individual processing is connected to the CPU 21. Has been done. A communication control circuit 23 that receives data transferred via the bus 40 and stores the data in the memory 22 is connected to the CPU 21 and the memory 22. The slave function block 30 has the same function as the slave function block 20, the CPU 31, the memory 32, and the communication control circuit 3.
3 is provided. The bus 40 has a frame synchronization signal line 41 for giving a data transmission start timing, a clock signal line 42 for giving a bit timing for data transfer, a data signal line 43 for transmitting transfer data, and slave function blocks 20 and 30. It has enable signal lines 44a and 44b for displaying the states of whether or not the data reception is possible.

FIG. 5 is a sequence diagram of data transfer in the system of FIG. 1, and FIG. 6 is a time chart showing an example of data transferred via the bus 40 of FIG.
Next, the procedure of data transfer in the system of FIG. 1 will be described with reference to these drawings. First, when transferring the data D1 from the master function block 10 to the slave function block 20, the CPU 11 reads the state of the enable signal line 44a via the communication control circuit 13 at time t1 in FIG. Check whether it is ready to receive data. If the slave function block 20 can receive data, the CPU 11
Is the data D in the storage area 12a of the memory 12 at time t2.
Writing 1 is started. Then, at time t3, the data D
When the writing of 1 is completed, the CPU 11 instructs the communication control circuit 13 to start the transfer at time t4.

The communication control circuit 13 which has received the transfer start instruction
As shown in FIG. 6, at time t5 according to the frame synchronization signal SYN output to the frame synchronization signal line 41.
Then, the transmission of the header portion H1 is started. The header portion H1 includes the address A1 of the slave function block 20 that is the destination of the data D1 and other control information. Each bit of the data signal DATA is, for example, 8 MH
The data signal line 43 is synchronized with the clock signal CLK of z.
To be sent in series. Following the transmission of the header portion H1, the communication control circuit 13 transmits the data D1 read from the storage area 12a, and further transmits a frame check sequence (hereinafter, referred to as “FCS”) for transmission error correction and the like. When the transmission of the series of information including the data D1 is completed at time t6, the communication control circuit 13 sends CP at time t7.
The U11 is notified of the completion of transmission. Thereby, C
The PU 11 can perform a transmission process for the next slave function block 30.

On the other hand, in the slave function block 20, when the communication control circuit 21 receives the header portion H1 sent by the data signal line 43 in accordance with the respective signals of the frame synchronization signal line 41 and the clock signal line 42, the header portion H is immediately sent.
The destination address A in 1 is checked. And if the destination address A matches its own address A1,
The subsequently transmitted data D1 is received and stored in the memory 22. If the destination address A is own address A1
If it does not match, the data D1 is not stored in the memory 22. In this case, since the destination address A matches the address A1 of the slave function block 20, the data D1 is stored in the memory 22. Then, when the storage of the reception data D1 in the memory is completed, the communication control circuit 23 notifies the CPU 21 of the reception completion at time t8. The CPU 21, which has received the reception completion notification, receives the time t9.
The enable signal line 44a is turned off to indicate to the master control block 10 that the next data D1 cannot be received. After that, the CPU 21 reads the data D1 stored in the memory 22 from time t10 to time t11 and performs a predetermined process. Then, at the time t12 when the reading process of the data D1 is completed, the CPU 21 turns on the enable signal line 44a and displays on the master function block 10 that the next data D1 can be received. The master function block 10 also transfers the data D2 to the slave function block 20 in the same procedure. In this case, as shown in FIG. 5, regardless of the processing of the data D1 in the slave functional block 20, the data D1
It is possible to transfer 2.

As described above, this embodiment has the following advantages (1) to (4). (1) As shown in FIG. 5, the transfer time of the data D1 from the master functional block 10 to the slave functional block 20 is from time t5 to t6, and
1 is transferred according to the clock signal CLK of 8 MHz. Therefore, the transfer time is irrelevant to the processing capability of the CPU 21 of the slave function block 20, and the bus 40 can be used efficiently. (2) Since the bus 40 of FIG. 1 performs serial transmission of the data D1, it can be composed of a small number of signal lines. (3) The enable / disable signal lines 44a and 44b shown in FIG. 1 are used to display the status of reception on the slave function block side on the master function block 10. Therefore, the data transfer for displaying the status of the slave function block is not necessary and confirmation is made. The process is simplified. Furthermore, since the data is transferred after confirming that the data can be received, there is no risk that the next data will be transferred and the previous data will be rewritten before the processing on the slave function block side is completed. (4) As shown in FIG. 6, since the FCS is continuously transmitted after the transfer data D1, the receiving side can check or correct a transmission error, and when an error is detected, a retransmission request or the like is sent. Transmission errors can be avoided by incorporating the procedure.

The present invention is not limited to the above embodiment, but can be variously modified. For example, there are the following modifications (a) to (f). (A) In the system shown in FIG. 1, two slave function blocks are provided.
Although it is configured by individual units, a system having three or more slave functional blocks can be similarly configured. (B) In the system of FIG. 1, the serial transmission bus is used as the bus 40, but a parallel transmission bus using a plurality of address, data, and control signal lines can be similarly configured. By using a parallel transmission bus,
Although the number of signal lines increases, the transfer speed can be improved. (C) The serial transmission bus 40 of the system shown in FIG. 1 has a clock signal CLK and a frame synchronization signal SY as shown in FIG.
Although the bit synchronization method using N is adopted, a method that does not use a clock synchronization signal or a frame synchronization signal, for example, a start-stop synchronization method may be used. In a system that does not require a high transfer rate, this can reduce the device scale.

(D) In the system of FIG. 1, dedicated enable signal lines 44a and 44b are used to display the states of the slave function blocks 20 and 30, but data signal lines from the slave function block to the master function block are used. May be used to transmit the control information. As a result, the number of signal lines can be reduced, which is particularly effective when the number of slave functional blocks is large. (E) In the system of FIG. 1, enable signal lines 44a,
Although the status of whether or not the slave functional blocks 20 and 30 can be received is displayed by 44b, if the system is such that the processing time in the slave functional block is surely completed before the next data D1 is transferred, the status of whether or not the slave can be received is judged. No labeling required. As such a system, for example, there is a system in which data is transferred from a master functional block in response to a request from a slave functional block. (F) In FIG. 6, the FCS is continuously transmitted after the transfer data D1, but when there is almost no possibility of a transmission error, or when the data check is performed in the processing of the CPU of the slave functional block, There is no need to transmit FCS.

[0020]

As described in detail above, according to the present invention, the common storage section of the master function block is provided with the storage areas corresponding to the plurality of slave function blocks, and each slave function block is provided with the common storage section. A storage unit corresponding to the storage area is provided. Then, the transfer data stored in the storage area of the common control unit is transferred to the storage unit of the corresponding slave functional block via the bus by the common transfer unit. Therefore, the contents of the storage unit of each slave function block are the same as the contents of the storage area of the common storage unit. When processing data, each slave functional block only needs to read the storage unit in the functional block, and access using the bus between the functional blocks is not necessary. As a result, each slave functional block can perform data processing without affecting other slave functional blocks. As a result, it becomes easy to improve the data transfer rate between the master functional block and the slave functional block. Further, in each slave functional block, the CP of the processing speed corresponding to the data processing is
It becomes possible to select U.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional multiprocessor system.

3 is a sequence diagram of data transfer between the processors of FIG.

FIG. 4 is a configuration diagram of a digital exchange according to an example of an embodiment of the present invention.

5 is a data transfer sequence configuration diagram between the functional blocks of FIG. 1;

6 is a time chart of data transfer by the bus of FIG.

[Explanation of symbols]

 10 Master Function Blocks 11, 21, 31 CPU 12 Common Memory 12a, 12b Storage Area 13 Common Communication Control Circuit 20, 30 Slave Function Block 22, 32 Memory 23, 33 Communication Control Circuit 40 Bus

Claims (2)

[Claims] 1. A multi-function system in which a master functional block that controls the entire system and a plurality of slave functional blocks that are given addresses and execute digital data processing under the control of the master functional block are connected to each other via a bus. In the processor system, the master functional block is assigned to each slave functional block, and has a plurality of storage areas for storing transfer data instructing processing contents in each slave functional block. A common data transfer unit that outputs the data stored in the storage area to the bus with the address of the slave functional block added thereto, and receives the data transferred via the bus; Monitor the processing state of the functional blocks and for each of those slave functional blocks A common control unit for accessing the common storage unit and controlling the operation of the common data transfer unit for indicating, wherein each slave functional block has a storage capacity corresponding to the storage area, and A storage unit that stores transfer data transferred from the functional block via the bus, and only when the transfer data with the address is received and the address of the transfer data with the address matches its own address. A data transfer unit having a reception function of storing the received transfer data in the storage unit and having a transmission function of outputting the data to the bus; and controlling the storage unit and the data transfer unit to store the data. A multiprocessor system comprising: a control unit that executes digital data processing. 2. The bus serially transfers the transfer data to which the address is added.
The described multiprocessor system.