JPH0951562A - Function extension system of dsp mounted device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide data on a filter coefficient, etc., for a plurality of DSPs(digital signal processor) by distributing the contents of a ROM to the DSPs. SOLUTION: This system is equipped with the DSPs 10 and the ROM 20 which stores the filter coefficient, initial conditions, branch conditions, etc. Further, the DSPs 10 and ROM 20 are connected by a bus 21. This bus 21 includes an address bus and a data bus. Consequently, the data on the filter coefficient, etc., can be distributed to the respective DSPs 10 in common and the data on the filter coefficient, etc., can be provided for the DSPs 10. In this case, the filter characteristics of the DSPs 10 can be changed only by the replacement of the one ROM. Consequently, the function extension system of the DSP mounted device is obtained which can provide the data on the filter coefficient, etc., for the DSPs 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function expansion system for DSP mounted devices.

[0002]

2. Description of the Related Art FIG. 22 is a conceptual diagram of a conventional system.
In the figure, 1 is an exchange, 2 is a central processing unit (CC) that controls the exchange, 3 is a line connected to the exchange 1, 4
Is a subscriber telephone connected to the exchange 1. Exchange 1
In the figure, 10 is a DSP (Digital Signal Processor) as a signal receiving device installed in the exchange 1.
It is. When the subscriber telephone set 4 is of the PB (push button) type, the dialed digits are given as a combination of two frequencies. A signal given by a combination of these two frequencies is referred to as DTMF (Dual Tone Multi).
Frequency) signal.

The DSP 10 extracts a specific frequency component from the DTMF dial signal received from the subscriber PB telephone 4 and determines a dial number. D
The signals received and analyzed by the SP 10 include inter-station control MF (Multi Frequency) signals and the like.

When a signal receiver equipped with a DSP receives a time-division multiplexed line, a plurality of DSs are packaged on a package.
P is installed, and the lines are distributed and processed in parallel. By the way, a digital filter for passing only a specific frequency is incorporated in the DSP 10. This digital filter is characterized in that the frequency characteristic and the time characteristic can be significantly changed by changing only the coefficient of the logical expression of the filter. It is useful to allow only the filter coefficient to be changed via the external interface while leaving the program for realizing the digital filter as it is, since the adjustment range of the operation of the DSP is provided.

[0005]

Conventionally, the means for changing the digital filter coefficient in this type of device is as follows.
A circuit for changing the coefficient is provided in advance on the DSP side, but the method of reading filter coefficients from the same database by a plurality of DSPs is not considered, and each device is devised with an external circuit. Is the current situation.

The present invention has been made in view of the above problems, and is characterized by providing a function expansion system for a DSP-equipped device capable of providing data such as filter coefficients to a plurality of DSPs. .

[0007]

FIG. 1 is a block diagram showing the principle of the first invention, FIG. 2 is a block diagram showing the principle of the second invention, and FIG.
FIG. 9 is a block diagram of the principle of the third invention. In FIG.
The same parts as those in FIG. 22 are designated by the same reference numerals. In the figure, 10 is a plurality of DSPs provided, and 20 is a ROM for storing filter coefficients, initial conditions, branch conditions and the like.
A bus 21 connects between the DSP 10 and the ROM 20. The bus 21 includes an address bus and a data bus.

By adopting such a configuration, each DS
The data such as the filter coefficient can be shared in common to P10, and the data such as the filter coefficient can be provided to the plurality of DSPs 10. Further, the filter characteristic of the DSP 10 can be changed by only replacing one ROM.

In FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals. In the figure, 10 is a DSP provided with two # 1 and # 2, 50 is a bus arbitration means for arbitrating output address information of the DSP 10 connected to the address bus 23 of the DSP 10, and 40 is an output of the bus arbitration means 50. The memory is accessed by an address bus and stores filter coefficients, initial conditions, branch conditions, and the like. 30 is DS
Receiving the status information of each P10, these DSP1
It is a DSP control means for controlling the 0 address output state. The number of DSPs 10 does not have to be two, and may be any number.

With such a configuration, the data stored in the memory 40 can be sequentially provided to each DSP 10, and the data such as the filter coefficient can be provided to the plurality of DSPs.

In this case, the bus arbitration means 50
Is provided with high-impedance control means for making the output of the high-impedance output high-impedance
A function capable of individually controlling the hard reset of 10 and a DSP by giving a control signal to the high impedance control means.
The DSP 10 is provided with a function of making the external address bus high impedance, and each DSP 10 is provided with an external bus read routine immediately after a hard reset and a read completion notification routine.

According to the present invention, when the DSP 10 is reset (when the operation of the DSP is initialized), the filter coefficient can be read from the memory 40 and the filter characteristic can be changed. Further, the DSP control means 30 is provided with a function capable of individually controlling the hard reset of each DSP 10,
The SP 10 is provided with a function of making the external address bus high impedance, and the DSP 10 is provided with a routine for making the external address high impedance, an external bus read routine, and a read completion notification routine.

According to the present invention, when the DSP 10 is reset (when the operation of the DSP is initialized), the filter coefficient can be read from the memory 40 to change the filter characteristic. Further, a high impedance control means for setting the output of the bus arbitration means 50 to a high impedance is provided, and the DSP control means 30 is provided with a function of controlling an external interrupt of each DSP 10 and a control signal to the high impedance control means. The DSP is provided with a function to make the external address bus high impedance, and the DSP 10 is provided with an external bus read routine at the time of interruption and a read completion notification routine.

According to the present invention, it is possible to read the filter coefficient and change the filter characteristic while the DSP 10 is operating. In addition, the DSP control means 30 is provided with each DSP.
A function capable of controlling 10 external interrupts is provided, and the DS
The P10 is provided with a function of making the external address bus high impedance, and the DSP 10 is provided with a control routine for making the external address high impedance, an external bus read routine at the time of interruption, and a read completion notification routine. I am trying.

According to the present invention, the filter coefficient can be read and the filter characteristic can be changed during the operation of the DSP 10. In addition, the DSP control means 30
When the data on the external bus shared by P10 is read, a function of receiving the read status from each DSP 10, a function of measuring the external bus read time of each DSP 10, and a function of disconnecting the external address bus of DSP 10 are provided. The DSP 10 is provided with an external bus read state notification routine.

According to the present invention, the DSP 10 in which the filter coefficient reading has failed is disconnected from the address bus, and the normal DSP 10 can continue its operation. In FIG.
The same components as those in FIG. 2 are denoted by the same reference numerals. In the figure, 10 is a DSP provided with two # 1 and # 2, 40
Is a memory for storing various information and accommodation address identification information and giving the stored information to the plurality of DSPs 10, and 30 is a DSP control means for giving a control signal to the DSPs 10 and giving an address to the memory 40. In the present invention, the output address of the DSP 10 is not accessed by the memory 10, but the memory 10 is accessed by the memory control unit 30a provided in the DSP control means 30. The number of DSPs 10 need not be two,
It can be any number.

According to the present invention, the memory 40 side defines whether to transmit coefficient data to all of the plurality of DSPs 10 connected to the data bus or to a specific DSP 10. Therefore, each DSP 10 can It is possible to identify the output data of the memory 10 to be taken in by the accommodation address identification information.

In this case, the DSP control means 3
Function to specify memory address to 0 (memory control unit 3
0a) is provided, and the DSP 10 is provided with a routine for identifying the accommodation address of the memory and reading only the designated data.

According to the present invention, the required filter coefficient data can be supplied to the DSP 10 without accessing the memory 40 from the DSP 10.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. An embodiment of the first invention will be described with reference to FIG. In the first invention,
The ROM 20 and the plurality of DSPs 10 are connected to each other via a bus 21. In this case, the output data can be distributed to each DSP 10 by giving an address to the ROM 20 from an access means (not shown). Each DSP 10 internally takes in data such as a filter coefficient given from the bus 21.

By adopting such a configuration, each DS
Data such as filter coefficients can be shared in common to P10, and data such as filter coefficients can be provided to a plurality of DSPs. If necessary, the filter characteristic of the DSP 10 can be changed by replacing only one ROM.

FIG. 4 is a block diagram showing a first embodiment of the second invention. The same components as those in FIG. 2 are denoted by the same reference numerals. In the figure, 10 is a DSP. The first DSP is DSP1 and the second DSP is DSP2. These DSP1 and DSP2 are provided with an external bus read routine immediately after a hard reset and a read completion routine.

Reference numeral 11 is a buffer for receiving the output address data of the DSP1 and DSP2. A buffer that receives the output of the DSP 1 is referred to as a buffer 1, and a buffer that receives the output of the DSP 2 is referred to as a buffer 2. The buffer 11 has an enable input E in addition to the data input terminal I, and by inputting a signal to this enable input, its output can be made high impedance. The buffer 1 and the buffer 2 constitute the bus arbitration means 50 of FIG. The output buses of the buffer 1 and the buffer 2 are connected to each other and are stored in the memory 40. Memory 40
Output data of each D via the data bus 22.
It is in SP1 and DSP2.

Reference numeral 31 is a clock generation circuit for supplying an operation clock to the DSP1 and DSP2, and 32 is each DSP1, DS.
This is a DSP reset control unit capable of individually controlling the hard reset of P2. The output of the DSP reset controller 32 is supplied to the DSP 1 as a reset signal RST1,
It is also input to DSP2 as a reset signal RST2. The DSP reset controller 32 includes DSP1, DS
The status information is input as P1 and P2 from the P terminal of P2. Reference numeral 33 is a high-impedance control unit that independently controls the outputs of the buffer 1 and the buffer 2 to be high impedance. These clock generation circuits 31, D
The SP reset control section 32 and the high impedance control section 33 constitute the DSP control means 30 of FIG. Further, the high impedance control unit 33 exchanges information with the DSP reset control unit 32. The operation of the apparatus configured as described above will be described below.

Description will be made with reference to the time chart of FIG. First, when the power of the apparatus is turned on as shown in (a), the DSP reset control section 32 raises power-on reset signals RST1 and RST2 as shown in (c) and (g). These reset signals are DSP1, DSP2
Since it enters the reset input RST of, DSP1, DSP2
Is in a hard reset state while the reset signal is at "1" level as shown in (e) and (i), respectively. When the power is turned on, the clock generation circuit 31
A clock is constantly generated as shown in FIG.

Here, at time t1, the reset signal RST1
Falls to "0" level, the DSP 1 starts the program operation from the address 1 and outputs the address data. At the same time, the high impedance control unit 33 (d)
The high impedance control signal E1 which makes its output active is output to the buffer 1 as shown in FIG. The buffer 1 outputs the output address data of the DSP 1. On the other hand, the buffer 2 is in the high impedance state because the control signal E2 has not risen. As a result, DS
The address data output from P1 is the address bus 2
The memory 40 is accessed via 3. Data (for example, coefficient data of digital filter) corresponding to the access address is output from the memory 40, and the data bus 22
Is input to the DSP 1 via. After reading the data, the DSP 1 reads DS, as shown in (f), at time t2.
A data read completion signal P1 is transmitted to the P reset control unit 32. The DSP 1 then executes a main program (for example, digital filter operation).

Upon receiving the data read completion signal P1, the DSP reset control section 32 next resets the reset signal RS.
T2 is lowered to "0" level. As a result, DSP2
Becomes active, starts the program operation from the address 1, and outputs the address data. At the same time, the high impedance control unit 33 outputs a high impedance control signal E2 that activates its output to the buffer 2 as shown in (h). At the same time, E1 falls to "0". The buffer 2 outputs the output address data of the DSP 2. On the other hand, in the buffer 1, the control signal E1 has not risen and is in a high impedance state. As a result, the address data output from the DSP 2 is accessed to the memory 40 via the address bus 23. Data (for example, digital filter coefficient data) corresponding to the access address is output from the memory 40 and input to the DSP 2 via the data bus 22. After reading the data, the DSP 2 sends a data read completion signal P2 to the DSP reset control section 32 at time t3 as shown in (j). Upon receiving the completion signal P2, the DSP reset control unit 32 lowers the high impedance signal E2 to the "0" level as shown in (h). As a result, the address bus 23 input to the memory 40 of both the DSP 1 and the DSP 2 is in a high impedance state. The DSP 2 then executes a main program (for example, digital filter operation). Hereinafter, the same operation will be repeated.

FIG. 6 is a flow chart showing the operation of the first embodiment of the second invention, showing the operation of the DSP. When the hard reset state is released (S1), the data of the external bus (data bus 22) is read, the bus data read completion signal P is transmitted (S3), and then the main program is executed (S4).

According to this embodiment, when the DSP 10 is reset (when the operation of the DSP is initialized), the filter coefficient can be read from the memory 40 to change the filter characteristic. FIG. 7 is a block diagram showing a second embodiment example of the second invention. The same parts as those in FIG. 4 are designated by the same reference numerals. In this embodiment, the respective DSP1 and DSP2 are
The high impedance control section 33 is unnecessary by providing the function of making the address bus high impedance. Therefore, the output address bus 23 of the DSP1 and DSP2 directly enters the memory 40. DSP10
In addition to the above-described routine for making the bus high impedance, an external bus read routine and a read completion notification routine are provided. Further, the DSP reset control unit 32 is provided with a function capable of individually controlling the hard reset of each DSP 10. The operation of the apparatus configured as described above will be described below.

Description will be made with reference to the time chart of FIG. First, when the power of the device is turned on as shown in (a), the DSP reset control section 32 raises power-on reset signals RST1 and RST2 as shown in (c) and (f). These reset signals are DSP1, DSP2
Since it enters the reset input RST of, DSP1, DSP2
Is in a hard reset state while the reset signal is at "1" level as shown in (d) and (g), respectively. When the power is turned on, the clock generation circuit 31
A clock is constantly generated as shown in FIG.

Here, at time t1, the reset signal RST1
Falls to the "0" level, the DSP 1 starts the program operation from the address 1, activates its own output address bus (state A), and outputs the address data. On the other hand, the DSP 2 is still in the hard reset state, and its address bus 23 is in the high impedance state. As a result, the address data output from the DSP 1 is accessed to the memory 40 via the address bus 23. Data (for example, digital filter coefficient data) corresponding to the access address is output from the memory 40 and input to the DSP 1 via the data bus 22. After reading the data, the DSP 1 sends a data read completion signal P1 to the DSP reset control section 32 at time t2 as shown in (e). The DSP 1 then executes a main program (for example, digital filter operation).

Upon receiving the data read completion signal P1, the DSP reset control unit 32 next resets the reset signal RS.
T2 is lowered to "0" level as shown in (f).
As a result, the DSP 2 becomes active, its address bus 23 becomes active (state A) as shown in (g), the program operation from the address 1 is started, and the address data is output. At this time, the address bus 23 of DSP1
Is in a high impedance state.

As a result, the address data output from the DSP 2 is accessed to the memory 40 via the address bus 23. From the memory 40, data corresponding to the access address (for example, coefficient data of digital filter)
Is output and input to the DSP 2 via the data bus 22. After reading the data, the DSP 2 sends a data read completion signal P2 to the DSP reset control section 32 at time t3 as shown in (h). At this time, DSP
The address bus 23 input to the memory 40 of both 1 and DSP 2 is in a high impedance state. DSP2
Then, the main program (for example, digital filter operation) is executed. Hereinafter, the same operation will be repeated.

FIG. 9 is a flowchart showing the operation of the second embodiment of the second invention, showing the operation of the DSP. When the hard reset is released (S1), the high impedance state of the bus is released (S2), and the data is read from the external bus (S3). Next, the bus is set to high impedance again (S4), and the DSP reset control unit 3
A bus data read completion notification is sent to 2 (S5).
Then, the main program as a digital filter is executed (S6). Note that steps S2 to S5 in FIG. 9 correspond to the state A in FIG.

According to this embodiment, the filter characteristic can be changed by reading the filter coefficient from the memory 40 when the DSP 10 is reset (when the DSP operation is initialized). FIG. 10 is a block diagram showing a third exemplary embodiment of the second invention. The same parts as those in FIG. 4 are designated by the same reference numerals. In this embodiment, instead of performing a hard reset on the DSP 10, an interrupt (interrupt: IN
In T), the contents of the memory are read.
Reference numeral 34 denotes a DSP interrupt control unit that controls external interrupts of the DSPs 1 and 2 and also applies a control signal to the high impedance control unit 33 to control the external address bus of the DSP 10 to high impedance. The output of the DSP interrupt control unit 34 is the DSP 1
To the DSP 2 as a sneak signal INT2. The DSP interrupt control unit 34 receives status information as P1 and P2 from the P terminals of the DSP1 and DSP2.

A high-impedance control unit 33 controls the outputs of the buffer 1 and the buffer 2 to have a high impedance independently. These clock generation circuit 3
1, the DSP interrupt controller 34 and the high impedance controller 33 constitute the DSP controller 30 of FIG. Further, the high impedance control unit 33 is a DSP
Information is mutually exchanged with the interrupt control unit 34. The DSP 1 and the DSP 2 are provided with an external bus read routine at the time of interruption and a read completion notification routine. The operation of the apparatus configured as described above will be described below.

Description will be made with reference to the time chart of FIG. First, both DSP1 and DSP2 are in state A (main program execution state) as shown in (c) and (g). The outputs E1 and E2 of the high impedance control unit 33 are both at "0" level as shown in (b) and (f), and the address buses 23 of the buffers 1 and 2 are in a high impedance state.

At time t1, the DSP interrupt control unit 34 sends an interrupt signal I as shown in FIG.
It is assumed that NT1 has occurred. Upon receiving this interrupt signal, the high impedance control unit 33 supplies the high impedance control signal E1 to the buffer 1 and activates the address bus 23 of the buffer 1 as shown in (b). The interrupt signal INT1 enters the DSP1. DS
When P1 receives the interrupt signal INT1 in the state of state A, it shifts to state B. In state B, DSP1 first saves the main program. After that, the external bus data read subroutine is started. As a result, the address data output from the DSP 1 is stored in the memory 4 via the buffer 1.
0 is accessed. Data such as the filter coefficient output from the memory 40 is sent to the DSP 1 via the data bus 22.
Are input and read.

After reading the data, the DSP 1
Exits the subroutine. As a result, the main program is restored. After that, DSP1 (d) at time t2
As shown in, the DSP interrupt control unit 34 is notified of the data read completion signal P1. DSP1 is (c)
As shown in, when the interrupt processing is completed, the main program is again in the execution state (state A). Upon receiving the data read completion signal P1, the DSP interrupt control unit 34 outputs an interrupt signal INT2 to the DSP2, as shown in (e) this time. High impedance control unit 33
In response to the interrupt signal, the buffer applies the high impedance control signal E2 to the buffer 2 as shown in (f) to activate the address bus 23 of the buffer 2.

This time, the DSP 2 enters the state B as shown in (g), and the reading process of the data stored in the memory 40 is performed. The operation is similar to that of the DSP1. When the data reading process is completed, the DSP2
At time t3, the data read completion signal P2 is notified to the DSP interrupt control unit 34 as shown in (h). D
After that, SP2 enters the state A and executes the main program.

FIG. 12 is a flow chart showing the operation of the third embodiment of the second invention, showing the operation of the DSP. Initially the DSP is in the main program execution state (state A)
(S1). Here, if an interrupt is received (S
2) The DSP saves the main program environment that has been executed so far (S3) and executes the external bus data read routine (S4). When the reading of the external bus data is completed, the DSP restores the saved main program environment (S5), and then issues a bus data reading completion notification (S6). Then, it returns to the main program execution state (S7). Of the above steps, the state B includes steps S2 to S6.

According to this embodiment, the filter characteristics can be changed by reading the filter coefficient during the operation of the DSP 10. FIG. 13 is a block diagram showing a fourth embodiment example of the second invention. The same components as those in FIG. 10 are denoted by the same reference numerals. In this embodiment, as in the embodiment of FIG. 7, the DSP 1 and the DSP 2 are provided with the high impedance control function of the address bus, and the high impedance control section 33 is unnecessary. Therefore, DSP1, DS
The output address bus 23 of P2 directly enters the memory 40. The DSP 10 is provided with an external bus read routine at the time of interruption and a read completion notification routine in addition to the above-described routine for making the bus high impedance. In addition, the DSP interrupt control unit 34
A function capable of interrupt control of SP10 is provided.
The operation of the apparatus configured as described above will be described below.

This will be described with reference to the time chart of FIG. Initially, both DSP1 and DSP2 are in state A as shown in (b) and (e), and are executing the main program.
At this time, the DSP interrupt control unit 34 at time t1 (a)
Assume that the interrupt signal INT1 is generated as shown in FIG. Upon receiving the interrupt signal INT1, the DSP1 shifts to the state B. In state B, the main program is saved and the external address bus 23 is activated. Next, the DSP 1 activates the external bus data read subroutine.

The DSP 1 outputs address data to the address bus 23 and accesses the memory 40. Memory 40
The coefficient data stored in the corresponding address is read and read into the DSP 1 via the data bus 22.
The DSP 1 which has read the coefficient data is connected to the address bus 23.
After setting to high impedance, the data read completion signal P1 is set to DS at time t2 as shown in (c).
Notify the P interrupt control unit 34. After that, the DSP 1 returns to the main program execution state A.

Upon receipt of the data read completion notice, the DSP interrupt control unit 34, as shown in FIG.
2 is notified of the interrupt signal INT2. Upon receiving the interrupt signal INT2, the DSP2 is in the state B similarly to the above-described DSP1 and performs the reading process of the data stored in the memory 40. When the reading process is completed,
At time t3, the DSP 2 generates a data read completion signal P2 as shown in (f), and notifies the DSP interrupt control unit 34 of it. After that, the DSP 2 returns to the execution state A of the main program.

FIG. 15 is an operation flow chart showing the fourth embodiment of the second invention, showing the operation of the DSP. Initially, the DSP is in the main program execution state (S
1). Here, when the interrupt signal INT is received (S
2) The DSP saves the main program environment (S3).
Then, the external address bus 23 is set to the active state from the high impedance (S4), and the data stored in the memory 40 is read via the external bus (S5).
After reading the data, the DSP sets the external address bus 23 to the high impedance state again (S
6) The main program environment is restored (S7). afterwards,
A data read completion notification is sent to the DSP interrupt control unit 34 (S8), and the main program execution state is returned to (S8).
9). Here, the state B is from step S2 to step S8.

According to this embodiment, the filter characteristic can be read and the filter characteristic can be changed during the operation of the DSP 10. FIG. 16 is a block diagram showing a fifth embodiment of the second invention. 2 and 4 are the same as
The same reference numerals are given. In the DSP control means 30, 35 is a read state receiving / time measuring unit that receives the read state information from the DSP 1 and DSP 2, and measures time, and 36 is connected to the read state receiving / time measuring unit 35 to control information. Is a bus disconnection control unit that disconnects the address bus 23 by sending and receiving the high impedance control signals E1 and E2 to the buffers 1 and 2. The DSP 1 and the DSP 2 are provided with an external bus read state notification routine, and are provided to the read state reception / time measuring unit 35 from the S terminal thereof. The operation of the apparatus configured as described above will be described below.

This will be described with reference to the time chart of FIG. First, the DSP 1 is initially in the main program execution state (state A) as shown in (a). The DSP 1 reads the next data in the memory 40 by the program in the state B
Move to At this time, the DSP 1 notifies the read state reception / time measuring unit 35 of the state information S1 as shown in (b) indicating that the state has shifted to the state B. Upon receiving this notification, the read state reception / time measuring unit 35 starts counting of the built-in timer as shown in (c). At this time, the bus disconnection control unit 36 applies the control signal E1 to the buffer 1 to activate the buffer 1 as shown in (d). In this case, the DSP 1 finishes reading the data within the predetermined time, so the control signal E1 falls to the "0" level as shown in (d). After this, DSP1 (a)
As shown in, the state A is entered and the main program is executed.

Next, it is assumed that the DSP 2 shifts to the state B this time. The DSP 2 also reads the data in the memory 40 in the same manner, but it is assumed that the data cannot be read continuously. At this time, when the timer times out as shown in (g), the read state reception / time measuring unit 35 gives a control signal to the bus disconnection control unit 36 and gives a control signal to the buffer 2 as shown in (h). Then, the address bus 23 of the buffer 2 is disconnected. Since the high-impedance control unit 33 stores that the data could not be read even after the next data reading process of the DSP 2,
The control signal E2 is not raised to "1" level. As a result, the address bus 23 of the DSP 2 continues to be in the disconnected state.

FIG. 18 is a flow chart showing the operation of the fifth embodiment of the second invention, showing the operation of the DSP.
First, the DSP is in the state A in which the main program is being executed (S1). Next, it shifts to the state B and starts reading the external bus (S2). When the reading state is entered, the DSP notifies the reading state receiving / time measuring unit 35 of the reading state (S3). The DSP next checks whether the data reading is completed (S4). When the read state is completed, the non-read state is notified to the read state reception / time measuring unit 35 (S5). The DSP then transitions to state B where the main program is executed. In step S4, if the data reading is not completed, the data reading is performed forever, after which the timer times out and the bus is disconnected. Step S2 in the figure
~ State S is step S5.

According to this embodiment, the DSP 10 which failed in reading the filter coefficient is separated from the address bus 23, and the normal DSP 10 can continue its operation. FIG. 19 is a block diagram showing an embodiment of the third invention.
The same parts as those in FIGS. 3 and 4 are designated by the same reference numerals.
The embodiment shown in the figure is characterized in that the memory 40 is not directly accessed from the DSP1 and DSP2. DSP
In the control means 30, 37 is a control signal CTL for reading the data bus 22 into the DSP1 and DSP2.
Is connected to the external bus memory read notification unit 37, and a memory 40
It is a memory address designating unit having a function of designating an address of. The memory addressing unit 38 corresponds to the memory control unit 31 in FIG.

In this embodiment, the memory 40 stores various kinds of information as well as accommodation address identification information. FIG. 20 is a diagram showing an example of the accommodation form in the memory. The accommodation address identification information and data are stored for the address. The DSP 1 and the DSP 2 are provided with a routine for identifying the accommodation address of the memory and reading only the designated data. Explaining the operation of the device configured in this way,
It is as follows.

Description will be made with reference to the flowchart of FIG. In the bus data reception standby start state, the DSP checks whether or not the data read notification CTL1 is issued from the external bus memory read notification unit 37 (S1). The external bus memory read notification unit 37 notifies the DSP 1 of the data read notification CTL1 and gives a command to the memory address designation unit 38. As a result, the memory address designation unit 38 outputs the address data to the memory 40. The memory 40 outputs the data of the address to the data bus 22.

When there is a read notification CTL1, D
SP1 receives and reads the data on the data bus 22 (S2). Next, the DSP 1 extracts the accommodation address identification information from the read data (S3), and reads only the designated data (S4). After that, the process returns to step S1 and waits for a data read notification.

In step S1, when there is no data read notification, the bus data reception standby ends. The operation of the DSP 1 has been described above, but the operation of the DSP 2 side is also the same.

According to this embodiment, it is possible to supply the necessary filter coefficient data to the DSP 10 without accessing the memory 40 from the DSP 10.

[0057]

According to the first invention, a plurality of DSPs,
It is composed of a ROM that stores various kinds of information and gives the stored information to the plurality of DSPs, and by distributing the contents of the ROM to the plurality of DSPs, a filter coefficient and the like common to each DSP. Data can be distributed, and data such as filter coefficients can be provided to a plurality of DSPs. Also, the filter characteristics of the DSP can be changed by replacing only one ROM.

According to the second invention, a plurality of DSPs, a bus arbitration means for arbitrating the output address information of these DSPs, various information which is addressed by the output of the bus arbitration means, and the stored information is stored. A memory for giving to the plurality of DSPs, and a DSP for receiving state information of the plurality of DSPs and controlling address output states of these DSPs.
By configuring with the control means, each DSP
The data stored in the memory can be sequentially provided, and the data such as the filter coefficient can be provided to the plurality of DSPs.

In this case, a high impedance control means for setting the output of the bus arbitration means to a high impedance is provided, and the DSP control means has a function of individually controlling the hard reset of each DSP, and the high impedance control means. Is provided with a control signal to make the external address bus of the DSP high impedance, and each DSP is provided with an external bus read routine immediately after a hard reset and a read completion notification routine so that when the DSP is reset ( The filter characteristics can be changed by reading the filter coefficient from the memory when the DSP operation is initialized).

Further, the DSP control means is provided with a function capable of individually controlling the hard reset of each DSP.
The SP is provided with a function of setting the external address bus to high impedance, and the DSP is provided with a routine for setting the external address to high impedance, an external bus read routine, and a read completion notification routine.
When the SP is reset (when the DSP operation is initialized), the filter coefficient can be read from the memory to change the filter characteristic.

Further, high impedance control means for setting the output of the bus arbitration means to high impedance is provided,
The DSP control means is provided with a function of controlling an external interrupt of each DSP and a function of giving a control signal to the high impedance control means to make an external address bus of the DSP high impedance, and the DSP is provided with an external function at the time of interrupt. By providing the bus read routine and the read completion notification routine, the filter coefficient can be read and the filter characteristic can be changed during the operation of the DSP. Further, the DSP control means is provided with a function capable of controlling an external interrupt of each DSP, and the DSP is provided with a function of setting an external address bus to a high impedance.
By providing a control routine for setting the external address to high impedance, an external bus read routine at the time of interruption, and a read completion notification routine, the filter coefficient can be read and the filter characteristics can be changed during the operation of the DSP.

Further, the DSP control means is provided with the DSP.
The function to receive the read status from each DSP when reading the data on the external bus shared by the
By providing a function for measuring the external bus read time and a function for disconnecting the external address bus of the DSP, and by providing the DSP with an external bus read state notification routine,
The DSP that failed to read the filter coefficient is disconnected from the address bus, and the normal DSP 10 can continue operating.

According to the third invention, a plurality of DSPs, a memory for storing various information and accommodation address identification information and for giving the stored information to the plurality of DSPs, a control signal for the DSPs, and With the DSP control means for giving an address to the memory, the coefficient data is supplied to all of the plurality of DSPs connected on the data bus.
Alternatively, since the memory side defines whether to transmit to a specific DSP, each DSP can identify the output data of the memory to be taken into itself by the accommodation address identification information.

In this case, the DSP control means is provided with a function (memory control section) for designating a memory address, and the DSP is provided with a routine for identifying the accommodation address of the memory and reading only the designated data. Allows the DSP to be accessed without accessing the memory from the DSP.
Can supply the necessary filter coefficient data.

Thus, according to the present invention, a plurality of DS
D that can provide data such as filter coefficients to P
It is possible to provide a function expansion system for an SP-equipped device.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the first invention.

FIG. 2 is a principle block diagram of the second invention.

FIG. 3 is a principle block diagram of the third invention.

FIG. 4 is a block diagram showing a first embodiment example of the second invention.

FIG. 5 is an operation time chart showing a first embodiment example of the second invention.

FIG. 6 is a flowchart showing the operation of the first embodiment of the second invention.

FIG. 7 is a block diagram showing a second embodiment example of the second invention.

FIG. 8 is an operation time chart of the second embodiment of the second invention.

FIG. 9 is a flowchart showing the operation of the second embodiment of the second invention.

FIG. 10 is a block diagram showing a third exemplary embodiment of the second invention.

FIG. 11 is an operation time chart of the third embodiment of the second invention.

FIG. 12 is a flowchart showing the operation of the third embodiment example of the second idea.

FIG. 13 is a block diagram showing a fourth embodiment example of the second invention.

FIG. 14 is an operation time chart of the fourth embodiment of the second invention.

FIG. 15 is an operation flowchart showing a fourth embodiment example of the second invention.

FIG. 16 is a block diagram showing a fifth exemplary embodiment of the second invention.

FIG. 17 is an operation flowchart of the fifth embodiment of the second invention.

FIG. 18 is a flowchart showing the operation of the fifth exemplary embodiment of the second invention.

FIG. 19 is a block diagram showing an embodiment of a third invention.

FIG. 20 is a diagram showing an example of how the memory is accommodated.

FIG. 21 is a flow chart showing the operation of the embodiment of the third invention.

FIG. 22 is a conceptual diagram of a conventional system.

[Explanation of symbols]

 10 DSP 22 data bus 23 address bus 30 DSP control means 40 memory 50 bus arbitration means

Claims (9)

[Claims] 1. A plurality of DSPs and a ROM which stores various information and gives the stored information to the plurality of DSPs, and the contents of the ROMs are distributed to the plurality of DSPs. Function expansion system for DSP-equipped devices. 2. A plurality of DSPs, a bus arbitration unit that arbitrates output address information of these DSPs, stores various information addressed by an output of the bus arbitration unit, and gives the stored information to the plurality of DSPs. A function expansion system for a DSP-equipped device, comprising: a memory; and DSP control means for receiving the status information of the plurality of DSPs and controlling the address output status of these DSPs. 3. A high impedance control means for setting the output of the bus arbitration means to a high impedance is provided, and the DSP control means has a function capable of individually controlling a hard reset of each DSP, and the high impedance control means is controlled. 3. A function for giving a signal to make the external address bus of the DSP high impedance is provided, and each DSP is provided with an external bus read routine immediately after a hard reset and a read completion notification routine. Function expansion system for DSP-equipped devices. 4. The DSP control means is provided with a function capable of individually controlling a hard reset of each DSP, the DSP is provided with a function of setting an external address bus to a high impedance, and the DSP is provided with an external address. 3. The function expansion system for a DSP-equipped device according to claim 2, further comprising a routine for setting a high impedance, an external bus read routine, and a read completion notification routine. 5. A high impedance control means for setting the output of the bus arbitration means to a high impedance is provided, and the DSP control means is provided with a function of controlling an external interrupt of each DSP and a control signal to the high impedance control means. 3. The function of the DSP-equipped device according to claim 2, wherein the DSP has a function of setting the external address bus of the DSP to a high impedance state, and the DSP has an external bus read routine at the time of interruption and a read completion notification routine. Expansion system. 6. The DSP control means is provided with a function capable of controlling an external interrupt of each DSP, the DSP is provided with a function of setting an external address bus to a high impedance, and the DSP has a high impedance of an external address. 3. The function expansion system for a DSP-equipped device according to claim 2, further comprising: a control routine for setting the external bus, an external bus read routine at the time of interruption, and a read completion notification routine. 7. When reading data on an external bus shared by the DSP into the DSP control means, each DS
The function of receiving the read status from P, the function of measuring the external bus read time of each DSP, and the function of disconnecting the external address bus of the DSP are provided, and the DSP is provided with an external bus read status notification routine. The function expansion system for a DSP-equipped device according to claim 2. 8. A plurality of DSPs, a memory for storing various information and accommodation address identification information and giving the stored information to the plurality of DSPs, and a DSP for giving a control signal to the DSPs and giving an address to the memory. A function expansion system for a DSP-equipped device configured with a control means. 9. The DSP control means is provided with a function for designating a memory address, and the DSP is provided with a routine for identifying a storage address of the memory and reading only designated data. 8. A function expansion system for a DSP-equipped device according to item 8.