JPH0834616B2 - Synchronization method of common data in multi-processor system - Google Patents

Description

DETAILED DESCRIPTION [Outline] A status display memory that stores status display data that is common data to a main processor, a status management unit that updates the data in the memory, and a status display in response to a request from another processor. A data request processing unit that transfers the contents of the memory to the request source is provided, and is periodically activated by a plurality of other processors to request the contents of the status display memory to the main processor and to send the requests from the main processor. A status display requesting unit that updates the memory of the processor according to the contents transferred to the issuing processor is provided to match the contents of the memory of the other processors with the contents of the status display memory of the main processor. Is.

[Industrial applications]

The present invention relates to a synchronization method for always matching data common to all processors in a multiprocessor system,
In particular, in a distributed control system in which the control information of the entire system of the main processor is used by a plurality of other processors, the present invention relates to a synchronization method for matching the control information held by the memories of all the processors.

FIG. 3 shows an example of the configuration of a multiprocessor system in an exchange, which is the background of the present invention.

In the figure, the main processor MPR and the slave processors CPRi, CP
Rj is control device (CC) 300, 310, 320, memory (MM) 301,
311,321 and channel devices 302,312,322, etc.,
A distributed control method is adopted for each slave processor CPRi, CPRj.
Each slave processor CPRi, CPRj controls connection between the respective switching networks (NW) 303 and 313, and performs communication between the processors via adapters (CCA) 307, 317, 323, 324 via the master processor MPR. Each network 30
Trunk circuits (TK) 304 and 314 for interfacing with each line, subscriber circuits (not shown), etc. are connected and housed in 3,313. In FIG. 3, reference numerals 305, 306, 315, 316 and 325 represent buses.

[Conventional technology]

FIG. 4 shows a block configuration of a conventional common data synchronization system in such a multiprocessor system. This figure shows a part related to the present invention in the system configuration shown in FIG.

In FIG. 4, reference numeral 40 is a main processor MPR, 41 and 42 are distributed control processors CPRi, CPRj, and 401 are status display memories storing status display data that are common data, and 402 is a status display data of the memory 401. State management section 411, 421 for performing a process of updating based on a command from the processor MPR or state change data from another processor and transferring the updated data to another processor, 411, 421 is each processor CPRi, C
Status display memory for storing status display data in PRj,
412 and 422 receive the update data of the status display information transferred from the status management unit of the main processor, and
The status display receivers 403, 404, 413, and 423 for updating the contents of are the interprocessor communication devices.

The multiprocessor system of this conventional example is specifically applied to a telephone exchange system, and a plurality of processors CP
Ri, CPRj ... each process one part of the network,
Each network accommodates a subscriber line circuit, a station line trunk (a circuit for connecting to a public telephone station), and each processor uses a program and data in a memory provided for connection processing by the network managed by itself. Do it.

On the other hand, the main processor MPR does not directly control the network itself, but manages the operation of the other processors CPRi, CPRj ..., processes such as the man-machine interface, and manages the trunks of each network managed by each processor CPRi, CPRj. Or the blocked (in use) status is stored in memory 401.
I remember.

The status display of this memory 401 holds the status of the trunk group of the entire network, and the change of the trunk status depends on the notification from each processor CPRi, CPRj or the input from the main processor MPR (when testing the trunk etc.). Then, the state management unit 402 updates the contents of the memory 401 each time.

The content of the memory 401 of the main processor MPR is always necessary for each processor CPRi, CPRj in the processing of each network. For example, when all the trunks managed by a certain processor are in use and are in a blocked state, the trunk is further used. When the connection process occurs, the status display of the trunk group of the entire network is used to use the trunk of the network managed by another processor.

Therefore, conventionally, the data in the memory 401 of the main processor MPR is updated and the processor CPR
Inter-processor communication device 40 for sequentially updating data for i and CPRj
Forwarded via 3,413 and 404,423, which is sent to processor CP
At Ri, the status display receiving unit 412 receives and updates the status display of the memory 411, and the processor CPRj is similarly subjected to reception processing, and the content is made the same as the memory 401 of the main processor MPR.

Conventionally, as a method of this transfer, a method of receiving a response of reception confirmation from the partner each time when the processor MPR sequentially transfers to the processors CPRi and CPRj, and a method of unilaterally transferring from the processor MPR to the partner There was a way to not receive a response from.

[Problems to be solved by the invention]

As mentioned above, in the past, the main processor with the state management unit was used.
Since the MPR was used to update the contents of each status display memory by transferring it to the processor each time a data update factor of the status display memory occurred, there were the following problems.

That is, according to the transfer method of receiving a response from the other party, the transfer can be surely performed, but when the network processing is temporarily concentrated in another processor, for example, the processor CPRi, the update data is transmitted. Even if received, the process of responding to the main processor may be delayed, the update process to the memory 411 of itself may be delayed, and it takes a considerable time for the transfer, and the state display memory due to the delay of the update process. There is a drawback that the period in which the contents of 411 do not match the memory 401 of the main processor MPR becomes long.

In addition, the above method, that is, the one-way transfer has an advantage that the transfer time is shortened, but the partner processor or the communication device of the processor has a failure and cannot receive the data, or the processor cannot receive the data. If the memory update processing cannot be performed when the network processing load is excessive,
Again, there is a drawback that the contents of the memory 401 of the main processor MPR and the contents of the memories 411 and 421 of other processors do not match.

If the contents of the state display memories of the processors MPR, CPRi, and CPRj do not match, a trunk that has changed from an idle state to a blocked state, for example, has other update information including the state change in the network connection processing. If it is not updated by transferring it to the state display memory of the other processor, the trunk may treat it as an empty state, which causes a problem that the state display on the processors CPRi and CPRj does not match the actual state. there were.

[Means for solving problems]

According to the present invention, each processor individually and periodically generates a transfer request for the data in the status display memory of the main processor via the inter-processor communication device, so that the transfer data from the main processor is received and the data in the respective processors is received. The above problem is solved by updating the status display memory of.

 The principle structure of the present invention is shown in FIG.

In FIG. 1, 10 is a main processor MPR, 11, 12 are processors CPRi, CPRj, 101, 111, 121 are status display memories, and 102 is a storage data of the status display memory 101 when receiving a status display data request sent from each processor. A data request processing unit for reading and transferring the data to the request source, 103 is a memory 101 corresponding to a cause of the status display.
The state management units 112 and 122 for updating the contents of the memory generate a request signal for the state display data in response to the input of the activation signal which is periodically generated, receive the data sent from the main processor MPR, and receive the respective memory 11
A state display requesting unit that updates the contents of 1,121, 104, 105, 114, and 124 are interprocessor communication devices, and 113 and 123 are periodic activation signals.

[Action]

In the main processor MPR, when the status management unit 103 receives the status change information of the trunk usage status from the other processors CPRi and CPRj and the status change information from the operation input device (not shown) connected to the main processor, each time. The corresponding status display data in the memory 101 is updated.

On the other hand, in the processors CPRi and CPRj, the start signal 1
13,123 occurs periodically. If the signal 113 is generated, the code for activating the status display requesting unit 112 and requesting the status display data in response to the signal 113 is transmitted via the interprocessor communication device 114, the bus, and the interprocessor communication device 104. It is transmitted to the data request processing unit 102 of the processor MPR. Upon receiving this request, the data request processing unit 102 accesses the status display memory, sequentially reads the contents, and transfers them to the processor CPRi via the interprocessor communication devices 104 and 114.

When the status display requesting unit 112 of the processor CPRi receives the transferred data of the memory 101, the content of the status display memory 111 is updated by the received data.

The data in the status display memory 121 in the processor CPRj is also updated by the periodic start signal 123 in the same operation as the processor CPRi.

〔Example〕

FIG. 2 shows a control flow chart of an embodiment in which the present invention is applied to a multiprocessor system of a distributed control type electronic exchange.

An embodiment of the present invention will be described below with reference to FIG. 2 while referring to the configuration of FIG.

First, regarding the data update of the status display memory 101 (FIG. 1) of the trunk group blockage of the main processor MPR, the status management unit 103 (FIG. 1) of the trunk group blockage etc. of the main processor MPR uses interprocessor communication. When the state change information including the address is generated due to the state change of another processor, for example, CPRi, via the devices 104 and 105 (FIG. 1), the interprocessor communication device 114, Bus / processor communication device 104
When it reaches the control unit (CC 320 in FIG. 3) via the control unit and detects that it is the trunk state information (S ₁ , S ₂ ), it notifies the state management unit 103 such as trunk group blockage and the state management. Part 103
Is thereby access to the control circuit of the state display memory 101, data of the next change information is updated is supplied to the memory 101 via the bus with the address (S _3).

The trunk status change information from the maintenance input device such as also given to the state management unit 103, similarly update of data is performed _{(S 1, S 2, S} 3).

Next, the data update of the status display memory 111 (FIG. 1) for blocking the trunk group of the processor CPRi will be described with reference to FIG.

The status display request unit 112 of the processor CPRi is periodically activated 113, and a control code representing a request for status display data is generated.
Thus via the inter-processor communication unit 114 or the like interrupt is generated and transferred to the main processor MPR (S _20).

When the main processor MPR detects the control code through the channel control unit, it activates the data request processing unit 102 (S
₁₀ ).

As a result, the data request processing unit 102 sends a control signal to the status display memory 101 for blocking the trunk group, performs read driving, sequentially supplies addresses to the bus for reading, and inputs them to the channel control unit (S ₁₁ ). .

From the channel control unit, read data interprocessor communication device 104, a bus is transferred to the channel control unit of CPRi via the inter-processor communication unit 114 (S _12).

Upon receiving this data, the status display requesting unit 112 sends a control signal to the status display memory 111 such as trunk group blockage, and sequentially receives the received data.
Control to write to (S ₂₁ , S ₂₃ ).

If the status display cannot be received due to a communication control error when the request from the status display requesting unit 112 occurs (S
₂₂ ) Stop the update process for that cycle and perform the update process again in the next cycle.

According to this embodiment, the contents of the status display memory such as the trunk group blockage of the processors CPRi and CPRj are the main processor MPR.
The contents of the status display memory do not remain inconsistent with each other, and it is possible to prevent the circuit control unit from catching a line that cannot be actually used or conversely determining that a usable line is unusable.

〔The invention's effect〕

According to the present invention, the main processor MPR only updates the memory on its own processor when a status update factor occurs, and the data transfer processing to the other processors CPRi and CPRj becomes unnecessary.

As a result, the conventional processing when a data update factor occurs does not require countermeasures for communication control errors related to data transfer and conflict measures when a number of status change factors occur continuously, and simplification of the process can be achieved. Further, there is an effect that data loss and inversion related to communication control from the main processor MPR to the processors CPRi and CPRj are eliminated.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention, FIG. 2 is a diagram showing a control flow of an embodiment of the present invention, FIG. 3 is a diagram showing a configuration example of a multiprocessor system according to the present invention, and FIG. The figure is a diagram showing a configuration of a conventional example. In FIG. 1, 10: main processor MPR 11, 12: processor CPRi, CPRj 101, 111, 121: status display memory 102: data request processing unit 103: status management unit 112, 122: status display request unit 104, 105, 114, 124: interprocessor communication device

Claims (1)

[Claims] 1. A main processor and a plurality of other processors are individually coupled by an inter-processor communication device,
A memory including a state management unit that updates common data in the main processor and a state display memory that stores state display data that is common data, and a memory that holds the contents corresponding to the state display memory in each of the other processors. In a multiprocessor system including: a data request processing unit that transfers the contents of the status display memory to the main processor in response to a request from another processor, and is periodically activated by the plurality of other processors. The main processor to request the contents of the status display memory and update the memory of the processor with the contents transferred from the main processor to the processor that issued the request. Of the contents of the memory of the other processors and the status display memory of the main processor A common data synchronization method in a multiprocessor system, which is characterized by matching the contents.