JPS594053B2 - Failure notification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure information notification method for a multiprocessor system.

More specifically, the present invention relates to a failure notification method for a multiprocessor system in which a plurality of processors and one or more peripheral control devices are connected via a common bus.

When transmitting and receiving information between processors or between a processor and a peripheral control device in a configuration where each processor and peripheral control device are connected to a common bus, as in this system, each processor and peripheral control device must have a unique device address. Communication is performed with the target device using the assigned device address as destination information.

In a multiprocessor system including this system, one of the multiple processors controls the system configuration and handles faults and manages the entire system.Fault information from each processor and peripheral control device is sent to the processor that manages the system. (This will be called the master CC) will collect the data. In conventional systems, the fault information of each processor and peripheral control device is stored either by the master CC periodically receiving device status information of each processor peripheral control device, or by each processor peripheral control device transmitting its own fault information to the master CC.
C was notified. The former has the problem that the master CP periodically acquires device status information, resulting in a time delay from the occurrence of a failure to its detection, prolonging the processing or service suspension. There is a problem in that the overhead of the master CC increases, resulting in a decrease in processing performance.

The latter requires the device address of the master CC to be fixed in order to notify the master CC of a failure from each processor peripheral control device, and if another processor replaces the master CC due to a failure of the master CC itself, the processor side The device address must be changed or the processor peripheral controller must be notified of the device address of the new master CC.

Changing the device address of the processor has the problem of complicating control because the processing that has been continuing must be temporarily interrupted.

An object of the present invention is to solve the above-mentioned problems when each processor or peripheral control device detects a failure.
This provides a failure notification method that allows failure information to be sent by specifying a failure notification address.

To achieve the above object, the present invention provides a system in which a plurality of processors and one or more peripheral control devices are connected to the same bus, and each of the processors and peripheral control devices has a unique device address. In a system in which communication is performed between processors or between processors and peripheral control devices by specifying addresses, an address that does not overlap with the above device addresses is used as the fault notification address, and any one of the plurality of processors It has the above-mentioned unique device address and fault notification address, and when each of the above processors and peripheral control devices detects a fault within its own device, it sends fault information to the above bus by specifying the fault notification address. The present invention is characterized in that a processor having a failure notification address among the processors receives the failure information.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a multiprocessor system for electronic switching to which the present invention is applied, in which n central controllers (
CC#1 to CC#n) 1, individual memories (IM#1 to IM#n) 2 connected corresponding to each CC, common memory CM3 accessed from each CC, and m peripheral control units (PU#
1 to PU#m) 4 and the network (NW#1 to NW#m) 5 connected to each PU, a common bus BUS 6 that connects each CC and PU, and a bus control device BCTL 7 that controls common bus access. configured.

This system is applied, for example, to relay switching in a telephone network, and N
W5 has a switch that connects the line and trunks that send and receive signals on the line, and CCl and PU4 select the trunk, specify switching, connect, disconnect, release, etc. based on the line status and dial information. control. C.C.
1 and PU4 are connected by BUS6, and line status information, control information, etc. are communicated.

IM2 is a memory having programs and data for each CCl, and CM3 stores data common to CCls and programs that are used less frequently. FIG. 2 shows the connection configuration of the signal lines of the common bus BUS6 to which the present invention is applied.
#1 to #n are bus use request signals from each CC, COK
#1 to #n are bus use 0K signals and PRQs to each CC
#1 to #m are bus use request signals from each PU, POK#
1 to #m are bus use 0K signals to each PU, ADT is
The address information sending timing signal, DTT, is a data sending timing signal.

The BUS is composed of a plurality of information lines and is used for sending and receiving address information and data. FIG. 3 shows a time chart of the above signal line. When there is a bus use request from CC#I, #j1 and PU#K, #T4, CRQ
#I, CRQ#J, PRQ#K, and PRQ#t become 0N, and the BCTL 7 selects these signals with priority, selects only one, and sends the bus use 0K signal COK#i.

The BCTL 7 sends out timing signals for the takeover ADT and DTT.

CC#i that received COK#i sets CRQ#i to 0FF.
and sends device address information indicating the destination onto BUS6 at the timing of ADT, and sends device address information indicating the destination onto BUS6 at the timing of DTT.
Send data upwards. CCl and PU4 that did not receive the bus use 0K signal will use BUS6 at the ADT timing.
Compare the above information with your own device address to determine if the access is for you.

FIG. 4 shows an embodiment of the bus control device BCTL7 according to the present invention, and the CRQ and PRQ signals from each CCsPU are first input to a priority selection circuit 71 that performs priority selection.

The output signal of the priority selection circuit 71 is sent to a bus 0K signal sending circuit 72 that sends COK and POK signals, as well as an address sending timing signal ADT and a data sending timing signal DT.
It is applied to a timing circuit 73 that creates T. In addition to the above-mentioned functions, the timing circuit 73 also creates timing for transmitting COK and POK signals. FIG. 5 is a block diagram showing the configuration of the CCl, and each CC is composed of a control unit CPU11 and a bus interface control unit 1NT12.

Note that the configuration of PU4 is also substantially the same.

FIG. 6 is a concrete example of a failure notification system in a common bus according to the present invention.

This shows an example of the configuration of INF12. In this figure, CC is taken as an example.

(Each CC and PU has the INF shown in Figure 6.) During normal communication, when INFl2 receives a communication request from CPUll, it sets RQFF6l and sets CRQ#i to 0N.
and issues a bus request to BCTL7.

Upon receiving COK#1 from BCTL7, it sends an 0K signal to CPUll, notifying that the request is accepted,
Reset RQFF6l, then receive ADT, send the communication destination device address to BUS6, receive DTT,
Sends the sending data to BUS. In addition, if ADT is received without receiving COK#i, the device address match circuit 63 of this 1NF compares the BUS information (address information) with its own device address, sends a device address match signal to the CPU, and sends the device address match signal to the CPU. Notify the reception of DTT.
Receives data on the BUS using signals and sends the received data to the CPU.

Furthermore, this 1NF includes a failure notification address generation circuit 62 and a failure notification address matching circuit 64.

When receiving ERROR signal from CPUll, RQFF6l
and sends a bus request to BCTL7, COK#I
, generates a failure notification address with the ADT signal, and connects BUS6.
and sends fault information to BUS6 using a DTT signal.

On the other hand, one CC among the CCs becomes the master CC and notifies the master CC signal to the INF, and the INF
At the time of reception, if a fault notification is detected by the fault notification address matching circuit 64 and there is a master CC signal, a fault notification address match signal is sent to the CPU to notify reception of the fault information, and the DT
Fault information is sent to the CPU using the T signal.

As explained above, according to the present invention, in a multiprocessor system using a common bus, notification of fault information can be realized with a relatively simple circuit, and the time from the occurrence of a fault to its detection can be shortened. It is possible and highly effective.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of a multiprocessor system for an electronic exchange to which the present invention is applied, FIG. 2 is a connection configuration diagram of a common bus signal line according to the present invention, and FIG. 3 is a time chart of FIG. FIG. 4 shows an embodiment of a bus control device according to the present invention, FIG. 5 shows a block diagram of the configuration of a CC according to the present invention, and FIG. 6 shows an embodiment of a bus interface control unit according to the present invention. 1...Central control unit, 2...Individual memory, 3...Common memory, 4...Peripheral control device, 5...Net Work, 6...
Common bus person 7...Bus control device, 12...
...Bus interface control unit, 61...Request flip-flop, 62...Fault notification address generation circuit, 63...Device address matching circuit, 64... ...address matching circuit for fault notification.

Claims (1)

[Claims] 1. A plurality of processors and one or more peripheral control devices are connected to the same bus, each of the processors and peripheral control devices has a unique device address, and the processors and the processor are connected by specifying the device address on the bus. In a system that performs communication between a processor and a peripheral control device, an address that does not overlap with the device address above is used as a fault notification address, and any one of the plurality of processors communicates with the unique device address above. When each of the above-mentioned processors and peripheral control devices detect a fault within their own device, they specify the fault notification address to the bus and send fault information, and A fault notification method for a multiprocessor system, characterized in that a processor having an address receives the fault information.