JPH0546576A - Mehtod and device for communication control for parallel computer - Google Patents

Abstract

PURPOSE:To increase the use efficiency of a network and the use efficiency of the whole system as to the parallel computer formed by connecting plural processors by the network. CONSTITUTION:The decentralized memory type parallel computer constituted by mutually connecting communication control means (C0...Cn) of respective processor elements P0...Pn by the network NW monitors the writing of data from the processors to memories to detect writing to a specific area as data to be sent, adds a transfer destination identification code and a transfer destination address which are found previously to the data to be sent, and sends the data to the reception-side processor element which is determined according to the transfer destination identification code MK, thereby storing the sent data in the memory of the reception-side processor element according to the transfer destination address. Consequently, part of the data can be divided and send to other processor elements without waiting for all data to be processed, thereby performing parallel computation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to communication control between processor elements in a distributed memory type parallel computer connected via a network.

[0002]

2. Description of the Related Art When performing a numerical calculation or the like on a distributed memory type parallel computer in which a processor element having a processor and a memory is connected by a communication network, data such as an array is divided into the processor elements for the calculation.

Since the method of division depends on the contents of the calculation, it is necessary to change the method of division during the calculation.
At that time, the data is exchanged between the processors. For the data exchange, the data to be divided is collectively calculated, and then the data is collectively collected for each transfer destination computer and sent through the network.

[0004]

When sending data as described above, since the calculation of all data is completed and the data is distributed to each destination processor, the data communication is performed. The network is unused and the effectiveness of using the network is reduced.

The present invention has been made in view of the above points,
The purpose of the present invention is to make it possible to acquire the data before the calculation of all the data and send it to a predetermined processor, improve the efficiency of use of the network, and improve the efficiency of use of the entire system.

[0006]

A communication control method for a parallel computer according to the present invention is, as shown in FIGS. 1 and 2, a processor (CPU), a memory (MM), and a communication control means (C0).
..Cn) and a plurality of processor elements (P0..Pn) respectively, and the communication control means (C0..Cn) of each of the processor elements P0..Pn are mutually connected by a network (NW). In the distributed memory type parallel computer configured, data is divided into each processor element and processed in the following procedure.

Step (a): The writing of data from the processor (CPU) to the memory (MM) is monitored and the writing to a specific area is detected as transmission data. Step (b): Then, the transfer destination identification code and the transfer destination address which have been obtained in advance are added to the transmission data.

Step (c): Next, the data for transmission is transmitted to the receiving side processor element determined according to the transfer destination identification code (MK). Step (d): Then, the transmission data is stored in the memory (MM) of the receiving side processor element according to the transfer destination address.

[0009]

As described above, according to the present invention, the processor (CP
Since the writing of data from U) to the memory (MM) is monitored and writing to a specific area is detected as transmission data, a part of the data is divided without waiting for all the data to be processed. can do.

The divided data is transmitted to another processor element. Therefore, one data group can be divided into a plurality of pieces, and the divided data pieces can be calculated in parallel by each processor element.

For example, it is used when the array data is divided into each column, the divided data of each column is transmitted to each of a plurality of processors (CPU), and each processor (CPU) calculates each column. it can.

The method of the present invention can be realized by the following device. That is, according to the present invention, as shown in the principle diagram of FIG. 2, a plurality of processor elements P0 ... Pn each having a processor (CPU), a memory (MM), and communication control means (C0 ... Cn). And a communication control means (C0 ... Cn) for each of the processor elements P0.
In a distributed memory type parallel computer configured by connecting each other via a network (NW), as shown in FIG.
The communication control means (C0 ... Cn) is composed of the following means.

A transmission data detection means (WC) for detecting data corresponding to a predetermined address among the data generated by the processor (CPU) and recorded in the memory (MM).

Transfer destination identification code generation means (RI-M) for generating an identification code (MK) of the transfer destination processor element of the transmission data. Memory in the transfer destination processor element (M
Transfer destination address generation means (RA-M) for generating the data storage address of M).

Transmission data detected by the transmission data detection means (WC), transfer destination identification code generation means (RI-
The identification code (MK) generated in M) and the address generated in the transfer destination address generation means (RA-M) are transmitted to the network (NW) (NC-0).

Receiving means (NC-1) for receiving the transmission data, the identification code (MK), and the transmission data sent from another processor element. A memory writing unit (MW) that writes the data received by the receiving unit (NC-1) into the memory (MM) according to the address information that is also received.

That is, in the transfer destination identification code generating means (RI-M), the transfer destination identification code (MK) is updated every time the transmission data is transmitted, the identification code updating means (A).
DD1) is provided and the transfer destination address generating means (RA-
In M), transfer destination address updating means (ADD0) for updating the transfer destination address each time the transmission data is transmitted is provided.

In the present invention, n with 2 processor elements is used.
If there is a multiple of the transfer destination identification code (MK) and the bit width of the transfer destination identification code (MK) is set to the minimum width that can express the number of the transfer destination identification code (MK), it is easy to update the transfer destination identification code (MK).

The transmission data includes a transfer destination identification code (M
K) and the transfer destination address are added and transmitted, but it is possible to transmit the data for transmission, the transfer destination identification code (MK), and the transfer destination address in the form of a packet (N).
This is preferable in suppressing the amount of data flowing through W) and improving communication efficiency.

That is, the transmission data detecting means (W
The data for transmission detected in C), the identification code (MK) generated by the transfer destination identification code generation means (RI-M), and the address generated by the transfer destination address generation means (RA-M) are packetized. A packet generating means (PC) is provided, and the transmitting means (NC-0) is a packet generating means (PC).
Packet is sent to the network (NW), and the receiving means (NC-1) sends the packet to the network (NW).
A packet decomposing means (PD) for decomposing the packet received by the receiving means (NC-1) is provided in the memory writing means (MW) so as to receive a packet sent from another processor element via W). The data obtained by disassembling the packet by the packet disassembling means (PD) is written in the memory (MM) according to the address information obtained in the same manner.

Further, it is possible that the transfer destination processor element does not include its own processor element if necessary. That is, in the identification code updating means (ADD1), the updated identification code (MK)
Indicates a self-processor element, the self-designation avoiding means (10) for further updating the update identification code (MK).
0) is provided.

In the transfer destination processor element, the write position at the transfer destination can be changed by adding an offset value to the write address. That is, the memory writing means (MW) is provided with an offset adding means (OADD) that adds an offset value to the received write address.

When the transfer data is transferred one after another,
When the transfer data having the same transfer destination identification code (MK) continues, if the continuous transfer data are collectively transmitted in one packet, the communication efficiency becomes higher.
That is, when transfer data having the same transfer destination identification code (MK) continues to the packet generation means (PC), continuous transfer data and addresses together with the transfer destination identification code (MK) are collected into one packet. Provide a continuous packetization function.

The hardware can be miniaturized by not providing an actual memory in a specific area in which the transfer data is to be written, but by using the area exclusively for transfer to another processor (CPU).
In addition, when writing transfer data to the transfer destination memory (MM) in order from the lowest address,
Communication control means (C0 ... Cn) is the destination processor (C
PU) and the hardware for calculating the address of the other party are smaller. That is, the memory writing means (MW)
Further, a write control means (WM) for writing transfer data to the transfer destination memory (MM) sequentially from the lowest address is provided.

By monitoring the memory writing of the data transferred from the processor (CPU) as described above, the transferred data can be sent to the network (NW) immediately after the calculation is completed.

In the present invention, the communication control means (C0 ... C
n) may be realized by the processor (CPU).

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. <Embodiment 1> FIG. 4 is a block diagram of an embodiment, in which an address bus and a data bus are respectively provided with central processing means (processor (CPU)), memory (MM), and communication control means (C).
0 ... Cn) are connected to form a processor element. Multiple processor elements are provided,
Communication control means (C0 ... Cn) of each processor element
They are connected to each other via a network (NW).

The communication control means (C0 ... Cn) has the following configuration. A window comparator (WC) that determines whether writing from the processor (CPU) to the memory (MM) is writing to the data detection area secured for transfer to another processor (CPU).

A data holding register (RD) that temporarily holds the data in the data detection area. An address generation circuit (AG) that generates a transfer destination identification code (MK) and a transfer destination address.

A packet generation circuit (P that packetizes the transfer destination identification code (MK), transfer destination address, and data
C). A transmission network control circuit (NC-0) for transmitting the generated packet.

A receiving network control circuit (NC-1) for receiving a packet sent from another processor element. A memory write circuit (M that decomposes the received packet and writes the sent data to the specified address
W).

Each section will be described below. {Window Comparator (WC)} The window comparator (WC) has the following configuration.

Data detection area setting means including an upper limit address register (RHO) for storing the upper limit address of data to be detected and a lower limit address register (RLO) for storing the lower limit address of data to be detected (DE).

The write address of the data output from the processor (CPU) is the data detection area setting means (D
E) determining means (J) for determining whether the area is within the area set
U).

This judging means (JU) is a processor (C
Upper limit address comparison circuit (CH) for determining whether the write address of the data output from PU) is less than the upper limit address stored in the upper limit address register (RHO)
O), a lower limit address comparison circuit (CLO) for determining whether the write address of data output from the processor (CPU) is equal to or higher than the lower limit address stored in the lower limit address register (RLO), and an upper limit. An AND circuit (AND) as a determination result output means for receiving the outputs of the address comparison circuit (CHO) and the lower limit address comparison circuit (CLO).
It has and.

The processor (CPU) processes the data input from the input means (not shown), calculates the write address, outputs the write address to the address bus, and outputs the data to the data bus. The memory (MM) stores data according to the write address.

At that time, the window comparator (WC)
Each time the write address calculated by the processor (CPU) is output to the address bus, it is determined whether or not it is in the data detection area. If the address is in the data detection area, the data at that time is written. Holding register (R
Store in D) and instruct to transfer the packet.

That is, the upper limit address of the data to be detected is registered in the upper limit address register (RHO), and the lower limit address of the data to be detected is registered in the lower limit address register (RLO). The upper limit address and the lower limit address are determined by what kind of data is handled by the parallel computer.

Since the write address of the data determined by the processor (CPU) is transmitted to the data bus, the upper limit address comparison circuit (CHO) and the lower limit address comparison circuit (CLO) respectively obtain the write address.

The upper limit address comparison circuit (CHO) compares the upper limit address stored in the upper limit address register (RHO) with the write address, and the write address is the upper limit address stored in the upper limit address register (RHO). When it is less than 1, "1" is output.

The lower limit address comparison circuit (CLO) compares the lower limit address stored in the lower limit address register (RLO) with the write address, and the write address of the lower limit address stored in the lower limit address register (RLO). When it is equal to or more than the address, "1" is output.

When the AND circuit (AND) receives the output "1" from the upper limit address comparison circuit (CHO) and the lower limit address comparison circuit (CLO), the data output from the processor (CPU) is output. , "1" is output as a determination signal indicating that the data is in the data detection area, and the address generation circuit (AG) and the packet generation circuit (PC) are activated. {Data holding register (RD)} The data holding register (RD) is connected between the data bus and the packet generation circuit (PC) and is used for data detection among the data sent from the processor (CPU) to the data bus. Holds the data in the area temporarily. {Address generation circuit (AG)} Address generation circuit (A
G) is a transfer destination identification code register (RI), transfer destination address register (RA), identification code update information memory (MD)
I), address update information memory (MDA), identification code update adder circuit (ADD1), address update adder circuit (ADD0), update control counter (CC), and update control table (RCC).

The transfer destination identification code register (RI) stores a transfer destination identification code (MK) for specifying a transfer destination processor element. The data transfer destination identification code (MK) is transferred to the packet generation circuit (PC) during data transfer. ) And the identification code update addition circuit (ADD1).

In the identification code update information memory (MDI),
Information for updating the transfer destination identification code (MK) is registered.
The identification code updating adder circuit (ADD1) sequentially updates the identification code (MK) to be designated. The identification code (MK) received from the transfer destination identification code register (RI)
The update information in the identification code update information memory (MDI) is added to generate a new identification code (MK), which is sent to the transfer destination identification code register (RI).

The transfer destination address register (RA) stores the write address of the memory (MM) at the transfer destination, and at the time of data transfer, transmits the transfer destination address to the packet generation circuit (PC) and updates the address. To the adder circuit (ADD0).

In the address update information memory (MDA),
Information for updating the transfer destination address is registered. The address update adder circuit (ADD0) sequentially updates the write address to be designated, and updates the transfer destination address received from the transfer destination address register (RA) registered in the address update information memory (MDA). A new transfer destination address is generated by adding the use information to the transfer destination address register (RA).

The update control counter (CC) is preset with an initial value "m", and is decremented by "1" from the initial value "m" each time data is transferred. The register control table (RCC) is a register that stores an initial value “m” to be given to the update control counter (CC) when the update control counter (CC) becomes “0”.

Then, at the time of data transfer, the transfer destination identification code (MK) is transmitted from the transfer destination identification code register (RI) to the packet generation circuit (PC) and is also transmitted to the identification code update addition circuit (ADD1). ..

Similarly, the transfer destination address register (RA)
From the transfer destination address to the packet generation circuit (PC) and the address update addition circuit (ADD0).

Further, at this time, the update control counter (C
C) is subtracted by "1". When the update control counter (CC) is not "0" as a result of the subtraction, the update registered in the identification code update information memory (MDI) in the transfer destination identification code (MK) by the identification code update addition circuit (ADD1). Information is added. As a result, a new identification code (MK) is generated. The new identification code (MK) is stored in the transfer destination identification code register (RI).

Similarly, an address updating adder circuit (ADD
0) to the transfer destination address as the address update information memory (MD
The update information registered in A) is added. As a result, a new transfer destination address is generated. The new transfer destination address is stored in the transfer destination address holding unit (RA).

When the update control counter (CC) is "0", the update control counter (CC) is given the initial value "m" registered in the update control control table (RCC).
The contents of the transfer destination address register (RA) and the transfer destination identification code register (RI) are updated by the procedure shown in the flowchart of FIG. 5 every time one packet is sent. In FIG. 5, the update procedure is performed when n = 3 in FIG. 4, but when n is different, update can be performed by the same procedure. Here, n is an arbitrary number irrelevant to the number of processors (CPU).

Explaining the flowchart for updating the address shown in FIG. 5, first, the value of the update control counter (CC-1) is decremented and decremented by "1" each time data is transferred, that is, packet is transferred. (Step 1
01).

Next, the update control counter (CC-1)
Is determined to be 0 (step 102), 0
If not, the value of the identification code update information memory (MDI-0) is added to the value of the transfer destination identification code register (RI) and the value of the transfer destination address register (RA) is added to the address update information memory MDA-0. Add the values (step 10
3) The address update is completed.

At step 102, the update control counter (C
If the value of C-1) is 0, the process proceeds to step 104, the value of the register control table (RCC-1) is copied to the update control counter (CC-1) and initialized, and the register control table (RC The value of RCC-2) is decremented and "1" is subtracted.

Next, the update control counter (CC-2)
Is determined to be 0 (step 105), 0
If not, the value of the identification code update information memory (MDI-1) is added to the value of the transfer destination identification code register (RI) and the value of the address update information memory MDA-1 is added to the value of the transfer destination address register (RA). Is added (step 10
6) The address update is completed.

At step 105, the update control counter (C
If the value of C-2) is 0, the process proceeds to step 107, the value of the register control table (RCC-2) is copied to the update control counter (CC-2) for initialization, and the register control table (CC The value of RCC-3) is decremented and "1" is subtracted.

Next, the update control counter (CC-3)
Is determined to be 0 (step 108), 0
If not, the value of the identification code update information memory (MDI-2) is added to the value of the transfer destination identification code register (RI), and the value of the address update information memory MDA-2 is added to the value of the transfer destination address register (RA). Is added (step 10
9) The address update is completed.

At step 108, the update control counter (C
If the value of C-3) is 0, the process proceeds to step 110, the value of the register control table (RCC-3) is copied to the update control counter (CC-3) for initialization, and the transfer destination identification code is also set. The value of the identification code update information memory MDI-3 is added to the value of the register (RI), and the address update information memory MDA- is added to the value of the transfer destination address register (RA).
The value of 3 is added and the address update is completed.

In this embodiment, the number of processors is 2
The number is limited to the n-th power (n is a natural number). Transfer destination identification code register (RI) and identification code update addition circuit (A
The bit width of DD1) is the minimum width that can express the number of vehicles. As a result, the transfer destination identification code register (RI) can be prevented from having a value other than the processor number at the time of updating. {Packet generation circuit (PC)} Packet generation circuit (P
In response to the instruction from the window comparator (WC), C) transfers the data of the transfer destination identification code register (RI), the transfer destination address register (RA) and the data holding register (RD) in the address generation circuit (AG). The packets are arranged in order and sent to the network control circuit (NC-0). {Network control circuit (NC-0)} The network control circuit (NC-0) sends this packet to the partner processor (CP) based on the transfer destination identification code (MK) of this packet.
Send to U). That is, it has a decoding means for the transfer destination identification code (MK) and a packet transmission means (NC-0).

The network control circuit (NC-0)
No transfer means identification code (MK) decoding means is provided in the network (NW), a relay exchange is installed, the transfer destination identification code (MK) is decrypted by this relay exchange, and the packet is transferred to the designated transfer destination. It may be transferred.

Note that the network (N
As an example of W), a network that specifies a destination identifier in advance of data transfer can be used. {Reception network control circuit (NC-1)} The reception network control circuit (NC-1) receives a packet sent from another processor element. {Memory write circuit (MW)} Memory write circuit (MW)
Is a packet decomposing circuit PD for decomposing a received packet to extract a write address and data, an address writing circuit WA for accumulating the obtained write address, and a data writing circuit WD for accumulating the obtained data. Have and.

The memory writing circuit (MW) issues a bus acquisition request to acquire the address bus and the data bus. The address writing circuit WA and the data writing circuit WD address the addresses via the address bus and the data bus, respectively. The data stored in the data write circuit WD is written in the memory (MM) according to the write address stored in the write circuit WA. {Form of Bus} In this embodiment, the data bus and the address bus are separated from each other, but the address and the data may be sent by one bus in a time division manner. <Operation Example of First Embodiment> The operation of the apparatus of the first embodiment will be described with reference to an example when parameters are set as shown in FIGS.

FIG. 6 is common to all the processors, and the register management table (RCC) of the address generation circuit (AG), the address update information memory MDA, and the identification code update information memory (M
It is a value set in DI). Figure 7 shows each processor (CP
U) is the set value. “2032” is registered in the upper limit address register (RHO) and “200” is registered in the lower limit address register (RLO) in common to each processor (CPU).
"0" is registered, and "1" is registered in the transfer destination identification code register (RI). “1000” is set in the transfer destination write address register (RA) of the processor (0), and “1” is set in the transfer destination write address register (RA) of the processor (1).
004 ”,“ 1008 ”is registered in the transfer destination write address register (RA) of the processor (2), and“ 1012 ”is registered in the transfer destination write address register (RA) of the processor (3).

First, the data (A0, B0, C0, D0, E0, F0, G0, H generated by the processor (0) is used.
0) is sent to the memory (MM), the respective addresses are acquired by the upper limit address comparison circuit (CHO) and the lower limit address comparison circuit (CLO).

The upper limit address comparison circuit (CHO) stores the upper limit address “2032” stored in the upper limit address register (RHO) and the upper limit “200” of the write address of each data.
4, 2008, 2012, 2012, 2020, 202
4, 2028, 2032 ". The upper limit of the write address of each data is the upper limit address register (R
Since it is less than the upper limit address “2032” stored in HO), the upper limit address comparison circuit (CHO) outputs “1” each time each data is acquired.

The lower limit address comparison circuit (CLO) has a lower limit address “2000” stored in the lower limit address register (RLO) and a lower limit “20” of a write address of each data.
00, 2004, 2008, 2012, 2016, 20
20, 2024, 2028 ". The lower limit of the write address of each data is the lower limit address register (RLO)
Since the lower limit address "2000" stored in is lower than or equal to "2000", the lower limit address comparison circuit (CLO) outputs "1" each time each data is acquired.

The AND circuit (AND) outputs "1" when it receives outputs "1" from the upper limit address comparison circuit (CHO) and the lower limit address comparison circuit (CLO), respectively, and the address generation circuit. (AG) and packet generation circuit (PC) are activated.

By setting in this way, the data of "2000 to 2032" (all addresses are expressed in decimal) of each processor is set to "1000 to 103" as shown in FIG.
You can change the layout to "2" and write.

The operation of the control circuit of the processor (0) at this time is shown in FIG. 8 shows the relationship between FIG. 8 and FIG. 9, A0 consists of the data of “D1 to D4” stored in the addresses “2000 to 2003”, and B0 is stored in the address “2004 to 2007”. Was done "D
5 to D8 ”data, and D0 is the address“ 2012
~ 2015 "stored in" D13 to D16 "
E0 is the address "2016-201".
It is assumed to be composed of data of "D17 to D20" stored in "9".

First, as is apparent from FIG. 7, in the processor (0), (RI) is set to "1", (RA) is set to "1000", and the upper limit address register (RHO) is set to "1". 2032 "is set, and" 2000 "is set in the lower limit address register (RLO).
Therefore, when the data D1 of A0 is sent, the address "2000" of D1 is changed to the window comparator (WC).
The upper limit address comparison circuit (CHO) and the lower limit address comparison circuit (CLO) are respectively captured and compared with the upper limit address “2032” and the lower limit address “2000”.

Since the D1 address is "2000" between "2032" and "2000", the AND circuit (AND) outputs "1" to activate the address generation circuit (AG). , The identification code “1” (indicating the processor (1)), and the write address (RA) value “100”.
0 ”and data D1 from the data holding register (RD)
And are packetized and sent to the network control circuit (NC-0) in the part of the figure. That is, the data D1 is sent to "1000" in the memory (MM) of the processor (1).
Then, (CC-1) is decremented according to step 101 of FIG. 5 as shown in FIG.
Since the value of 1) does not become 0, the value "0" of MDI-0 is added to the value "1" of the transfer destination identification code register (RI),
MD in the value "1000" of the transfer destination address register (RA)
The value "1" of A-0 is added, and as a result, (RI) =
“1” and (RA) = “1001”.

Similarly, the data D2 of the address "2001" is transferred to the address "1001" of the processor (1), the value of (CC-1) is decremented to "2", and (RI) = "1". , (RA) = “1002” is updated. The data D3 is the address "1" of the processor (1).
002 ”, the value of (CC-1) is decremented to“ 1 ”, (RI) =“ 1 ”, (RA) =“ 100 ”.
3 ”is updated.

Next, when the data D4 is transferred to the address "1003" of the processor (1), the value of (CC-1) is decremented to 0 in FIG.
The value "4" of (RCC-1) is copied to (CC-1). Further, the value of (CC-2) is decremented (step 104). As a result (CC-2) does not become 0 (step 105), the transfer destination identification code register (R
The value "1" of the identification code update information memory MDI-1 is added to the value "1" of I), so that the value of the transfer destination identification code register (RI) becomes "2". At the same time, the value “-3” of the address update information memory MDA-1 is added to the value “1003” of the transfer destination address register (RA), and the value of the transfer destination address register (RA) is the write address of the processor (2) “ 1000 "is updated.

As described above, the data D stored in the addresses "2000 to 2003" of the processor (0)
1 to D4, that is, “A0” in FIG. 8 is transferred to the address “1000 to 1003” of the processor (1).

Similarly, the data "D5 to D8" of the address "2004 to 2007" of the processor (0) = "B".
0 is the address (1000-100) of the processor (2)
3 ”. Similarly, when the data “D13 to D16” = “D0” stored in the addresses “2012 to 2015” of the processor (0) is transferred to the address “1000 to 1003” of the processor (0), as shown in FIG. , (CC-1) are decremented from "1" to "0" (step 101), after which the value "4" of (RCC-1) is copied to (CC-1) (step 10).
4). Also, (CC-2) is decremented from "1" to "0" (step 104), and then (RCC-).
The value "4" of 2) is copied to (CC-2) (step 107). At the same time, (CC-3) is decremented from "4" to "3" (step 107). Since CC-3 is not "0", the value "1" of MDI-2 is added to the value "0" of the transfer destination identification code register (RI) and the value "1003" of the transfer destination address register (RA). To MD
The value "13" of A-2 is added. As a result, the transfer destination of the next data D17 is "1016" of the processor (1).
Will be updated.

Although not shown in the figure, data sent from another processor is written in the memory (MM) while the address bus / data bus is not used. <Embodiment 2> FIG. 10 is an embodiment in which the transfer destination identification code update circuit (RI) of FIG. 4 is modified. In the embodiment of FIG. 4, the transfer control circuit also creates a packet for writing to its own memory (MM), but in the embodiment of FIG.
The own identification code is not written in the transfer destination identification code register (RI).

In this embodiment, the following constitution is provided. An identification code update addition circuit (ADD1) that adds the value of MDI to the current identification code RI.

This adder circuit for updating the identification code (ADD
A comparison circuit (CMP0) that compares the new transfer destination identification code RI created in 1) with its own processor identification code. When the comparison circuit (CMP0) compares its own identification code with the value of the new transfer destination identification code RI created by the identification code update addition circuit (ADD1), the output of the identification code update addition circuit (ADD1) The self-identification code avoidance data output circuit (MPX0) which outputs "1" when it is equal to the identification code of No.

Data “1” or “0” given by the self-identification code avoidance data output circuit (MPX0)
Is added to the new transfer destination identification code RI created by the identification code updating addition circuit (ADD1).

Identification code register (RI). With the above configuration, the comparison circuit (CMP0) compares its own identification code with the value of the new transfer destination identification code RI created by the identification code update addition circuit (ADD1), and the identification code update addition circuit (ADD1). , The data output circuit for avoiding the self-identification code (MP
X0) allows the second identification code updating adder circuit (AD
Since the data given to D2) is set to "1", its own identification code is not stored in the transfer destination identification code register (RI). <Third Embodiment> FIG. 11 shows a different embodiment of the transfer destination identification code updating circuit (RI) shown in FIG. In the embodiment of FIG. 4, the number of processors is limited to the power of 2 to the n-th power, but the embodiment of FIG. 11 has the following configuration.

An identification code update addition circuit (ADD1) that adds the value of MDI to the current identification code RI. A processor number comparison circuit (CMP1) that compares the new transfer destination identification code RI created by the identification code update addition circuit (ADD1) with the total number of processors.

When the comparison result of the comparison circuit (CMP1) and the total processor are input, and the comparison result indicates that the number of processors exceeds the value of RI, “the number of processors” is output, and otherwise, “0” is output. Select output circuit (MPX1).

Identification code update addition circuit (ADD1)
A subtraction circuit (SUB0) that subtracts the total number of processors from the value of the new transfer destination identification code RI created in. Identification code register (RI). Then, the comparison circuit (CMP1) compares the output of the address update addition circuit (ADD0) with the number of processor elements, and the address update addition circuit (ADD1) has an unsigned binary number (a binary number representing a positive number). By subtracting the number of processors by the subtraction circuit (SUB0) when the number of processors is equal to or more than the number of processors, the value of the transfer destination identification code register (RI) is restricted so as not to exceed the number of processors even if the number of processors is arbitrary. Can be done. <Embodiment 4> FIG. 12 shows an embodiment in which the memory write circuit (MW) is different. In this way, by providing the offset addition circuit (ADD3) for adding an offset value for shifting the address value to the write address on the receiving side, the receiving side area can be placed at a different address for each processor. <Embodiment 5> FIG. 13 shows a modification of the packet generation means (PC). When transfer data having the same transfer destination identification code continues, the transfer destination identification code and continuous transfer data and address are combined into one. It has a continuous packetizing function that collects packets.

In this embodiment, an identification code holding circuit (LI) and an identification code comparison circuit (CLI) are connected between the packet generating means (PC) and the transfer destination identification code register (RI). The identification code holding circuit (LI) stores the identification code of each packet when transferring each packet. The identification code comparison circuit (CLI) compares the identification code from the transfer destination identification code register (RI) with the previous identification code stored in the identification code holding circuit (LI) when a new packet is transmitted. When the identification code from the transfer destination identification code register (RI) is equal to the identification code stored in the identification code holding circuit (LI), the packet generation means (PC)
Only the transfer destination address of the transfer destination address holding unit (RA) and the data of the data holding register (RD) are sent to the network control circuit (NC-0).

FIG. 14 shows the difference between the packet generation in the first embodiment and the packet generation in the fifth embodiment. The packet generation means (PC) changes the network control circuit (NC-).
0) represents the data to be sent. FIG. 14 (1) shows the case where the first two packets of the data transfer in FIG. 9 are sent by the method of the first embodiment, and FIG. 14 (2) shows the same data sent by the method of the fifth embodiment. Represents the case.

In the fifth embodiment, as shown in FIG. 14B, when the identification code is sent by increasing the data width by 1 bit and sending the identification code, is it possible to send the identification code? I'm trying to figure out how. Therefore, the network control circuit (NC-0) can determine whether or not the data sent from the packet generation means (PC) includes the identification code. Then, the network control circuit (NC-0) determines that one packet has been sent until a new "1" is set in the identification code bit, and continues sending data to the same processor.

In this embodiment, the network control circuit (NC-0) and the network (NW) only have to specify the destination processor only for the first data when the data addressed to the same processor continues. It can reduce the time required for. Also, the amount of data flowing through the network can be reduced.

[0089]

By controlling the communication between the processors by the method and apparatus according to the present invention, the communication of data and the generation of the data can be performed in an overlapping manner.
Further, since the processing time in the processor is not required for determining the transfer destination, the execution efficiency of the system can be improved.

[Brief description of drawings]

FIG. 1 is an operation principle diagram of the present invention.

FIG. 2 is a block diagram showing an outline of a parallel computer according to the present invention.

FIG. 3 is a block diagram showing the principle of the device of the present invention.

FIG. 4 is a block diagram showing an embodiment of the present invention.

FIG. 5 is a flowchart showing a process of updating a transfer destination identification code and a transfer destination address.

FIG. 6 is a diagram showing a setting example of an update control table (RCC), an address update information memory (MDA), and an identification code update information memory (MDI) in all processors.

FIG. 7 is a transfer destination identification code register (RI), transfer destination address register (RA), lower limit address register (RL)
O) and an example of setting the upper limit address register (RHO)

FIG. 8 is a diagram showing an example of data transfer based on the initial setting values in FIGS.

9 is a timing chart of data transfer in FIG.

FIG. 10 is a block diagram showing another embodiment of the transfer destination identification code updating means.

FIG. 11 is a block diagram showing still another embodiment of the transfer destination identification code updating means.

FIG. 12 is a block diagram showing an offset adding unit for changing an address in a memory writing unit.

FIG. 13 is a block diagram showing a modification of the packet generation means (PC).

FIG. 14 is a diagram showing a difference between packet generation in the first embodiment and packet generation in the fifth embodiment. (1) shows the first two packets of the data transfer in FIG. 9 by the method of the first embodiment. When sent, (2) shows the case where the same data is sent by the method of the fifth embodiment.

[Explanation of symbols]

 (CPU) Processor (MM) Memory (C0 ... Cn) Communication control means (P0 ... Pn) Processor element (NW) Network (WC) Transmission data detection means (RI-M) Transfer destination identification code generation means (RA -M) Transfer destination address generation means (NC-0) Transmission means (NC-1) Reception means (MW) Memory writing means (ADD1) Identification code updating means (ADD0) Transfer destination address updating means (100) Self-designation avoidance Means (PC) Packet generation means (PD) Packet decomposition means (OADD) Offset addition means (WM) Write control means (RHO) Upper limit address registration unit (RLO) Lower limit address registration unit (DE) Data detection area setting means (JU) ) Judgment means (CHO) Upper limit address comparison means (CLO) Lower limit address comparison means (AND) Determination result output means (RD) Data holding section (RI) Transfer destination identification code holding section (MDI) Identification code update information memory (ADD1) Identification code update addition means (CC) Update control counter (RCC) Update control table (RA) Transfer destination address holding unit (MDA) Address update information memory (ADD0) Addition unit for address update

Claims (22)

[Claims] 1. A processor (CPU) and a memory (M
M) and a plurality of processor elements (P0 ... Pn) each having communication control means (C0 ... Cn),
Communication control means (C0 ...
In a distributed memory type parallel computer configured by connecting Cn) to each other via a network (NW), for writing data to a specific area by monitoring the writing of data from the processor (CPU) to the memory (MM) It is detected as data (step (a)), and the transfer destination identification code (M
K) and the transfer destination address (AD) are added (step (b)), the transmission data is transmitted to the reception side processor element determined according to the transfer destination identification code (step (c)), and the reception side processor A communication control method for a parallel computer, characterized in that transmission data is stored in a memory (MM) of an element according to the transfer destination address (step (d)). 2. The communication control method for a parallel computer according to claim 1, wherein the transfer destination identification code and the transfer destination address are updated every time the transmission data is transmitted. 3. The communication control method for a parallel computer according to claim 2, wherein the number of processor elements is 2 to the n-th power, and the bit width of the transfer destination identification code is set to the minimum width capable of expressing the number. 4. The communication control method for a parallel computer according to claim 1, wherein the transmission data, the transfer destination identification code, and the transfer destination address are packetized and transmitted. 5. The communication control method for a parallel computer according to claim 4, wherein when the transfer data having the same transfer destination identification code continues, the continuous transfer data is collectively transmitted in one packet. 6. The communication control method for a parallel computer according to claim 1, wherein the processor element of the transfer destination does not include its own processor element. 7. In the transfer destination processor element,
2. The communication control method for a parallel computer according to claim 1, wherein the write position at the transfer destination is changed by adding an offset value to the write address. 8. The communication control method for a parallel computer according to claim 1, wherein a real memory is not placed in a specific area in which the transfer data is to be written, and the area is dedicated to transfer to another processor (CPU). .. 9. The communication control method for a parallel computer according to claim 1, wherein the transfer data is written into the transfer destination memory (MM) in order from the lowest address. 10. A processor (CPU) and a memory (M
M) and a plurality of processor elements (P0 ... Pn) each having communication control means (C0 ... Cn),
Communication control means (C0 ...
In a distributed memory type parallel computer configured by connecting Cn) to each other via a network (NW), the communication control means (C0 ... Cn) is generated by the processor (CPU) and stored in the memory (MM). Outgoing data detection means (WC) for detecting data corresponding to a predetermined address among recorded data
And transfer destination identification code generation means (RI-M) for generating an identification code of the transfer destination processor element of the transmission data.
And the memory (M
M) the transfer destination address generating means (RA-M) for generating the data storage address, the transmission data detected by the transmission data detecting means (WC), and the transfer destination identification code generating means (RI-M). Identification code and transfer destination address generation means (RA-
M) transmitting means (NC-0) for transmitting the address to the network (NW), and receiving means (NC) receiving the transmission data, the identification code and the transmission data transmitted from another processor element. -1), and a memory writing unit (MW) for writing the data received by the receiving unit (NC-1) to the memory (MM) according to the address information also received, the communication of a parallel computer characterized by the following: Control device. 11. The transfer destination identification code generating means (RI-
M) has an identification code updating unit (ADD1) that updates the transfer destination identification code each time the transmission data is transmitted, and the transfer destination address generation unit (RA-M) sets the transfer destination address to the transmission data. 11. The communication control device for a parallel computer according to claim 10, further comprising transfer destination address updating means (ADD0) for updating each transmission. 12. The communication control device for a parallel computer according to claim 11, wherein the number of processor elements is 2 to the n-th power, and the bit width of the transfer destination identification code is set to the minimum width capable of expressing the number. 13. The identification code updating means (ADD1)
Has self-designation avoiding means (100) for further updating the updated identification code when the updated identification code indicates a self-processor element.
1. A communication control device for a parallel computer according to 1. 14. The transmission data detected by the transmission data detection means (WC) and the transfer destination identification code generation means (R).
I-M), and a packet generation unit (PC) that packetizes the identification code generated by the transfer destination address generation unit (RA-M), and the transmission unit (NC-0) is a packet Generation means (P
Send the packet by C) to the network (NW),
The receiving means (NC-1) receives a packet sent from another processor element via the network (NW), and the memory writing means (MW) receives the packet received by the receiving means (NC-1). Packet disassembling means (PD) for disassembling
11. The communication control device for a parallel computer according to claim 10, wherein the data obtained by decomposing the packet in D) is written in the memory (MM) according to the address information obtained in the same manner. 15. The packet generating means (PC), when transfer data having the same transfer destination identification code continues, collects continuous transfer data and addresses together with the transfer destination identification code into one packet. 15. The communication control device for a parallel computer according to claim 14, which has a function. 16. The memory writing means (MW) has an offset adding means (OADD) for adding an offset value to the received write address.
The communication control device of the parallel computer described in 0. 17. The write control means (WM), wherein the memory writing means (MW) writes transfer data to the transfer destination memory (MM) in order from the lowest address.
The communication control device for a parallel computer according to claim 10, further comprising: 18. The transmission data detecting means (WC)
Is an upper limit address registration unit (RHO) that stores an upper limit address of data to be detected and a lower limit address registration unit (RL) that stores a lower limit address of data to be detected.
O) and data detection area setting means (DE)
And a determination means (JU) for determining whether or not the write address of the data output from the processor (CPU) is within the area set by the data detection area setting means (DE), and the processor (CPU) 11. When the write address of the data output from the device is determined to be within the area set by the data detection area setting means (DE), the data within the area is output. Of parallel computer communication controller. 19. The determination means (JU) determines whether or not the write address of the data output from the processor (CPU) is less than or equal to the upper limit address stored in the upper limit address registration unit (RHO). An upper limit address comparison means (CHO) for judging and a lower limit address comparison for judging whether or not the write address of the data output from the processor (CPU) is greater than or equal to the lower limit address stored in the lower limit address register (RLO). Means (CLO), the upper limit address comparing means (CHO) and the lower limit address comparing means (CLO), the write address of the data output from the processor (CPU) is stored in the upper limit address registering unit (RHO). Write address of data output from the processor (CPU) that is less than or equal to the upper limit address and below. And a determination result output means (AND) that outputs a determination signal indicating that the data is within the data detection area when the lower limit address stored in the lower limit address register (RLO) is exceeded or exceeded. 19. The communication control device for a parallel computer according to claim 18. 20. The parallel according to claim 18, further comprising a data holding unit (RD) for temporarily holding data in the data detection area detected by the transmission data detection unit (WC). Computer communication control device. 21. The transfer destination identification code generating means (RI-
M) is a transfer destination identification code holding unit (RI) that stores the transfer destination identification code, an identification code update information memory (MDI) in which information for updating the transfer destination identification code is registered, and a transfer destination identification code holding unit (RI). The update information registered in the identification code update information memory (MDI) is added to the transfer destination identification code stored in (RI) to generate a new identification code, and the transfer destination identification code holding unit (R
I) the addition means for updating the identification code (ADD1), the update control counter (CC) which is set to the initial value “m” and subtracted from “m” for each data transfer, and the update control counter (CC). When it becomes "0", the update control counter (C
C) has an update control table (RCC) in which an initial value "m" is registered, and the transfer destination identification code holding unit (RI) transmits the transfer destination identification code to the communication means during data transfer. When the update control counter (CC) is not “0” and the update control counter (CC) is decremented at the same time, the identification code update addition means (ADD1) is added. ), A new identification code is generated by adding the update information registered in the identification code update information memory (MDI) to the transfer destination identification code, and the new identification code is stored in the transfer destination identification code holding unit (RI) for update control. Initial value "m" registered in the update control counter (CC) in the update control counter (CC) when the counter (CC) for update is "0"
11. The communication control device for a parallel computer according to claim 10, wherein 22. The transfer destination address generating means (RA-
M) is stored in the transfer destination address holding unit (RA) storing the transfer destination address, the address update information memory (MDA) in which the update information of the transfer destination address is registered, and the transfer destination address holding unit (RA). The update information registered in the address update information memory (MDA) is added to the transfer destination address to generate a new transfer destination address and is sent to the transfer destination address holding unit (RA).
0), initial value "m" is set and "m" is set for each data transfer.
An update control counter (CC) subtracted from the update control table, and an update control table in which an initial value "m" to be given to the update control counter (CC) when the update control counter (CC) becomes "0" is registered. (RCC), the transfer destination address holding unit (RA) transmits the transfer destination address to the communication unit and the address update addition unit (ADD0) at the time of data transfer, and at the same time, the update control counter (RAD). CC) is subtracted, and when the update control counter (CC) is not "0", the update information registered in the address update information memory (MDA) is added to the transfer destination address by the address update addition means (ADD0). As a result, a new transfer destination address is generated and stored in the transfer destination address holding unit (RA), and when the update control counter (CC) is "0", the update control counter CC) to update control for the control table (RC
11. The communication control device for a parallel computer according to claim 10, wherein the initial value "m" registered in C) is given.