CN113204517A - Inter-core sharing method of Ethernet controller special for electric power - Google Patents

Inter-core sharing method of Ethernet controller special for electric power Download PDF

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CN113204517A
CN113204517A CN202110488650.5A CN202110488650A CN113204517A CN 113204517 A CN113204517 A CN 113204517A CN 202110488650 A CN202110488650 A CN 202110488650A CN 113204517 A CN113204517 A CN 113204517A
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register
power
cache
address
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李鹏
潘可
李立浧
于杨
姚浩
习伟
丁琳
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Nanjing SAC Automation Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
    • Y04S40/12—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment
    • Y04S40/124—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment using wired telecommunication networks or data transmission busses

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Abstract

The invention discloses an inter-core sharing method of a power-dedicated Ethernet controller, which comprises configuration of the power-dedicated Ethernet controller, shared reception of Ethernet data and shared transmission of the Ethernet data. The inter-core sharing method of the Ethernet controller special for electric power provided by the invention can realize high-efficiency shared reception of the data special for electric power among multiple computing cores, and simultaneously can realize the equivalent data transmission function of the multiple computing cores. The sharing mode can effectively adapt to the current situation that various types of data introduced by the transformation and the upgrade of the power communication system are transmitted on the same physical Ethernet, and the problem of low receiving and sending efficiency of the power special data under the isolation operation of the current multifunctional area is solved.

Description

Inter-core sharing method of Ethernet controller special for electric power
Technical Field
The invention relates to an inter-core sharing method of a power special Ethernet controller, belonging to the technical field of computer system control in a power system.
Background
An Ethernet controller: a controller included in the processor for interfacing with functional portions of the ethernet transceiver. The processor realizes the function of physical network connection outside the processor through the controller and the special Ethernet transceiver. An ethernet controller mainly comprises two functional parts of data receiving and data transmitting.
Power-dedicated ethernet controller: on the basis of the Ethernet controller, preprocessing functions of data types specific to the power communication system are added, such as functions of GOOSE subscription, filtering, storm processing and the like.
Base address of power-dedicated ethernet controller: all configuration registers of the power-dedicated Ethernet controller are relatively centrally placed in a configuration space of the system, and the address of the minimum configuration register in all configuration registers is used as the base address of the power-dedicated Ethernet controller. All configuration registers of the power-specific ethernet controller may be obtained from the base address plus the difference between the address of the configuration register and the configuration register with the smallest address.
The relay protection product is an important secondary device of a power system as one of intelligent devices of a power grid, and fault judgment must be reliably and rapidly carried out, and a fault element must be selectively removed from the power system. With the development of digital relay protection technology, the performance, function and integration of relay protection products are greatly improved, and multi-core processors are gradually popularized in the relay protection products. Aiming at the requirements of high reliability, isolation among functions and the like of relay protection products, the multi-core processor generally works in an asymmetric multiprocessing working mode in the relay protection products, namely, each core of the multi-core processor respectively runs different operating system images, and each function area respectively runs different operation cores, so that the isolation degree among the function areas can be improved, and the reliability of the products is further improved.
When the relay protection product adopts an asymmetric multiprocessing working mode, the isolation degree between the functional areas is improved, and meanwhile, the cost of data sharing between different functional areas is increased. With the development of the current substation technology, relay protection products need to access more and more digital information, such as process level GOOSE, station control level GOOSE, and the like. The data are accessed to the relay protection product in the form of physical links of the Ethernet. The data volume of the information is large, and the requirement on the timeliness of the subsequent processing of the data is very high. With the combination of communication networks with different functions in the substation communication system, data accessed by the same physical ethernet device can be simultaneously required by a plurality of different functional areas. Under an asymmetric multiprocessing operation mode, sharing physical peripherals connected with Ethernet data receiving among processor cores directly causes great reduction of the operation efficiency among the cores, and how to efficiently and quickly share the physical peripherals among a plurality of independently operated function sections becomes a huge pain point in the application of the conventional multi-core processor.
In the patent "method and apparatus for accessing shared resources in a multi-core processor system", a method for accessing shared resources among cores in a multi-core processor system is mainly described. However, this access method requires additional hardware devices such as a mutex register, a setting unit, and a processing unit, and therefore, it can be applied only to a specific processor, and is not widely applicable. On the other hand, the shared resources targeted in the patent are mainly configuration resources of some systems, such as simple information of working frequency, working mode, whether to switch on or off, and cannot realize sharing and interaction of a large amount of data, so that the shared resources cannot meet the requirement of ethernet data sharing in a power scene.
The patent "system and method for implementing multi-core CPU to perform combined processing of messages" focuses more on a special multi-core CPU combined information processing, which is a specific information processing flow, and each computing core of the multi-core CPU combines processing of information. This is a specific solution under specific application requirements, and cannot be applied to the requirement of ethernet data sharing under power scenarios.
In the prior art, two schemes of time division multiplexing or function division are mostly adopted for resource sharing among cores in a multi-core processor.
The patent "a method and apparatus for accessing shared resources in a multi-core processor system" sets the status bit of the mutual exclusion register, thereby avoiding multiple computation cores from accessing shared resources at the same time, which is a time division multiplexing mode. The main disadvantage of time division multiplexing is that this will cause multiple compute cores that could be executed in parallel to wait for the release of the same resource, resulting in a significant decrease in the performance of multiple compute cores. This is not evident in the simple configuration of the patent method and apparatus for accessing shared resources in a multi-core processor system, but results in significant performance degradation due to inter-core latency when large data throughput is performed. On the other hand, in time division multiplexing, at any point, the shared resource will be exclusively occupied by the computing core that acquired the resource, which further causes multiple computing cores to respectively obtain part of ethernet data. According to the design of the current power communication system, data needed by multiple computing cores often overlap, and when a time division multiplexing scheme is adopted, additional data exchange overhead is introduced at multiple computing core points.
In the patent "system and method for implementing combined processing of messages by a multi-core CPU", a shared data buffer is provided for each core device in an execution data processing flow and possible preceding and following processes in a complete data processing flow, wherein a preceding processor writes only to the buffer and a succeeding processor reads only to the buffer. This is to realize resource sharing among cores by functional division. The main disadvantage of function division is that the two functions of reading or writing a shared resource must be divided in the computing core, i.e. for a shared resource, one core can only read and the other core can only write. This is not in line with the current power communications system requirements, and multiple computing cores must be able to simultaneously receive data from the power-only ethernet controller and simultaneously transmit data to the outside through the power-only ethernet controller.
Disclosure of Invention
The purpose is as follows: in order to overcome the defects in the prior art, the invention provides a method for sharing among cores of a power-dedicated Ethernet controller, by which when a power grid intelligent device operates, the power-dedicated Ethernet controller simultaneously provides data to different operation cores, and the data transmission of a plurality of different cores through the power-dedicated Ethernet controller is realized in a time-sharing way.
The technical scheme is as follows: in order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a method for sharing among cores of a power-dedicated Ethernet controller comprises a power-dedicated Ethernet controller configuration method, wherein the power-dedicated Ethernet controller configuration method comprises MAC configuration of the power-dedicated Ethernet controller, GOOSE configuration of the power-dedicated Ethernet controller, receiving buffer configuration of the power-dedicated Ethernet controller, sending buffer configuration of the power-dedicated Ethernet controller and sending and receiving enabling configuration of the power-dedicated Ethernet controller.
The MAC configuration of the power-dedicated Ethernet controller is executed in the main core, and the slave core is not executed; acquiring a base address of the Ethernet controller special for electric power, and acquiring addresses of a high-order register and a low-order register of an MAC address configuration register according to the base address; writing the high-order 2 bytes of the MAC address of the Ethernet controller into a high-order register of a MAC address configuration register; the lower 4 bytes of the ethernet controller MAC address are written into the lower register of the MAC address configuration register.
The GOOSE configuration of the power-dedicated ethernet controller is executed in the master core, and the slave core is not executed; acquiring a base address of the Ethernet controller special for electric power, acquiring a starting address of a GOOSE configuration register according to the base address, and acquiring an upper limit of the number of subscriptions currently supported by the GOOSE and a support of a filtering function; the configuration sequence number of the GOOSE subscription register is set to be 0; acquiring data of a destination MAC address, APPID, GOCBRef, DatSet, GoID and PortNum of a GOOSE message to be subscribed, and performing Hash calculation of CRC-32 on the data; filling the generated hash value into a GOOSE subscription register; adding 1 to the configuration serial number of the GOOSE subscription register; and repeating the steps until all GOOSE subscription information configuration is completed or all GOOSE subscription registers are exhausted.
Unpacking 10 GOOSE messages, timing, setting the timing value as tGS(ii) a The receiving frequency of the GOOSE message of each second of the power grid intelligent equipment is fGS_recvThe upper limit of the GOOSE message processing time is TGSAnd accordingly, the upper limit of the GOOSE processing capacity of the intelligent equipment of the power grid is determined to be
Figure BDA0003049383210000041
And writing the calculation result into a filter register of the GOOSE.
The receiving buffer configuration of the power-dedicated Ethernet controller is different in execution flow on the master core and the slave core; a main core process: acquiring a base address of the power special Ethernet controller, and calculating an address of a receiving cache address register, an address of a receiving cache size register, a received cache region number register and a receiving cache region state register according to the base address; according to the design and engineering configuration of the transformer substation, the network flow of the Ethernet controller special for the electric power is estimated and recorded as RestimateCalculating the average network packet size according to the engineering configuration
Figure BDA0003049383210000042
The maximum possible size of a network packet is
Figure BDA0003049383210000043
According to the design of the intelligent equipment of the power grid, the receiving frequency of each functional area is obtained
Figure BDA0003049383210000044
The value of the lowest receiving frequency is taken as
Figure BDA0003049383210000045
The size of the single receive buffer required for the power-dedicated Ethernet controller is calculated as
Figure BDA0003049383210000046
The number of receiving buffers is
Figure BDA0003049383210000047
The total size of the receive buffer required for the calculation is
Figure BDA0003049383210000048
Applying for a section of continuous inter-core shared memory; filling the initial address of the shared memory into a receiving cache address register of the power-dedicated Ethernet controller; size of single receive buffer
Figure BDA0003049383210000049
A receive buffer size register populated into the power-specific Ethernet controller; number of buffers to be received
Figure BDA00030493832100000410
A received buffer number register populated into the power-dedicated Ethernet controller; applying for an independent 8-byte inter-core shared memory, and recording as a shared received cache number register; a secondary core process: acquiring a base address of the power special Ethernet controller, and calculating an address of a receiving cache address register, an address of a receiving cache size register and a received cache region number register according to the base address; reading the content of a receiving cache address register, and acquiring the address of the receiving cache shared between the current cores; reading the content of a receiving cache size register and a received cache number register, and calculating the address of each receiving cache according to the address of the receiving cache, the size of the receiving cache and the number of the receiving caches; setting the local 8-byte received cache quantity to be 0; and acquiring the address of the shared received cache number register in the inter-core shared memory applied by the main core.
The sending cache configuration of the power-dedicated Ethernet controller is different in the execution flow of the master core and the slave core; a main core process: acquiring a base address of the power special Ethernet controller, and calculating an address of a sending cache address register, an address of a sending cache size register, a sending cache region number register and a sending cache region state register according to the base address; according to the design and engineering of the substationConfiguring, transmission network flow prediction of power dedicated Ethernet controller as TestimateCalculating the average size of each network packet according to the engineering configuration
Figure BDA0003049383210000051
The maximum possible size of a network packet is
Figure BDA0003049383210000052
The maximum delay requirement of the power special Ethernet data transmission of each functional area is
Figure BDA0003049383210000053
Wherein the maximum latency requirement for the minimum power-dedicated Ethernet data transmission is noted
Figure BDA0003049383210000054
The size of the single transmit buffer required for the power-dedicated Ethernet controller is calculated as
Figure BDA0003049383210000055
The number of transmission buffers is
Figure BDA0003049383210000056
Based on the above information, the total required send buffer size is calculated as
Figure BDA0003049383210000057
Applying for a section of continuous inter-core shared memory; filling the initial address of the shared memory into a transmission cache address register of the power special Ethernet controller; size of single send buffer
Figure BDA0003049383210000058
A transmission buffer size register filled in the power-dedicated Ethernet controller; number of buffers to be sent
Figure BDA0003049383210000059
Transmit cache for fill-in power-only Ethernet controllerA zone number register; applying for an independent 4-byte inter-core shared memory, and recording the memory as a serial number register of a sending cache region; a secondary core process: acquiring a base address of the power special Ethernet controller, and calculating an address of a sending address register, an address of a sending cache size register and a sending cache region number register according to the base address; reading the content of a sending cache address register, and acquiring the address of the sending cache between the current cores; reading the content of a sending cache size register and a sending number register, and calculating the address of each sending cache region according to the address of the sending cache, the size of the sending cache and the number of the sending caches; and acquiring the address of a sending cache region sequence number register in the inter-core shared memory applied by the main core.
The transmission and reception enabling configuration of the power-dedicated Ethernet controller is executed in the master core, and the slave core is not executed; acquiring a base address of the power special Ethernet controller, and calculating an address of a control register according to the base address; turning on the transmitting and receiving functions of the power-dedicated Ethernet controller; determining whether a broadcast receiving function or a hybrid receiving function of the power-dedicated Ethernet controller needs to be turned on according to a specific data type on the power-dedicated Ethernet controller; according to the data transmission type of the power-dedicated Ethernet controller, the minimum requirement for confirming the transmission delay of the data is
Figure BDA0003049383210000061
Calculating the overall transmit frequency of the power-dedicated Ethernet controller as
Figure BDA0003049383210000062
And a local timer with the same frequency is set, and the local timer sends out interruption at fixed time and is connected with the interruption for triggering the work flow of sending the special data of the electric power.
The shared memory in the receive buffer configuration of the power-dedicated ethernet controller needs to be able to be read by all compute cores and can be read and written by the ethernet controller.
The shared memory in the receive buffer configuration of the power-dedicated ethernet controller needs to be accessible to all other compute cores and separately operable to read and write, and needs to be simultaneously operable to read and write by the primary core.
The shared memory in the transmit buffer configuration of the power-dedicated ethernet controller needs to be accessible to all compute cores and to be able to perform read and write operations, respectively.
As a preferred scheme, the method further comprises an ethernet data sharing receiving method, and the specific steps are as follows:
a main core process: reading a receiving buffer area state register, wherein each bit in the register corresponds to a receiving buffer area, and when the receiving buffer area contains new unread data, the bit corresponding to the receiving buffer area is set to be 1; if any bit in the receiving buffer status register is set to 1, indicating that a new receiving buffer to be received exists; if each bit in the status register of the receiving buffer area is 0, it indicates that no new data exists in the receiving buffer area.
A secondary core process: reading a shared received cache number register and judging whether the shared received cache number register is consistent with the locally maintained received cache number; if the cache is consistent with the receiving cache, the cache is not newly received; if not, it indicates that there are more caches to be read currently.
The number of the received Ethernet messages for the power special purpose in the current nth functional area is recorded as
Figure BDA0003049383210000063
The number of shared caches applied by the main core is recorded as RnIf the current buffer sequence number to be received is
Figure BDA0003049383210000064
According to the base address Addr of the receiving bufferrecvAnd the size of each receive buffer
Figure BDA0003049383210000065
Obtain the address of the current receiving buffer area as
Figure BDA0003049383210000066
The data in the receiving buffer is read and stored locally by various feasible methods.
A main core process: calculating the bit offset of the buffer area state register according to the currently received sequence number of the buffer area; and (3) the corresponding bit offset position of a number with the same width is set to be 1, and the value is written into a buffer area state register, so that the release operation of the receiving buffer is realized.
A secondary core process: no operation is required.
A main core process: sharing the number of received buffers
Figure BDA0003049383210000071
The operation of adding 1 is carried out,
Figure BDA0003049383210000072
representing the number of power private ethernet messages received by functional area 0.
A secondary core process: the local received cache amount is processed
Figure BDA0003049383210000073
And adding 1.
As a preferred scheme, the method further comprises an ethernet data sharing sending method, and the specific steps are as follows:
the Ethernet sending time of each computing kernel starts from interruption triggering; for the primary core, the interrupt source is a timer set during Ethernet configuration; for a slave core, the interrupt source is an inter-core interrupt sent by the previous core in the sending order.
Judging whether data are to be transmitted: checking whether a local sending cache is empty, if so, no data needs to be sent; if not, then there is data to send.
According to the current serial number of the sending buffer zone
Figure BDA0003049383210000074
Multiplied by the transmit buffer size
Figure BDA0003049383210000075
The address offset of the current transmit buffer may be obtained
Figure BDA0003049383210000076
Plus the base address Addr in the transmit buffer address registersendThen the current sending buffer address can be obtained as
Figure BDA0003049383210000077
And filling the data in the local sending cache into the data cache.
Reading a state register of a sending buffer area, wherein each bit in the register corresponds to one sending buffer area, and when data in the corresponding sending buffer area needs to be sent, the position corresponding to the sending buffer area needs to be 1; after the data in the sending buffer is sent, the position corresponding to the sending buffer area is cleared by the power-dedicated Ethernet controller; and calculating the bit offset in a sending cache region status register corresponding to the sending cache region according to the serial number of the current sending cache region, and displacing the bit offset by 1 to realize cache sending.
After the transmission is completed, the status register of the transmission cache region needs to be moved forward; and it needs to calculate whether the sending buffer sequence number is already the same as the sending buffer number, if so, the sending buffer sequence number needs to be set to 0.
After the transmission is completed, the computing kernel needs to hand over the transmission right of the power-dedicated ethernet controller to a possible next computing kernel, and the operation is realized by using inter-kernel interrupt; the inter-core interrupt is initiated by a sending completion party, and a receiving party of the inter-core interrupt is a next calculation core of the sending sequence.
Preferably, if the current compute kernel is the last in the send order, then the inter-kernel interrupt need not be sent.
Has the advantages that: the inter-core sharing method of the Ethernet controller special for electric power provided by the invention can realize high-efficiency shared reception of the data special for electric power among multiple computing cores, and simultaneously can realize the equivalent data transmission function of the multiple computing cores. The sharing mode can effectively adapt to the current situation that various types of data introduced by the transformation and the upgrade of the power communication system are transmitted on the same physical Ethernet, and the problem of low receiving and sending efficiency of the power special data under the isolation operation of the current multifunctional area is solved.
Drawings
Fig. 1 is a schematic diagram of a multi-core sharing process of a power-dedicated ethernet controller.
Fig. 2 is a schematic diagram of a configuration flow of a power-dedicated ethernet controller.
Fig. 3 is a schematic diagram of a reception process of ethernet data sharing.
Fig. 4 is a schematic diagram of a process of sending ethernet data sharing.
Detailed Description
The present invention will be further described with reference to the following examples.
As shown in fig. 1, the multi-core sharing scheme of the power-dedicated ethernet controller includes three parts, namely, power-dedicated ethernet controller configuration, ethernet data-sharing reception, and ethernet data-sharing transmission.
As shown in fig. 2, the power-dedicated ethernet controller configuration includes a MAC configuration of the power-dedicated ethernet controller, a GOOSE configuration of the power-dedicated ethernet controller, a receive buffer configuration of the power-dedicated ethernet controller, a transmit buffer configuration of the power-dedicated ethernet controller, and a transmit receive enable configuration of the power-dedicated ethernet controller.
1. MAC configuration of power-dedicated ethernet controller, which configuration will only be performed at the master core, not at the slave core.
1.1. Acquiring a base address of the Ethernet controller special for electric power, and acquiring addresses of a high-order register and a low-order register of an MAC address configuration register according to the base address;
1.2. writing the high-order 2 bytes of the MAC address of the Ethernet controller into a high-order register of a MAC address configuration register;
1.3. writing the low-order 4 bytes of the MAC address of the Ethernet controller into a low-order register of a MAC address configuration register;
2. GOOSE configuration of the power-dedicated ethernet controller, which will only be performed in the master core and not in the slave core.
2.1. Acquiring a base address of the Ethernet controller special for electric power, acquiring a starting address of a GOOSE configuration register according to the base address, and acquiring an upper limit of the number of subscriptions currently supported by the GOOSE and a support of a filtering function;
2.2. configuring GOOSE subscription information;
2.2.1, setting the configuration sequence number of the GOOSE subscription register as 0;
2.2.2. acquiring data of a destination MAC address, APPID, GOCBRef, DatSet, GoID and PortNum of a GOOSE message to be subscribed, and performing Hash calculation of CRC-32 on the data;
2.2.3. filling the generated hash value into a GOOSE subscription register;
2.2.4. adding 1 to the configuration sequence number of the GOOSE subscription register;
2.2.5. repeating the steps until all GOOSE subscription information configuration is completed or all GOOSE subscription registers are exhausted;
2.3. configuring GOOSE filtering information;
2.3.1. unpacking 10 GOOSE messages, timing, setting the timing value as tGS。
2.3.2. The receiving frequency of the GOOSE message of each second of the power grid intelligent equipment is fGS_recvThe upper limit of the GOOSE message processing time is TGSAnd accordingly, the upper limit of the GOOSE processing capacity of the intelligent equipment of the power grid is determined to be
Figure BDA0003049383210000091
2.3.3. The calculation result is written into a filtering register of the GOOSE, so that the receiving quantity of GOOSE messages can be ensured not to exceed the computing capability of the intelligent equipment of the power grid, and different message analysis and processing performances can be automatically adapted.
3. And receiving a cache configuration of the power-dedicated Ethernet controller, wherein the configuration is different from the execution flow of the configuration on the master core and the slave core.
3.1. A main core process:
3.1.1. acquiring a base address of the power special Ethernet controller, and calculating an address of a receiving cache address register, an address of a receiving cache size register, a received cache region number register and a receiving cache region state register according to the base address;
3.1.2. according to the design and engineering configuration of the transformer substation, the network flow of the Ethernet controller special for the electric power is estimated and recorded as RestimateCalculating the average network packet size according to the engineering configuration
Figure BDA0003049383210000101
The maximum possible size of a network packet is
Figure BDA0003049383210000102
According to the design of the intelligent equipment of the power grid, the receiving frequency of each functional area is obtained
Figure BDA0003049383210000103
The value of the lowest receiving frequency is taken as
Figure BDA0003049383210000104
The size of the single receive buffer required for the power-dedicated Ethernet controller is calculated as
Figure BDA0003049383210000105
The number of receiving buffers is
Figure BDA0003049383210000106
The total size of the receive buffer required for the calculation is
Figure BDA0003049383210000107
And applies for a section of continuous inter-core shared memory.
The segment of shared memory needs to be able to be read by all compute cores and read and write by the ethernet controller.
3.1.3. Filling the initial address of the shared memory into a receiving cache address register of the power-dedicated Ethernet controller;
3.1.4. size of single receive buffer
Figure BDA0003049383210000108
A receive buffer size register populated into the power-specific Ethernet controller;
3.1.5. number of buffers to be received
Figure BDA0003049383210000109
A received buffer number register populated into the power-dedicated Ethernet controller;
3.1.6. an independent 8-byte inter-core shared memory is applied and is recorded as a shared received cache number register. The segment of shared memory needs to be accessible to all other compute kernels and can be read separately, and needs to be read and written simultaneously by the main kernel.
3.2. A secondary core process:
3.2.1. acquiring a base address of the power special Ethernet controller, and calculating an address of a receiving cache address register, an address of a receiving cache size register and a received cache region number register according to the base address;
3.2.2. reading the content of a receiving cache address register, and acquiring the address of the receiving cache shared between the current cores;
3.2.3. reading the content of a receiving cache size register and a received cache number register, and calculating the address of each receiving cache according to the address of the receiving cache, the size of the receiving cache and the number of the receiving caches;
3.2.4. setting the local 8-byte received cache quantity to be 0;
3.2.5. and acquiring the address of the shared received cache number register in the inter-core shared memory applied by the main core.
4. And the sending buffer configuration of the power-dedicated Ethernet controller is different from the execution flow of the configuration on the master core and the slave core.
4.1. A main core process:
4.1.1. acquiring a base address of the power special Ethernet controller, and calculating an address of a sending cache address register, an address of a sending cache size register, a sending cache region number register and a sending cache region state register according to the base address;
4.1.2. according to the design and engineering configuration of the transformer substation, the transmission network flow of the power special Ethernet controller is estimated to be TestimateCalculating the average size of each network packet according to the engineering configuration
Figure BDA0003049383210000111
The maximum possible size of a network packet is
Figure BDA0003049383210000112
The maximum delay requirement of the power special Ethernet data transmission of each functional area is
Figure BDA0003049383210000113
Wherein the maximum latency requirement for the minimum power-dedicated Ethernet data transmission is noted
Figure BDA0003049383210000114
The size of the single transmit buffer required for the power-dedicated Ethernet controller is calculated as
Figure BDA0003049383210000115
The number of transmission buffers is
Figure BDA0003049383210000116
Based on the above information, the total required send buffer size is calculated as
Figure BDA0003049383210000117
And applies for a section of continuous inter-core shared memory. The segment of shared memory needs to be written by all the computation cores for storing the ethernet data to be sent.
4.1.3. And filling the initial address of the shared memory into a transmission cache address register of the power-dedicated Ethernet controller.
4.1.4. Size of single send buffer
Figure BDA0003049383210000118
Fill in the transmit buffer size register of the power-dedicated ethernet controller.
4.1.5. Number of buffers to be sent
Figure BDA0003049383210000119
Fill in the transmit buffer number register of the power-dedicated ethernet controller.
4.1.6. An independent 4-byte inter-core shared memory is applied and is recorded as a sending cache region sequence number register. The segment of shared memory needs to be accessible to all compute kernels and can be read and written separately.
4.2. A secondary core process:
4.2.1. and acquiring a base address of the power special Ethernet controller, and calculating an address of a sending address register, an address of a sending cache size register and a sending cache region number register according to the base address.
4.2.2. And reading the content of the sending cache address register to obtain the address of the sending cache between the current cores.
4.2.3. And reading the content of the sending buffer size register and the sending number register, and calculating the address of each sending buffer area according to the address of the sending buffer, the size of the sending buffer and the number of the sending buffers.
4.2.4. And acquiring the address of a sending cache region sequence number register in the inter-core shared memory applied by the main core.
5. The transmit receive enable configuration of the power-dedicated ethernet controller will be performed only at the master core and not at the slave core.
5.1. Acquiring a base address of the power special Ethernet controller, and calculating an address of a control register according to the base address;
5.2. turning on the transmitting and receiving functions of the power-dedicated Ethernet controller;
5.3. determining whether a broadcast reception function or a promiscuous reception function of the power-dedicated Ethernet controller needs to be turned on according to a specific data type on the power-dedicated Ethernet controller.
5.4. According to the data transmission type of the power-dedicated Ethernet controller, the minimum requirement for confirming the transmission delay of the data is
Figure BDA0003049383210000121
Calculating the overall transmit frequency of the power-dedicated Ethernet controller as
Figure BDA0003049383210000122
And a local timer with the same frequency is set, and the local timer sends out interruption at fixed time and is connected with the interruption for triggering the work flow of sending the special data of the electric power. Under the working mode, the delay of the power special Ethernet data transmission of each functional area operated in the power grid intelligent equipment can be ensured to be within the standard requirement.
As shown in fig. 3, the ethernet data sharing reception is divided into two roles of a master core and a slave core. The main core and the slave core are respectively and independently executed, and the flow is as follows:
1. judging whether valid data exists in the receiving cache or not:
1.1. a main core: reading a receiving buffer area state register, wherein each bit in the register corresponds to a receiving buffer area, and when the receiving buffer area contains new unread data, the bit corresponding to the receiving buffer area is set to be 1. If any bit in the receiving buffer status register is set to 1, indicating that a new receiving buffer to be received exists; if each bit in the status register of the receiving buffer area is 0, it indicates that no new data exists in the receiving buffer area.
1.2. And (3) a slave core: the shared received buffer number register is read and judged whether the shared received buffer number register is consistent with the received buffer number maintained locally. If the cache is consistent with the receiving cache, the cache is not newly received; if not, it indicates that there are more caches to be read currently.
2. Calculating a receiving cache address: the current n functional area has received the Ethernet report special for electric powerAmount of text, as
Figure BDA0003049383210000131
The number of shared caches applied by the main core is recorded as RnIf the current buffer sequence number to be received is
Figure BDA0003049383210000132
According to the base address Addr of the receiving bufferrecvAnd the size of each receive buffer
Figure BDA0003049383210000133
Obtain the address of the current receiving buffer area as
Figure BDA0003049383210000134
3. Receiving data: the data in the receiving buffer is read and stored locally by various feasible methods.
4. Receiving buffer release:
4.1. a main core: and calculating the bit offset of the buffer status register according to the sequence number of the currently received buffer. And (3) the corresponding bit offset position of a number with the same width is set to be 1, and the value is written into a buffer area state register, so that the release operation of the receiving buffer is realized.
4.2. And (3) a slave core: no operation is required.
5. The number of received buffers increases:
5.1. a main core: sharing the number of received buffers
Figure BDA0003049383210000135
The operation of adding 1 is carried out,
Figure BDA0003049383210000136
representing the number of power private ethernet messages received by functional area 0.
5.2. And (3) a slave core: the local received cache amount is processed
Figure BDA0003049383210000137
Plus 1 operation。
As shown in fig. 4, the ethernet data sharing transmission is divided into two roles of a master core and a slave core. The master core and the slave core need to be executed cooperatively. Both the master core and the slave core can meet the requirement of sending Ethernet data, but the master core needs to additionally realize the triggering of the whole sending process.
1. Waiting for an interrupt trigger: the ethernet sending time of each compute kernel starts after an interrupt trigger. For the primary core, the interrupt source is a timer set during Ethernet configuration; for the slave core, the Interrupt source is an Inter-Processor Interrupt (IPI) sent by the previous core in the sending order.
2. Judging whether data are to be transmitted: checking whether a local sending cache is empty, if so, no data needs to be sent; if not, then there is data to send.
3. Calculating a sending cache address: according to the current serial number of the sending buffer zone
Figure BDA0003049383210000141
Multiplied by the transmit buffer size
Figure BDA0003049383210000142
The address offset of the current transmit buffer may be obtained
Figure BDA0003049383210000143
Plus the base address Addr in the transmit buffer address registersendThen the current sending buffer address can be obtained as
Figure BDA0003049383210000144
4. Filling data: and filling the data in the local sending cache into the data cache.
5. Sending and caching: reading a state register of a sending buffer area, wherein each bit in the register corresponds to one sending buffer area, and when data in the corresponding sending buffer area needs to be sent, the position corresponding to the sending buffer area needs to be 1; when the data in the transmission buffer is completely transmitted, the position corresponding to the transmission buffer area is cleared by the power-dedicated Ethernet controller. And calculating the bit offset in a sending cache region status register corresponding to the sending cache region according to the serial number of the current sending cache region, and displacing the bit offset by 1 to realize cache sending.
6. Forward shifting the sequence number of the sending buffer area: after the transmission is completed, the status register of the transmission buffer needs to be moved forward. And it needs to calculate whether the sending buffer sequence number is already the same as the sending buffer number, if so, the sending buffer sequence number needs to be set to 0.
7. Sending an inter-core interrupt: after the transmission is complete, the compute core needs to hand off the power-specific ethernet controller's transmission to the possible next compute core, which is done using an inter-core interrupt. The inter-core interrupt is initiated by a sending completion party, and a receiving party of the inter-core interrupt is a next calculation core of the sending sequence. It should be noted that if the current compute kernel is the last in the issue order, the inter-core interrupt no longer needs to be issued.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.

Claims (7)

1. A method for sharing cores of a power-dedicated Ethernet controller is characterized in that: the method comprises a configuration method of a power-dedicated Ethernet controller, wherein the configuration method of the power-dedicated Ethernet controller comprises MAC configuration of the power-dedicated Ethernet controller, GOOSE configuration of the power-dedicated Ethernet controller, receiving buffer configuration of the power-dedicated Ethernet controller, sending buffer configuration of the power-dedicated Ethernet controller and sending and receiving enabling configuration of the power-dedicated Ethernet controller;
the MAC configuration of the power-dedicated Ethernet controller is executed in the main core, and the slave core is not executed; acquiring a base address of the Ethernet controller special for electric power, and acquiring addresses of a high-order register and a low-order register of an MAC address configuration register according to the base address; writing the high-order 2 bytes of the MAC address of the Ethernet controller into a high-order register of a MAC address configuration register; writing the low-order 4 bytes of the MAC address of the Ethernet controller into a low-order register of a MAC address configuration register;
the GOOSE configuration of the power-dedicated ethernet controller is executed in the master core, and the slave core is not executed; acquiring a base address of the Ethernet controller special for electric power, acquiring a starting address of a GOOSE configuration register according to the base address, and acquiring an upper limit of the number of subscriptions currently supported by the GOOSE and a support of a filtering function; the configuration sequence number of the GOOSE subscription register is set to be 0; acquiring data of a destination MAC address, APPID, GOCBRef, DatSet, GoID and PortNum of a GOOSE message to be subscribed, and performing Hash calculation of CRC-32 on the data; filling the generated hash value into a GOOSE subscription register; adding 1 to the configuration serial number of the GOOSE subscription register; repeating the steps until all GOOSE subscription information configuration is completed or all GOOSE subscription registers are exhausted;
unpacking 10 GOOSE messages, timing, setting the timing value as tGS(ii) a The receiving frequency of the GOOSE message of each second of the power grid intelligent equipment is fGS_recvThe upper limit of the GOOSE message processing time is TGSAnd accordingly, the upper limit of the GOOSE processing capacity of the intelligent equipment of the power grid is determined to be
Figure FDA0003049383200000011
Writing the calculation result into a filter register of the GOOSE;
the receiving buffer configuration of the power-dedicated Ethernet controller is different in execution flow on the master core and the slave core; a main core process: acquiring a base address of the power special Ethernet controller, and calculating an address of a receiving cache address register, an address of a receiving cache size register, a received cache region number register and a receiving cache region state register according to the base address; according to the design and engineering configuration of the transformer substation, the network flow of the Ethernet controller special for the electric power is estimated and recorded as RestimateCalculating the average network packet size according to the engineering configuration
Figure FDA0003049383200000012
The maximum possible size of a network packet is
Figure FDA0003049383200000013
According to the design of the intelligent equipment of the power grid, the receiving frequency of each functional area is obtained
Figure FDA0003049383200000021
The value of the lowest receiving frequency is taken as
Figure FDA0003049383200000022
The size of the single receive buffer required for the power-dedicated Ethernet controller is calculated as
Figure FDA0003049383200000023
The number of receiving buffers is
Figure FDA0003049383200000024
The total size of the receive buffer required for the calculation is
Figure FDA0003049383200000025
Applying for a section of continuous inter-core shared memory; filling the initial address of the shared memory into a receiving cache address register of the power-dedicated Ethernet controller; size of single receive buffer
Figure FDA0003049383200000026
A receive buffer size register populated into the power-specific Ethernet controller; number of buffers to be received
Figure FDA0003049383200000027
A received buffer number register populated into the power-dedicated Ethernet controller; applying for an independent 8-byte inter-core shared memory, and recording as a shared received cache number register; a secondary core process: special Ethernet for acquiring powerThe network controller calculates the address of a register for receiving the cache address, the address of a register for receiving the cache size and the number of received cache regions according to the base address; reading the content of a receiving cache address register, and acquiring the address of the receiving cache shared between the current cores; reading the content of a receiving cache size register and a received cache number register, and calculating the address of each receiving cache according to the address of the receiving cache, the size of the receiving cache and the number of the receiving caches; setting the local 8-byte received cache quantity to be 0; acquiring addresses of shared received cache number registers in an inter-core shared memory applied by a main core;
the sending cache configuration of the power-dedicated Ethernet controller is different in the execution flow of the master core and the slave core; a main core process: acquiring a base address of the power special Ethernet controller, and calculating an address of a sending cache address register, an address of a sending cache size register, a sending cache region number register and a sending cache region state register according to the base address; according to the design and engineering configuration of the transformer substation, the transmission network flow of the power special Ethernet controller is estimated to be TestimateCalculating the average size of each network packet according to the engineering configuration
Figure FDA0003049383200000028
The maximum possible size of a network packet is
Figure FDA0003049383200000029
The maximum delay requirement of the power special Ethernet data transmission of each functional area is
Figure FDA00030493832000000210
Wherein the maximum latency requirement for the minimum power-dedicated Ethernet data transmission is noted
Figure FDA00030493832000000211
The size of the single transmit buffer required for the power-dedicated Ethernet controller is calculated as
Figure FDA00030493832000000212
The number of transmission buffers is
Figure FDA00030493832000000213
Based on the above information, the total required send buffer size is calculated as
Figure FDA0003049383200000031
Applying for a section of continuous inter-core shared memory; filling the initial address of the shared memory into a transmission cache address register of the power special Ethernet controller; size of single send buffer
Figure FDA0003049383200000032
A transmission buffer size register filled in the power-dedicated Ethernet controller; number of buffers to be sent
Figure FDA0003049383200000033
A register for the number of transmission buffer areas filled in the Ethernet controller special for electric power; applying for an independent 4-byte inter-core shared memory, and recording the memory as a serial number register of a sending cache region; a secondary core process: acquiring a base address of the power special Ethernet controller, and calculating an address of a sending address register, an address of a sending cache size register and a sending cache region number register according to the base address; reading the content of a sending cache address register, and acquiring the address of the sending cache between the current cores; reading the content of a sending cache size register and a sending number register, and calculating the address of each sending cache region according to the address of the sending cache, the size of the sending cache and the number of the sending caches; acquiring an address of a sending cache region sequence number register in an inter-core shared memory applied by a main core;
the transmission and reception enabling configuration of the power-dedicated Ethernet controller is executed in the master core, and the slave core is not executed; obtaining a base address of a power-specific Ethernet controller and calculating based on the base addressAn address of a control register; turning on the transmitting and receiving functions of the power-dedicated Ethernet controller; determining whether a broadcast receiving function or a hybrid receiving function of the power-dedicated Ethernet controller needs to be turned on according to a specific data type on the power-dedicated Ethernet controller; according to the data transmission type of the power-dedicated Ethernet controller, the minimum requirement for confirming the transmission delay of the data is
Figure FDA0003049383200000034
Calculating the overall transmit frequency of the power-dedicated Ethernet controller as
Figure FDA0003049383200000035
And a local timer with the same frequency is set, and the local timer sends out interruption at fixed time and is connected with the interruption for triggering the work flow of sending the special data of the electric power.
2. The method of claim 1, wherein the method comprises: the method also comprises an Ethernet data sharing receiving method, which comprises the following steps:
a main core process: reading a receiving buffer area state register, wherein each bit in the register corresponds to a receiving buffer area, and when the receiving buffer area contains new unread data, the bit corresponding to the receiving buffer area is set to be 1; if any bit in the receiving buffer status register is set to 1, indicating that a new receiving buffer to be received exists; if each bit in the status register of the receiving cache region is 0, the receiving cache region does not have new data;
a secondary core process: reading a shared received cache number register and judging whether the shared received cache number register is consistent with the locally maintained received cache number; if the cache is consistent with the receiving cache, the cache is not newly received; if the cache is inconsistent, the cache is indicated to have more caches to be read;
the number of the received Ethernet messages for the power special purpose in the current nth functional area is recorded as
Figure FDA0003049383200000041
The number of shared caches applied by the main core is recorded as RnIf the current buffer sequence number to be received is
Figure FDA0003049383200000042
According to the base address Addr of the receiving bufferrecvAnd the size of each receive buffer
Figure FDA0003049383200000043
Obtain the address of the current receiving buffer area as
Figure FDA0003049383200000044
Reading the data in the receiving cache region by various feasible methods and storing the data in the local region;
a main core process: calculating the bit offset of the buffer area state register according to the currently received sequence number of the buffer area; the corresponding bit offset position of a number with the same width is set to be 1, and the value is written into a buffer area state register to realize the release operation of the receiving buffer;
a secondary core process: no operation is required;
a main core process: sharing the number of received buffers
Figure FDA0003049383200000045
The operation of adding 1 is carried out,
Figure FDA0003049383200000046
representing the quantity of the received Ethernet messages special for the power in the 0 th functional area;
a secondary core process: the local received cache amount is processed
Figure FDA0003049383200000047
And adding 1.
3. The method of claim 1 or 2, wherein the method comprises: the method also comprises an Ethernet data sharing and sending method, which comprises the following steps:
the Ethernet sending time of each computing kernel starts from interruption triggering; for the primary core, the interrupt source is a timer set during Ethernet configuration; for the slave core, the interrupt source is an inter-core interrupt sent by the previous core in the sending sequence;
judging whether data are to be transmitted: checking whether a local sending cache is empty, if so, no data needs to be sent; if not, then there is data to send;
according to the current serial number of the sending buffer zone
Figure FDA0003049383200000048
Multiplied by the transmit buffer size
Figure FDA0003049383200000049
The address offset of the current transmit buffer may be obtained
Figure FDA00030493832000000410
Plus the base address Addr in the transmit buffer address registersendThen the current sending buffer address can be obtained as
Figure FDA00030493832000000411
Filling the data in the local sending cache into the data cache;
reading a state register of a sending buffer area, wherein each bit in the register corresponds to one sending buffer area, and when data in the corresponding sending buffer area needs to be sent, the position corresponding to the sending buffer area needs to be 1; after the data in the sending buffer is sent, the position corresponding to the sending buffer area is cleared by the power-dedicated Ethernet controller; according to the serial number of the current sending cache region, calculating the bit offset in a status register of the sending cache region corresponding to the sending cache region, and displacing the bit offset by 1 to realize cache sending;
after the transmission is completed, the status register of the transmission cache region needs to be moved forward; whether the number of the sending buffer area is the same as the number of the sending buffer area or not needs to be calculated, and if the number of the sending buffer area is the same as the number of the sending buffer area, the number of the sending buffer area needs to be set to be 0;
after the transmission is completed, the computing kernel needs to hand over the transmission right of the power-dedicated ethernet controller to a possible next computing kernel, and the operation is realized by using inter-kernel interrupt; the inter-core interrupt is initiated by a sending completion party, and a receiving party of the inter-core interrupt is a next calculation core of the sending sequence.
4. The method of claim 1, wherein the method comprises: the shared memory in the receive buffer configuration of the power-dedicated ethernet controller needs to be able to be read by all compute cores and can be read and written by the ethernet controller.
5. The method of claim 1, wherein the method comprises: the shared memory in the receive buffer configuration of the power-dedicated ethernet controller needs to be accessible to all other compute cores and separately operable to read and write, and needs to be simultaneously operable to read and write by the primary core.
6. The method of claim 1, wherein the method comprises: the shared memory in the transmit buffer configuration of the power-dedicated ethernet controller needs to be accessible to all compute cores and to be able to perform read and write operations, respectively.
7. The method of claim 3, wherein the method comprises: if the current compute kernel is the last in the send order, then the inter-kernel interrupt no longer needs to be sent.
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