JPS55102054A - Failure informing system - Google Patents

Failure informing system

Info

Publication number
JPS55102054A
JPS55102054A JP902479A JP902479A JPS55102054A JP S55102054 A JPS55102054 A JP S55102054A JP 902479 A JP902479 A JP 902479A JP 902479 A JP902479 A JP 902479A JP S55102054 A JPS55102054 A JP S55102054A
Authority
JP
Japan
Prior art keywords
failure
address
processor
unit
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP902479A
Other languages
Japanese (ja)
Other versions
JPS594053B2 (en
Inventor
Toshio Awaji
Kazumi Endo
Takeshi Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP54009024A priority Critical patent/JPS594053B2/en
Publication of JPS55102054A publication Critical patent/JPS55102054A/en
Publication of JPS594053B2 publication Critical patent/JPS594053B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To reduce the failure from the production of a failure to its detection, by giving specific address and failure informing address to one processor among a plurality of processors.
CONSTITUTION: A plurality of processors CC#1WCC#n and one or more peripheral control unit PU#1WPU#m are connected on the same bus 6, and each processor and peripheral unit has specific unit address. Since specific unit address and failure informing address are given to either one of the processors, each processor and peripheral control unit designate the failure informing address to the bus 6 when a failure of the unit itself and delivers the failure information. Accordingly, the processor having the failure informing address receives the failure information, then the time up to the detection can be reduced.
COPYRIGHT: (C)1980,JPO&Japio
JP54009024A 1979-01-29 1979-01-29 Failure notification method Expired JPS594053B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54009024A JPS594053B2 (en) 1979-01-29 1979-01-29 Failure notification method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54009024A JPS594053B2 (en) 1979-01-29 1979-01-29 Failure notification method

Publications (2)

Publication Number Publication Date
JPS55102054A true JPS55102054A (en) 1980-08-04
JPS594053B2 JPS594053B2 (en) 1984-01-27

Family

ID=11709080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54009024A Expired JPS594053B2 (en) 1979-01-29 1979-01-29 Failure notification method

Country Status (1)

Country Link
JP (1) JPS594053B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01303942A (en) * 1988-06-01 1989-12-07 Hitachi Ltd Communication control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01303942A (en) * 1988-06-01 1989-12-07 Hitachi Ltd Communication control system
JP2528938B2 (en) * 1988-06-01 1996-08-28 株式会社日立製作所 Communication control system

Also Published As

Publication number Publication date
JPS594053B2 (en) 1984-01-27

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