JPS62161295A - Electronic exchange - Google Patents

Abstract

PURPOSE:To improve the efficiency of communication between processors by connecting a local memory to a local bus and making communication between processors connected to a common bus through the common bus, a common memory and a buffer. CONSTITUTION:The processor of transmitting side performs the transmission by writing data in a common memory through a common bus, and the processor of receiving side receives by reading the content of the common memory. A card that constitutes a common control section such as a local CPU card 13 that makes input/output level conversion in soft, a time switch card 14 that executes the conversion of a time division time slot, etc., is mounted to a common control shelf 1. Processors in common control card 11-14 perform communication mutually through the common memory 16 connected to the common bus 15. When a decoder 44 detects address allotted to a common memory 71, a buffer 45 connects the common bus 15 and a local bus 46. Thus, the communication between processors can be made at high efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a distributed control electronic switching system, and particularly to a communication system between processors connected to a common bus.

(Prior Art) In recent years, electronic exchanges have been required not only to have simple exchange processing functions, but also to have various associated features (for example, call management, message services, directories, etc.). Providing a large number of features increases the load on the processor accordingly. Therefore, the overall processing capacity is increased by using multiple processors and distributing the processing power and load.

When configuring such a multiprocessor type electronic exchange, the problem is how to smoothly communicate between the processors. In particular, since the above-mentioned features are deeply related to exchange processing, there is a lot of data that is commonly used between the features, and therefore precise inter-processor communication is required.

One way to communicate between multiple processors is to
It is conceivable to form a unique bus between processors. However, this method has the problem that when a plurality of processors are mounted on different cards, the number of wires between the cards increases, resulting in an increase in cost and a decrease in reliability by 1'B.

On the other hand, if a common bus system is adopted in which a plurality of processors communicate via a common bus, the above-mentioned problems of the unique bus system can be solved. However, in the common bus method, if each processor is simply connected to a common bus and each processor directly accesses the memory attached to the other processor, there is a possibility that the work being executed by the other processor may be interfered with. be. In order to prevent such interference, if the destination processor is performing work, waiting for communication until the work is completed will result in inefficiency and make it difficult to provide advanced services.

(Problems to be Solved by the Invention) As described above, in the conventional common bus system, it is difficult for each processor to communicate efficiently between processors without interfering with the work being executed by other processors. Ta.

The present invention has been made to solve these problems, and allows smooth communication between multiple processors connected to a common bus, regardless of whether or not the destination processor is executing other tasks. It is an object of the present invention to provide an electronic exchange that can perform the above operations efficiently.

Configuration of the Invention (Means for Solving Problems) The present invention is an electronic switching system using a multiprocessor control system in which a plurality of processors are connected to a common bus, in which a common memory commonly used by each processor is connected to the common bus. and connect the local bus through a buffer,
Connect local memory that stores programs and data that operate processors to a local bus, and communicate between processors connected to a common bus by using a common bus, common memory, and buffers? It is characterized by being carried out through

(Operation) When transmitting data from one processor to another, the transmitter's processor writes the data to the common memory via the common bus, and the transmitter's processor writes the contents of the common memory as appropriate. Receive by reading. Therefore, when the sending processor generates data that it wants to send, it can immediately send it regardless of the state of the sending destination processor, thereby making communication between the processors efficient. Further, since the local memory attached to the processor is separated from the common bus via a buffer, the operation of the processor is not disturbed by data on the common bus.

(Embodiment) FIG. 1 is a schematic configuration diagram of an electronic exchange according to an embodiment of the present invention, in which a common control shelf 1 and a plurality of line/trunk shelves 28 to 2n are stacked as shown in FIG. It has a structure.

The common $ control shelf 1 includes a main CPU (MCI) card 11 that handles exchange processing, maintenance, etc.
Application CPLI (Ac
t) Communication control between the card 12, the main CPIJ card 11, the application CPU card 12, and the line/trunk (L/T) card 21;
Local C that performs input/output level conversion etc. in software
PU (L91) IJ) card 13, and a time switch (TSW) for converting time division time slots.
A card (card-shaped circuit device) constituting a common control unit such as the card 14 is mounted. In the present invention, the various cards 11 to 14 in the common control shelf 1 are collectively referred to as a common control card. In addition, each common control card 1
The processors 1 to 14 can communicate with each other via a common memory 16 connected to a common bus 15.

On the other hand, inside the line/trunk shelves 2a to 2n, there are line/trunk shelves to which subscriber terminals such as telephones and data terminals are connected.
Trunk (L/T) cards 21 are installed according to the number of lines. The connection between the common control shelf 1 and the line/trunk shelves 2a to 2n includes a data highway for transmission from the local CPU card 13 to the line/trunk card 21 and a data highway for reception from the line/trunk card 21 to the local CPU card 13. A control highway 3 for serial transmission and a PCM highway 4 for exchanging PCM time slots are connected between the time switch card 14 and the line/trunk card 21.

Next, each part in FIG. 1 will be explained in detail.

FIG. 3 shows the internal configuration of the line/trunk card 21, particularly the line/trunk card connected to the digital telephone 31. As shown in FIG. In FIG. 3, a digital telephone LS I (DTLS I) 32 is a board controller (PC) 33 consisting of a digital telephone 31 and a CPU that controls line/trunk cards, telephones connected to this, shoulder lines, etc. This is an LSI that controls communications between the two. In addition, interface LSI (IL
SI) 34 is an LSI that controls communication between the boat controller 33 and the local CPU 13 (FIG. 1) in the common control shelf 1, and is assumed to operate in slave mode as described later.

FIG. 4 shows the internal configuration of the local CPU card 13 within the common control shelf 1. In FIG. 4, an interface LSI (ILSI) 41 has the same configuration as the interface LSI 34 in FIG. 3, but has a different mode setting input from the outside, and operates in a mask mode as described later. Local memory 42 is local C
The buffer 45 is for storing programs and data for operating the PU (LCEILI) 43.
is for connecting and disconnecting the common bus 15 and the local bus 46 in the local CPU card 13. When the local CPU 43 accesses the common bus 15, the decoder 44 allocates the common bus 15 to the common memory 71 (described later). When the address is detected, the buffer 45 is turned on to connect the common bus 15 and the local bus 46. Note that different addresses are assigned to the local memory 42 and the common memory 71.

Figure 5 shows the main CPU card 1 in the common control shelf 1.
The internal configuration of 1 is shown. As shown in the figure, the main CPU card 11 has almost the same configuration as the local CPU card 13 shown in FIG. 4, and the local memory 51. Main CP
U (Mcpu) 52. Decoder 53. Batsuhua 5
4 and a local bus 55. However, the main CP
Since the U card 11 is not connected to the control highway 3, it does not include an interface LSI.

Although not shown, the application CPU card 12 in the common retractable shelf 1 also has the same configuration as the main CPU card 11 shown in FIG.

FIG. 6 shows the internal configuration of the time switch card 14 in the common control shelf 1, which includes a time switch controller and time switch 61, a decoder 62, and a buffer 63. Time switch card 1°4 is main C
It is accessed only by the PU 52. Specifically, the decoder 62 monitors whether the address on the common bus 15 matches the time switch control address and turns on the buffer 63 only when the address matches. The time switch controller and the time switch 61 are connected to the common bus 15.

FIG. 7 shows the common memory card 16 in the common control shelf 1.
It has an internal configuration including a common memory 71, a decoder 72, and a buffer 73, and the method of accessing the common memory 71 is the same as the access method described above for the time switch card 14 shown in FIG.

Next, referring to the eighth factor, the processor in the common control card in the common control shelf 1, for example, the local CPU 43 in the local CPU card 13 shown in FIG.
A communication method with the processor (boat controller 33) in the line/trunk card 21 shown in FIG. 3 will be explained.

As described above, communication between processors in different shelves is performed by serial transmission under interrupt control.

In FIG. 8, the control highway 3 has a data highway (data input/output Ijl), a frame synchronization signal transmission line, and a data highway clock transmission line,
The PCM highway 4 has a transmission line for a PCM highway clock and a transmission line for a PCM highway frame synchronization signal. Clock generator 47 in local CPU card 13
sends the data highway clock to control highway 3. On the other hand, the line corresponding section 36 in the line/trunk card 21 includes a CODEC, SiC, and the like.

In this embodiment, the interface LSI has two modes depending on the mode setting input: a mask mode that has the function of transmitting data in a time slot that is previously assigned to itself in synchronization with the time slot change point, and a The device used is configured to be able to switch between a slave mode and a slave mode, which has a function of transmitting data only at a time slot address obtained by a slot designation address.

Interface LSI in local CPU card 13
41 operates in mask mode and is inserted between the local CPU and the control highway 3. Data is sent from the interface LSI 41 to the control highway 3 in synchronization with the time slot change point. Furthermore, when receiving data from the interface LSI 34 in the line/trunk card 21,
When the header is detected, it is received and the local CPU
43 as a reception request.

Interface LS in line/trunk card 21
I34 is a boat controller 33 that operates in slave mode and controls input/output of the control highway 3, PCM highway 4, and each boat in the card 21.
Connect with. Data can be sent from this interface LSr34 to the control highway 3 only in the time slot designated by the time slot designation address from the outside. In addition, when receiving the interface LSI 34, the data is received via the control highway 3 after detecting the header, and the received data is valid only when the address of the received data matches the time slot specified address from the outside. Based on the judgment, an interrupt request as a reception request is generated to the boat controller 33.

When the baud 1 to controller 33 receives an interrupt request, they read the received data from the reception register in the interface LSI 34 and control the line/trunk card 21 according to the data. When sending data to the line corresponding section 36, the baud 1 controller 33 writes control data to the line corresponding section control section in the interface LSI 34, and then the interface LSI 34 sends the control data to the line corresponding section 36. .

The status of the line support section 36 or data from subscriber terminals such as the digital telephone 31 are transmitted to the interface LS.
It is periodically fetched into the I10 register of the line support department in the I34. By periodically reading the data in the I10 register, the boat controller 33 detects changes in the state of the line corresponding section 36 or changes the state of the local CPU.
43, the control data for the interface LSI 3
Occupies the transmit register in 4. Thereafter, the interface LSI 34 outputs the contents of the transmission register to the data highway (data output line) of the control highway 3 in the time slot given by the time slot designation address from the outside.

Next, a communication system between the processors in the common control shelf 1, that is, between the processors provided in the common control cards, which is a feature of the present invention, will be explained. For inter-processor communication within the common control shelf 1, each local CPU 4
3 is a main CPU that processes data related to the status of subscriber terminals collected from the affiliated line/trunk card 21 and data from the subscriber terminals to a predetermined level.
52 or application CPU, and main CPU 52 and application C.
There is data transmission for transmitting terminal control data obtained through exchange processing by each PU to the local CPU 43 side.

As described above, communication between processors within the same shelf is achieved by connecting a common memory 16 that can be commonly accessed by each processor to the common bus 15, writing data to be transmitted to this common memory 16, and This is done by reading the data to be received from this common memory 16.

The method of connecting a common memory to a common bus and transmitting data between arbitrary processors via the common memory is well known, for example, as seen in the control according to IEE 796. According to this method, a processor that requires access to a common memory issues a control signal on a common bus, and data transmission is performed by occupying the common bus during the access period. In that case, if accesses by multiple processors conflict, processing is performed based on a predetermined priority order.

In this embodiment, each local CPLj 43 writes the status or dial information data into the common memory 16 each time a status change occurs on the subscriber terminal side and each time dial information is sent from the subscriber terminal. Main C
By periodically polling the contents of the common memory 16, the PU 52 learns of changes in the status of each subscriber terminal and performs processing accordingly. For example, when a call is initiated from a subscriber terminal, it is detected and the call is processed. In this series of call processing routines, the data originally stored in the common memory 16 or the local
When the data written in the common memory 16 via the PU 43 is needed, the common memory 16 is accessed and the data is read and processed. If the control data controlling the subscriber terminal side changes as a result of this processing, the control data is written into the common memory 16.

On the other hand, the local CPL 143 also checks the contents of the common memory 16 in order to determine whether or not a change has occurred in the control data of the subscriber terminal, and to detect the contents of the control data if a change has occurred. Polling regularly.

In this way, data to be transmitted by each processor (main CP (J52゜local CPU 43, etc.)) is stored in the common memory 16.
Communication between these processors is performed by writing data to the common memory 16, polling the contents of the common memory 16 periodically or whenever necessary, and reading data to be received. In this way, there is a difference in performance level between the local CPU 43, the main CPU 52, and the application CPU, and even though data is collected from the local CPU 43 side to the main CPU 52 and the application CPU, the main CPU 52 and the application CPU etc. can execute their own processing programs (for example, exchange processing programs) without interruption, improving processing efficiency.

Also, 〇-Cal CPU (Lcpu) 43. Main C
PU (Mcpu) and application CPU (
Mcpu-L cpu,
L cpu -A cpu, M cpu -A cp
Since communication between users can be performed flexibly, it is possible to provide more advanced services while maintaining real-time performance.

Further, as shown in FIG. 9, the local CPU 43 located between the serial transmission area and the parallel transmission area moves from the physical level, which is the processing level of the line/trunk card 21, to the logical level, which is the processing level of the local CPU 43. By performing this conversion, the main CPLI 52 can handle input and output at the maximum abstraction level. In addition, FIG. 9 shows line/1 to rank cards 21. A specific example of the functions of the local CPU 43 and the main CPU 52 and communication data between these processors is shown. In this way, the local CPU 43 can control the transmission of command data between subscriber terminals and trunks, and there is no need for the main CPLj 52 to manage command data.
There are advantages in that the load on U52 is reduced, changes, additions, etc. are facilitated, expandability is improved, and productivity is also increased.

Next, the internal configuration of the interface LSI (34, 41, etc.) will be explained with reference to FIG. As mentioned above, the interface LSI is the control highway 3
A mask mode that has the function of sending data to the internal data highway in synchronization with the time slot change point, and an address that matches the address given by the time slot specified address from the outside. It is configured so that it can be switched to slave mode, which is possible only in the time slots of . A control unit that switches the master/slave mode based on a mode setting input is located in the data highway transmitting/receiving unit 101.

In FIG. 10, a data highway transmitting/receiving section 101 operates based on a frame synchronization signal DHFS and a data highway clock DHCLK, and a data highway transmitting register 102 and a data highway receiving register 10
Data is transmitted and received between the data input lines DHIN and 15 and the data output line DHOUT via the data input lines DHIN and 15 and the data output line DHOUT. In this case, as described above, the timing of transmission and reception differs depending on the mode. That is, in the mask mode, the data in the transmission register 102 is sent out in synchronization with the change point of the time slot, and in the case of reception, the data is received after header detection and stored in the reception register 103. In slave mode, the data in the transmission register 102 is transmitted only in the time slot whose address matches the time slot designation address from the outside, and when receiving data, the data is received after detecting the header, and the data is transmitted according to the time slot designation from the outside. Data is stored in the reception register 103 only when the address matches the address in the received data.

The CPU interface control unit 104 decodes the address data from the data bus and outputs the ink-face L.
Send data to each block within SI.

The line correspondence unit control unit 105 has an input register 106. It has an output register 107 and an input/output designation register 108 for designating an input/output mode, and is connected to the line correspondence section 36 (FIG. 8).

The PCM time slot control unit 109 counts the number of time slots using the PCM frame synchronization MFS and the PCM clock PCMCLK, and controls the boat controller 3.
3, the PCM time slot address is compared with the PCM time slot address set in the specification register 110, and when they match, control is performed to provide frame synchronization to the GODEC.

In the electronic exchange of this embodiment, when transmitting the same data from the local CPU 43 to a plurality of boat controllers 33, those boat controllers 33 communicate with the connected slave mode interface 5I34.
A common group address is assigned to each group, and data is transmitted using this group address. This group address has meaning as a collection of addresses of multiple interface LSIs 34, and each interface LSI
It is registered in advance in SI34.

Note that there are two methods for transmitting the same data from the local CPU 43 to multiple boat controllers 33: (1) sending normal calls to each port controller in sequence and transmitting the same data; and (1) transmitting the same data to the boat controllers 33 as described above. Multiple interface LSI3 connected to
A possible method is to add transmission data to a group address representing group address No. 4 and transmit the data. Although method (2) is simple, it requires sequentially transmitting addresses and transmission data to each boat controller individually. In contrast,
In method (2), transmission can be performed between the local CPU 43 and a plurality of boat controllers 33 at the same time, so the time required for transmission is retraced, and the local CPU
The load on U43 is also reduced.

Next, the transmission signal format in this embodiment is
This will be explained with reference to the figures. As shown in the figure, one frame is formed by a header, address, control data, and information data. Address is a single port controller 33
An individual address for transmitting data individually to multiple port controllers 33, a broadcast address for transmitting the same data to multiple port controllers 33, and a simultaneous broadcast address for transmitting the same data to all port controllers 33. Can be divided. Information (referred to as an identifier) indicating the distinction between an individual address, a broadcast address, and a simultaneous broadcast address is the upper part (MSB side) in the address format shown in the lower part of Figure 11.
2 bits are used.

In the case of an individual address, the upper 2-bit identifier indicating the distinction of this address is followed by a single interface L.
An SI address (ILSI address) is added, and in the case of broadcasting, a group address indicating an arbitrarily designated group is added.

Now, a single group address (#
Assuming that A) represents the address information of multiple interface LSIs, when transmitting the same data from the local CPU 43 to the interface LSIs 34 connected to multiple port controllers 33, the information shown in FIG. As shown above, set the identifier ``10'' in the upper two bits of the address format, and continue with 71~
#A may be added as the representative address of #n.

As a result, data from the local CPU 43 is sent to the interface LSI 34 connected to the plurality of ports 1 to controller 33 by - times of transmission operations.

The interface LSI 34 to which the data from the local CPU 43 has been sent extracts a group address from the data received via the data highway and compares it with a group address registered in advance.

As a result of this comparison, when both addresses match, the information data in the transmission data is received. Note that in FIG. 12, group addresses #A and #B correspond to the line/trunk card 21 in which the interface LSI 34 is installed.
indicates that the card is connected to a standard telephone 1fl (STT). This line/trunk card can receive transmitted data from local CPU 43, but other line/trunk cards cannot receive the same data.

FIG. 13 shows the configuration of an address processing circuit provided in the line/trunk 21 for performing the above-mentioned processing, and the upper two bits (identifier) of the received address are sent to the E and S terminals ( control input terminal). The A and 81 children (data input terminals) of the selector 131 are supplied with the group address stored in the memory 132 in the line/1-rank 21 and the LSI address assigned to the country interface LSI 34, respectively. From the selector 131, (E, S) = (0
,O)6') and 8L8171'res, but also (E.

When S)=(1, O), each group address is output and supplied to the first input terminal of the comparator 133. Address information following the upper two bits of the received address is supplied to the second input terminal of the comparator 133, and when the first and second input terminals match, the output of the comparator 133 becomes II II II. .

On the other hand, the information on the upper 2 bits of the received address is further input to the 2-input AND gate 134, and the upper 2 bits are "
11", that is, whether the received address is a broadcast address. This AND gate 134
The output of the comparator 133 and the output of the comparator 133 are input to the two-man OR gate 135. The "'1°" output of the OR gate 135 becomes a reception request to the port controller 33.

That is, the interface L on which the receiving address was received
Receives the information data following the address when it is an individual address (LSI address) corresponding to the SI, when it is a broadcast address (group address) that includes the received interface LSI, and when it is a -simultaneous broadcast address. A request is made to do so.

Such a configuration is effective when a program is stored in each port, such as when starting up the system when the system goes down. That is, since the time required to load programs, etc. is determined only by the number of programs to be loaded, regardless of the board size, the time required to start up the system is significantly reduced.

[Effect of the invention 1] According to the present invention, communication between a plurality of processors connected to a common bus can be carried out efficiently without interfering with the work being executed by processors other than the sender, and the highly advanced multiprocessor It is possible to provide an electronic exchange that can provide services while maintaining real-time performance.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a schematic configuration of an electronic exchange according to an embodiment of the present invention, Fig. 2 is a diagram showing a shelf lamination groove path of the electronic exchange, and Fig. 3 is a diagram showing lines /1 to /1 in the embodiment. FIG. 4 is a diagram showing the internal configuration of the local CPU card in the same embodiment. FIG. 5 is a diagram showing the internal configuration of the main CPU card in the same embodiment. FIG. 7 is a diagram showing the internal configuration of the time switch card in the same embodiment. FIG. 8 is a diagram showing the internal configuration of the common memory card in the same embodiment. FIG. /
Diagram for explaining the communication method in the trunk card, No. 9
The figure shows a specific example of entertainment distribution and mutual communication data between the line/trunk card, local CPU, and main CPU, FIG. 10 is a diagram showing the internal configuration of the interface LSI in the same embodiment, and FIG. 11 is the same. FIG. 12 is a diagram showing a transmission signal format for explaining the data transmission method from the local CPU to the boat controller in the line/1 to rank cards in the embodiment; FIG. 12 is a conceptual diagram for explaining the data transmission method; FIG. 13 is a diagram showing the configuration of an address receiving circuit in a line/trunk card used to implement the data transmission method. 1...Common control shelf, 2a-2n...Line/
Trunk shelf, 3...control highway,
4... PCM highway, 11... Main CPU card, 12... Application CPU card, 13
...Local CPU card, 14...Time switch card, 15...Common bus, 16...Common memory, 21...Line/trunk card, 33...Port controller, 34.41... - Interface LS1.43... Local CPU, 52... Main CPU, 71... Common memory. Applicant's agent Patent attorney Takehikotomi Suzue

Claims (2)

[Claims] (1) In a multiprocessor-controlled electronic switching system in which multiple processors are connected to a common bus, a common memory commonly used by each processor is connected to the common bus, and a local bus is connected via a buffer. An electronic exchange characterized in that a local memory storing programs and data for operating the processors is connected to the processor, and communication between the processors connected to the common bus is performed via the common bus, the common memory, and the buffer. (2) When the buffer detects that an address assigned to the common memory is issued from a processor connected via the local bus, the buffer connects the local bus and the common bus. Electronic switching equipment according to scope 1.