JPS62155694A - Electronic exchange - Google Patents

Abstract

PURPOSE:To reduce a laying cost by transmitting data serially on a data highway by an interruption control when the communication is carried out between processors packaged in different shelves, for instance, between the processor in a line/trunk shelf and the processor in a common control shelf. CONSTITUTION:The communication between the processors in the same shelf is carried out by connecting a common memory 16 which can be made access commonly by the respective processors to a common bus 15, writing the data to be transmitted in this common memory 16 and reading the data to be received from this common memory 16. Respective local CPUs 43, at every time when the change in a state is produced in a subscriber's terminal side and at every time when dial information is fed from the subscriber's terminal, writes the state or the data of the dial information in the common memory 16. In a main CPU 52, by polling the contents of the common memory 16 periodically, the change in the state of the respective subscriber's terminals is understood and a processing according thereto is performed. For instance, when a calling is generated from the subscriber's terminal, it is detected and a calling processing is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a distributed control electronic switching system, and particularly to a communication system between processors.

(Prior Art) A distributed control type electronic exchange □, in which a plurality of processors are arranged in a distributed manner to improve the overall function and processing capacity, is attracting attention. As such a distributed control type electronic switching system, the present inventors have developed a system that includes subscriber terminals such as telephones and data terminals, lines connected to central office lines or dedicated lines, and multiple lines/trunk shelves equipped with trunk cards. proposed an electronic switching system in which common control shelves equipped with common control cards that control switching processing can be stacked according to the scale of the line, processors are placed in each shelf, and communication is performed between these processors. are doing.

In such electronic exchanges, communications between processors installed in different shelves, particularly between processors in the line/trunk shelves and processors in the common control shelf, must occur in real time. For this purpose, communication between processors can be performed using parallel transmission, but this increases the number of cables connecting the shelves, which increases the cable Pi installation cost and reduces reliability. .

On the other hand, when communicating between different processors within the same shelf, for example, a common control shelf, if serial transmission is performed using interrupt control, a complex circuit for interrupt control is required for each shelf, so the entire exchange There is a problem in that the amount of hardware increases and the exchange process is interrupted every time separate control is performed, resulting in a decrease in processing efficiency.

(Problems to be Solved by the Invention) In this electronic switching system in which line/trunk shelves and common control shelves are arranged in W4 layers and processors are distributed in each shelf, communication between processors in different shelves is The major challenges are to perform real-time communication without increasing the number of wires between shelves, and to perform communication between processors within the same shelf without increasing the hardware and without reducing the efficiency of exchange processing. It becomes.

The present invention was made to solve these problems, and it is possible to reduce the number of wires between shelves as much as possible in an electronic switching system using a distributed control method with a structure in which line/trunk shelves and common control shelves are stacked. To provide an electronic exchange center capable of communicating in real time between processors in different shelves, and also capable of communicating between processors in the same shelf without increasing hardware or reducing efficiency of exchange processing. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a plurality of line/trunk shelves equipped with line/trunk cards connected to subscriber terminals and central office lines or leased lines, and which controls switching processing. In a distributed control type electronic switching system that is configured by stacking common control shelves that are equipped with common control cards, and in which processors are distributed within each shelf, communication between processors installed on different shelves is serially controlled by interrupt control. Communication between processors installed on the same shelf is performed by transmission, and the sending processor writes the data to be sent to a common memory connected to a common bus, and the sending destination processor polls the common memory to achieve parallel communication. It is characterized by being carried out by transmission.

(Operation) When communicating between processors installed in different shelves, for example, a processor in the line 7' trunk shelf and a processor in the common control shelf,
Data is transmitted serially on the data highway using interrupt control. Therefore, fewer wires are needed to connect the shelves, greatly reducing the installation cost and increasing reliability.

On the other hand, when communicating between processors within the same shelf, for example within a common control shelf, when data to be transmitted is generated, the sending processor immediately transmits the data in parallel via the common bus and stores it in parallel in the common memory. The destination processor periodically polls this common memory and reads necessary data in parallel via the common bus as appropriate. Therefore, like when using interrupt control? ! This eliminates the need for expensive hardware and improves processing efficiency.

(Embodiment) FIG. 1 is a schematic configuration diagram of an electronic exchange according to an embodiment of the present invention, in which a common control shelf 1 and a plurality of line/trunk shelves 2a to 2n are stacked as shown in FIG. It has a structure.

The common control shelf 1 includes a main CPU (Mcpu) card 11 that handles exchange processing, maintenance, etc., and an application CPU (Acpu) card that handles various applications such as call management, messaging, and daily communication.
) card 12, a local CPU that controls communication between the main CPU card 11, application CPU card 12, and line/trunk (L/T) card 21, and performs input/output level conversion in software.
(Lcpu) card 13, and a time switch (TSW) card 14 that performs time division time slot conversion.
A card (card-shaped circuit device) constituting a common control unit such as the following is mounted. In the present invention, the various cards 11 to 14 in the common control shelf 1 are collectively referred to as a common control card. Further, the processors in each common control card 11 to 14 are connected to a common memory 1 connected to a common bus 15.
They can communicate with each other via 6.

On the other hand, inside the line/trunk shelves 2a to 2n, there are line/trunk shelves to which subscriber terminals such as telephone frozen data terminals are connected.
Trunk (L/T) cards 21 are installed according to the number of lines. between the common control shelf 1 and the line/trunk shelves 2a to 2n), a data highway for transmission from the local CPU card 13 to the line/trunk card 21 and a data highway for reception from the line/trunk card 21 to the local CPU card 13. A control highway 3 for serial transmission, including a control highway 3 for serial transmission, and a PCM highway 4 for PCM time slot input connected between the time switch card 14 and the line/trunk card 21.

Next, each part of FIG. 1 will be explained in detail.

FIG. 3 shows the internal configuration of the line/trunk card 21, particularly the line/trunk card connected to the digital telephone 31. As shown in FIG. In FIG. 3, a digital telephone LSI (DTLSf) 32 is a digital telephone Akebono 31.
This is an LSI that controls communication between the line/trunk card and a port controller (PC) 33 consisting of a CPLJ that controls the line/trunk card and the telephone set, office line, etc. connected to the line/trunk card. Also, interface LSI<ILS
I) 34 is an LSI that controls communication between the port controller 33 and the local CPU 13 (FIG. 1) in the common control shelf 1, and is assumed to operate in slave mode as described later.

FIG. 4 shows the internal configuration of the local CPU card 13 within the common control shelf 1. In FIG. 4, an interface LSI (ILSI) 41 has the same configuration as the interface LSI 34 in FIG. 3, but has a different mode setting input from the outside, and operates in a mask mode as described later. Local memory 42 is local C
The buffer 45 is used to store programs and data for operating the PLJ (Lcpu) 43, and the buffer 45 is used to connect and disconnect the common bus 15 and the local bus 46 in the local CPU card 13. When a certain local CPU 43 accesses the common bus 15, when the decoder 44 detects an address assigned to the common memory 71 (described later), the buffer 45 is turned on to connect the common bus 15 and the local bus 46. Note that different addresses are assigned to the local memory 42 and the common memory 71.

Figure 5 shows the main CPU card 1 in the common control shelf 1.
The internal configuration of 1 is shown. As shown in the figure, the main CPU card 11 has almost the same configuration as the local CPU card 13 shown in FIG. 4, and the local memory 51. Main CPU
(Mcpu) 52. Decoder 53. Buffer 54
and a local bus 55. However, the main CPU
Since the card 11 is not connected to the controller 1 to the roll highway 3, it does not include an interface LSI.

Although not shown, the application CPU card 12 in the common control shelf 1 also has the same configuration as the main CPU card 11 shown in FIG.

FIG. 6 shows the internal configuration of the time switch card 14 in the common control shelf 1, which includes a time switch controller and time switch 61, a decoder 62, and a buffer 63. The decoder 62 monitors whether or not the address on the common bus 15 matches the address for time switch control, and only when the address matches, the buffer 63
is turned on to connect the time switch controller and time switch 61 to the common bus 15.

FIG. 7 shows the common memory card 16 in the common control shelf 1.
The internal structure includes a common memory 71, a decoder 72, and a buffer 173, and the method for accessing the common memory 71 is the same as the above-described access method for the time switch card 14 shown in FIG.

Next, referring to FIG. 8, the processors in the common control card in the common control shelf 1, for example, the local CPU 43 in the local CPU card 13 shown in FIG. 4, and the line/trunk card 21 shown in FIG. The communication method with the processor (port controller 33) within the port will be explained.

As mentioned above, communication between processors in these different shelves is performed by serial transmission using interrupt 1ill III.

In FIG. 8, the control highway 3 has a data highway (data input/output line), a frame synchronization signal transmission line, and a data highway clock transmission line,
The M highway 4 has a transmission line for a PCM highway clock and a transmission line for a PCM highway frame synchronization signal.

A clock generator 47 in the local CPU card 13 sends a data highway clock to the control highway 3. On the other hand, the line corresponding section 36 in the line/trunk card 21 includes a CODEC, 5LIC, and the like.

In this embodiment, the interface LSI has two modes depending on the mode setting input: a mask mode that has the function of transmitting data in a time slot that is previously assigned to itself in synchronization with the time slot change point, and a The device used is configured so that it can be switched to a slave mode, which has the function of transmitting data only at a time slot address obtained by a slot designated address.

Interface LSI in local CPU card 13
41 operates in mask mode and is inserted between the local CPU and the control highway 3. Data is sent from the interface LSI 41 to the control highway 3 in synchronization with the time slot change point. Furthermore, when receiving data from the interface LSI 34 in the line/trunk card 21,
When the header is detected, it is received and the local CPU
43 as a reception request.

Interface LS in line/trunk card 21
The I34 operates in slave mode and controls input/output of the control highway 3, PCM highway 4, and each boat in the card 21.
Connect with 3. Sending of data from this interface LSI 34 to the control highway 3 is possible only in the time slot designated by the time slot designation address from the outside. In addition, when receiving the interface LSI 34, after detecting the header, the data is received via the control highway 3,
Only when the address of the received data matches the time slot designation address from the outside, the received data is determined to be valid and an interrupt request as a reception request is generated to the port controller 33.

When the port controller 33 receives an interrupt request, it reads the received data from the reception register in the interface LSI 34 and controls the line/1-rank card 21 in accordance with the data. When sending data to the line corresponding section 36, the port controller 33 writes control data to the line corresponding section control section in the interface LSI 34, and then the interface LSI 34 sends the control data to the line corresponding section 36.

The status of the line support section 36 or data from subscriber terminals such as the digital telephone 31 are transmitted to the interface LS.
It is periodically fetched into the ■/○ register of the line correspondence section control section in the I34. By periodically reading the data in the I10 register, the boat controller 33 detects changes in the state of the line corresponding section 36 or changes the state of the local CPU 43.
control data for is written to the transmission register in the interface LSI 34. After this, interface L
The SI 34 transfers the contents of the transmission register to the data highway (
data output line).

Next, a communication method between each processor in the common control shelf 1, that is, a communication method between processors provided in each common control card will be described. For inter-processor communication within the common control shelf 1, the main CPLI 52 uses data related to the status of subscriber terminals collected by each local CPtJ 43 from the affiliated line/trunk cards 21 and data processed from the subscriber terminals to a predetermined level. Alternatively, data transmission to the application CPU and terminal control data obtained through exchange processing by the main CPU 52 and the application CPJJ are sent to the local CPU 43.
There is data transmission to convey information to the other side.

As described above, communication between processors within the same shelf is achieved by connecting a common memory 16 that can be commonly accessed by each processor to the common bus 15, writing data to be transmitted to this common memory 16, and This is done by reading the data to be received from this common memory 16.

The method of connecting a common memory to a common bus and transmitting data between arbitrary processors via the common memory is well known, for example, as seen in the control according to IEE 796. According to this method, a processor that requires access to a common memory issues a control signal on a common bus, and data transmission is performed by occupying the common bus during the access period. In that case, if accesses by multiple processors conflict, processing is performed based on a predetermined priority order.

In this embodiment, each local CPU 43 writes the status or dial information data into the common memory 16 each time a status change occurs on the subscriber terminal side and each time dial information is sent from the subscriber terminal. Main CP
By periodically polling the contents of the common memory 16, U52 learns of changes in the status of each subscriber terminal and performs processing accordingly. For example, when a call is initiated from a subscriber terminal, it is detected and the call is processed. In this series of call processing routines, data originally stored in the common memory 16 or from the subscriber terminal to the local CP
When the data written in the common memory 16 via U43 is needed, the common memory 16 is accessed and the data is read and processed. If the control data controlling the subscriber terminal side changes as a result of this processing, the control data is written into the common memory 16.

On the other hand, the local CPU 43 also checks the contents of the common memory 16 in order to determine whether or not a change has occurred in the control data of the subscriber terminal, and to detect the contents of the control data if a change has occurred. Polling regularly.

In this way, data to be transmitted by each processor (main CPtJ52, local CPU43, etc.) is stored in the common memory 16.
Communication between these processors is performed by writing data to the common memory 16, polling the contents of the common memory 16 periodically or whenever necessary, and reading data to be received. In this way, although there is a difference in the functional level between the local CPU 43, the main CPU 52, and the application CPLI, and data is collected from the local CPU 43 side to the main CPU 52 and the application CPLI, the main CPU 52, the application CPLI, etc. can execute its own processing program (for example, exchange processing program) without interruption, improving processing efficiency.

Also, local CPU (Lcpu) 43. Main C
PU (Mcpu) and application CPU (
ACDtl) are connected via the common memory 16 on the common bus 15, so that the Mcpu-l
, l cl) u −A cpu, v cpu −A
C1) Since communications between u can be performed flexibly, it is possible to provide more advanced services while maintaining real-time performance.

Further, as shown in FIG. 9, the local CPU 43 located between the serial transmission area and the parallel transmission area moves from the physical level, which is the processing level of the line/trunk card 21, to the logical level, which is the processing level of the local CPU 43. By performing this conversion, the main CPU 52 can handle input and output at the highest level of abstraction. Note that FIG. 9 shows the line/trunk card 21. local CP
A specific example of the performance of each of the U43 and the main CPU 52 and communication data between these processors is shown. In this way, the local CPU 43 can control command data transmission between subscriber terminals and trunks, and there is no need for the main CPLI 52 to manage command data.
This has the advantage that the load on 2 is reduced, changes, additions, etc. are facilitated, expandability is improved, and productivity is also increased.

Next, the internal configuration of the interface LSI (34, 41, etc.) will be explained with reference to FIG. As mentioned above, the interface 81 is the control highway 3
A mask mode that has the function of sending data to the internal data highway in synchronization with the time slot change point, and an address that matches the address given by the time slot specified address from the outside. It is configured so that it can be switched to slave mode, which is possible only in the time slots of . A control unit that switches the master/slave mode based on a mode setting input is located in the data highway transmitting/receiving unit 101.

In FIG. 10, a data highway transmitter/receiver 101 operates using a frame synchronization signal DI-IFs and a data highway clock DHCLK, and connects a data input line DI-(IN and a data output Data is sent and received to and from IDHOUT. In this case, the timing of sending and receiving differs depending on the mode as described above. In other words, in the mask mode, the transmission register 102 is synchronized with the changing point of the time slot.
In the case of reception, the data is received after detecting the header and stored in the reception register 103. In slave mode, the data in the transmission register 102 is transmitted only in the time slot whose address matches the time slot designation address from the outside, and when receiving data, the data is received after detecting the header, and the data is transmitted according to the time slot designation from the outside. Data is stored in the reception register 103 only when the address matches the address in the received data.

The CPU interface control unit 104 decodes address data from the data bus, and
Send data to each block within SI.

The line correspondence unit control unit 105 has an input register 106. It has an output register 107 and an input/output designation register 108 for designating an input/output mode, and is connected to the line correspondence section 36 (FIG. 8).

The PCM time slot control unit 109 counts the number of time slots using the PCM frame synchronization PCMFS and the PCM clock PCMCLK, and controls the port controller 3.
3, the address is compared with the PCM time slot address set in the PCM time slot designation register 110, and when they match, control is performed to provide frame synchronization to the GODEC.

In the electronic exchange of this embodiment, when transmitting the same data from the local CPU 43 to a plurality of port controllers 33, the slave mode interface LSI 34 to which those port controllers 33 are connected
A common group address is given to each group, and data is transmitted using this group address. This group address has meaning as a collection of addresses of multiple interface LSIs 34, and each interface LSI
It is registered in advance in SI34.

Note that there are two methods for transmitting the same data from the local CPIJ 43 to multiple boat controllers 33: (1) sending normal calls to each boat controller in sequence and transmitting the same data; (2) transmitting the same data to each boat controller in sequence, and (2) transmitting the same data to each boat controller 33 as described above. Multiple interface LSI3
A possible method is to add transmission data to a group address representing group address No. 4 and transmit the data. Although method (2) is simple, it requires sequentially transmitting addresses and transmission data to each boat controller individually. On the other hand,
In the method (2), transmission can be performed between the local CPU 43 and a plurality of boat controllers 33 at the same time, so the time required for transmission is shortened, and the local CPU 43
The load on U43 is also reduced.

Next, the transmission signal format in this embodiment is
This will be explained with reference to the figures. As shown in the figure, one frame is formed by a header, address, control data, and information data. The address is a single pomy controller 3
3, an individual address for transmitting data individually to a plurality of boat controllers 33, a broadcast address for transmitting the same data to multiple boat controllers 33, and a simultaneous broadcast address for transmitting the same data to all boat controllers 33. It can be divided into For information (referred to as an identifier) indicating the distinction between an individual address, a broadcast address, and a broadcast address, the upper two bits (MSB side) in the address format shown in the lower part of FIG. 11 are used.

In the case of an individual address, the upper 2-bit identifier indicating the distinction of this address is followed by a single interface L.
An SI address (ILSI address) is added, and in the case of broadcasting, a group address indicating an arbitrarily designated group is added.

Now, a single group address (#
Assuming that A) represents the address information of multiple interface LSIs, when transmitting the same data from the local CPU 43 to the interfaces 18134 connected to multiple boat controllers 33, the information shown in FIG. As shown above, set the identifier "10" in the upper two bits of the address format, and continue with #1.
#A may be added as a representative address of ~#n.

As a result, data from the local CPU 43 is sent to the interface LSI 34 connected to the plurality of boat controllers 33 by - times of transmission operations.

The interface LSI 34 to which the data from the local CPU 43 has been sent extracts a group address from the data received via the data highway and compares it with a group address registered in advance.

As a result of this comparison, when both addresses match, the information data in the transmission data is received. In addition, in FIG. 12, group addresses #A and #B are 21 within the line/trunk 21 where the interface LSI 34 is provided.
is a card connected to a standard telephone set (STT). This line/trunk card can receive transmitted data from the local CPU 43, but other line/trunk cards cannot receive the same data.

FIG. 13 shows the configuration of an address processing circuit provided in the line/trunk 21 for performing the above-mentioned processing, and the upper two bits (identifier) of the received address are sent to the E and S terminals ( control input terminal). The A and S terminals (data input terminals) of the selector 131 are supplied with the group address stored in the memory 132 in the insert/trunk 21 and the LSI address assigned to the individual interface LSI 34, respectively. From the selector 131, (E, S) = (0,
0>, the LSI address is also (E.

When S)=(1, O), each group address is output and supplied to the first input terminal of the comparator 133. Address information following the upper two bits of the received address is supplied to the second input terminal of the comparator 133, and when the values at these first and second input terminals match, the output of the comparator 133 becomes 1''.On the other hand, The information on the upper two bits of the received address is further input to the two-person AND gate 134, and it is determined whether the upper two bits are "'11", that is, whether the received address is a simultaneous broadcast address. The output of 134 and the output of comparator 133 are input to the two-man OR gate 135. The ``1'' output of the OR gate 135 becomes a reception request to the port controller 33. That is, the reception address is an individual address corresponding to the received interface LSI. (LSI address), a broadcast address (group address) that includes the received interface LSI, and - simultaneous broadcast address, a request to receive information data following the address is issued. It will be done.

Such a configuration is effective when storing programs in each boat, such as when starting up the system when the system goes down. In other words, since the time required for loading programs etc. is determined only by the number of programs to be loaded, regardless of the port specification, the time required for starting up the system is significantly reduced.

[Effects of the Invention] According to the present invention, it is possible to perform communication between processors in the shelves in real time without increasing the number of wires between stacked storage/trunk shelves or common control shelves. Furthermore, it is possible to provide a distributed control type electronic exchange that allows communication between processors within the same shelf without increasing hardware or reducing the efficiency of exchange processing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of an electronic exchange according to an embodiment of the present invention, FIG. 2 is a diagram showing a stacked shelf structure of the electronic exchange, and FIG. 3 is a diagram showing a line/trunk card in the same embodiment. FIG. 4 is a diagram showing the internal configuration of the local CPU card in the same embodiment. FIG. 5 is a diagram showing the internal configuration of the main CPU card in the same embodiment. FIG. 6 is a diagram showing the internal configuration of the main CPU card in the same embodiment. FIG. 7 is a diagram showing the internal configuration of the common memory card in the same embodiment, and FIG. 8 is a diagram showing the internal configuration of the time switch card in the same embodiment.
FIG. 9 is a diagram for explaining the communication method within the I-rank card; FIG. FIG. 11 is a diagram showing the internal configuration of the interface LSI in the same embodiment, and FIG. FIG. 12 is a conceptual diagram for explaining the data transmission method, and FIG. 13 is a diagram showing the configuration of an address receiving circuit in a line/trunk card used to implement the data transmission method. 1...Common control shelf, 2a-2n...Line 2
・'Trunk shelf, 3...Control highway, 4...PC~1 highway, 11...Main C
PU card, 12...Application CPU card, 13...Local CPU card, 14...Time switch card, 15...Common bus, 16...Common bus, 21...Line/trunk Card, 33...
・Port 1 Hecon [・Roller, 34.41...Interface LS L 43...Local CPU, 52
...Main CPU171...Common memory. Applicant's agent Patent attorney Takehiko Suzue Q Yar 薯V

Claims (2)

[Claims] (1) Constructed by stacking multiple line/trunk shelves equipped with line/trunk cards connected to subscriber terminals and central office lines or leased lines, and a common control shelf equipped with common control cards that control switching processing. Furthermore, in a distributed control type electronic exchange in which processors are distributed within each shelf, communication between processors installed on different shelves is performed by serial transmission using interrupt control, and communication between processors installed on the same shelf is An electronic switching system characterized in that communication is performed in parallel by a transmitting processor writing data to be transmitted in a common memory connected to a common bus, and a transmitting processor polling the common memory. (2) A patent claim in which one of the different shelves in which communication between processors is performed by serial transmission is a common control shelf, the other is a line/trunk shelf, and the shelf in which communication between processors is performed by parallel transmission is a common control shelf. The electronic switching equipment according to item 1 in the scope of .